1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Device tree for the Tolino Shine 2 HD ebook reader 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Name on mainboard is: 37NB-E60QF0+4A2 or 37NB-E60QF0+4A3 6*4882a593Smuzhiyun * Serials start with: E60QF2 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Copyright 2020 Andreas Kemnade 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/dts-v1/; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 14*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 15*4882a593Smuzhiyun#include "imx6sl.dtsi" 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun/ { 18*4882a593Smuzhiyun model = "Tolino Shine 2 HD"; 19*4882a593Smuzhiyun compatible = "kobo,tolino-shine2hd", "fsl,imx6sl"; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun chosen { 22*4882a593Smuzhiyun stdout-path = &uart1; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun gpio_keys: gpio-keys { 26*4882a593Smuzhiyun compatible = "gpio-keys"; 27*4882a593Smuzhiyun pinctrl-names = "default"; 28*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_gpio_keys>; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun cover { 31*4882a593Smuzhiyun label = "Cover"; 32*4882a593Smuzhiyun gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; 33*4882a593Smuzhiyun linux,code = <SW_LID>; 34*4882a593Smuzhiyun linux,input-type = <EV_SW>; 35*4882a593Smuzhiyun wakeup-source; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun fl { 39*4882a593Smuzhiyun label = "Frontlight"; 40*4882a593Smuzhiyun gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; 41*4882a593Smuzhiyun linux,code = <KEY_BRIGHTNESS_CYCLE>; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun home { 45*4882a593Smuzhiyun label = "Home"; 46*4882a593Smuzhiyun gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; 47*4882a593Smuzhiyun linux,code = <KEY_HOME>; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun power { 51*4882a593Smuzhiyun label = "Power"; 52*4882a593Smuzhiyun gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; 53*4882a593Smuzhiyun linux,code = <KEY_POWER>; 54*4882a593Smuzhiyun wakeup-source; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun leds: leds { 59*4882a593Smuzhiyun compatible = "gpio-leds"; 60*4882a593Smuzhiyun pinctrl-names = "default"; 61*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_led>; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun on { 64*4882a593Smuzhiyun label = "tolinoshine2hd:white:on"; 65*4882a593Smuzhiyun gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 66*4882a593Smuzhiyun linux,default-trigger = "timer"; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun memory@80000000 { 71*4882a593Smuzhiyun device_type = "memory"; 72*4882a593Smuzhiyun reg = <0x80000000 0x20000000>; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun reg_wifi: regulator-wifi { 76*4882a593Smuzhiyun compatible = "regulator-fixed"; 77*4882a593Smuzhiyun pinctrl-names = "default"; 78*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_wifi_power>; 79*4882a593Smuzhiyun regulator-name = "SD3_SPWR"; 80*4882a593Smuzhiyun regulator-min-microvolt = <3000000>; 81*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 82*4882a593Smuzhiyun gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun wifi_pwrseq: wifi_pwrseq { 86*4882a593Smuzhiyun compatible = "mmc-pwrseq-simple"; 87*4882a593Smuzhiyun pinctrl-names = "default"; 88*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_wifi_reset>; 89*4882a593Smuzhiyun post-power-on-delay-ms = <20>; 90*4882a593Smuzhiyun reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun}; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun&i2c1 { 95*4882a593Smuzhiyun pinctrl-names = "default","sleep"; 96*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c1>; 97*4882a593Smuzhiyun pinctrl-1 = <&pinctrl_i2c1_sleep>; 98*4882a593Smuzhiyun status = "okay"; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun /* TODO: embedded controller at 0x43 (driver missing) */ 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun}; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun&i2c2 { 105*4882a593Smuzhiyun pinctrl-names = "default","sleep"; 106*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c2>; 107*4882a593Smuzhiyun pinctrl-1 = <&pinctrl_i2c2_sleep>; 108*4882a593Smuzhiyun clock-frequency = <100000>; 109*4882a593Smuzhiyun status = "okay"; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun zforce: touchscreen@50 { 112*4882a593Smuzhiyun compatible = "neonode,zforce"; 113*4882a593Smuzhiyun pinctrl-names = "default"; 114*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_zforce>; 115*4882a593Smuzhiyun reg = <0x50>; 116*4882a593Smuzhiyun interrupt-parent = <&gpio5>; 117*4882a593Smuzhiyun interrupts = <6 IRQ_TYPE_EDGE_FALLING>; 118*4882a593Smuzhiyun vdd-supply = <&ldo1_reg>; 119*4882a593Smuzhiyun reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 120*4882a593Smuzhiyun x-size = <1072>; 121*4882a593Smuzhiyun y-size = <1448>; 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun /* TODO: TPS65185 PMIC for E Ink at 0x68 */ 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun}; 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun&i2c3 { 129*4882a593Smuzhiyun pinctrl-names = "default"; 130*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c3>; 131*4882a593Smuzhiyun clock-frequency = <400000>; 132*4882a593Smuzhiyun status = "okay"; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun ricoh619: pmic@32 { 135*4882a593Smuzhiyun compatible = "ricoh,rc5t619"; 136*4882a593Smuzhiyun pinctrl-names = "default"; 137*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_ricoh_gpio>; 138*4882a593Smuzhiyun reg = <0x32>; 139*4882a593Smuzhiyun interrupt-parent = <&gpio5>; 140*4882a593Smuzhiyun interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 141*4882a593Smuzhiyun system-power-controller; 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun regulators { 144*4882a593Smuzhiyun dcdc1_reg: DCDC1 { 145*4882a593Smuzhiyun regulator-name = "DCDC1"; 146*4882a593Smuzhiyun regulator-min-microvolt = <300000>; 147*4882a593Smuzhiyun regulator-max-microvolt = <1875000>; 148*4882a593Smuzhiyun regulator-always-on; 149*4882a593Smuzhiyun regulator-boot-on; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun regulator-state-mem { 152*4882a593Smuzhiyun regulator-on-in-suspend; 153*4882a593Smuzhiyun regulator-suspend-max-microvolt = <900000>; 154*4882a593Smuzhiyun regulator-suspend-min-microvolt = <900000>; 155*4882a593Smuzhiyun }; 156*4882a593Smuzhiyun }; 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun /* Core3_3V3 */ 159*4882a593Smuzhiyun dcdc2_reg: DCDC2 { 160*4882a593Smuzhiyun regulator-name = "DCDC2"; 161*4882a593Smuzhiyun regulator-always-on; 162*4882a593Smuzhiyun regulator-boot-on; 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun regulator-state-mem { 165*4882a593Smuzhiyun regulator-on-in-suspend; 166*4882a593Smuzhiyun regulator-suspend-max-microvolt = <3100000>; 167*4882a593Smuzhiyun regulator-suspend-min-microvolt = <3100000>; 168*4882a593Smuzhiyun }; 169*4882a593Smuzhiyun }; 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun dcdc3_reg: DCDC3 { 172*4882a593Smuzhiyun regulator-name = "DCDC3"; 173*4882a593Smuzhiyun regulator-min-microvolt = <300000>; 174*4882a593Smuzhiyun regulator-max-microvolt = <1875000>; 175*4882a593Smuzhiyun regulator-always-on; 176*4882a593Smuzhiyun regulator-boot-on; 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun regulator-state-mem { 179*4882a593Smuzhiyun regulator-on-in-suspend; 180*4882a593Smuzhiyun regulator-suspend-max-microvolt = <1140000>; 181*4882a593Smuzhiyun regulator-suspend-min-microvolt = <1140000>; 182*4882a593Smuzhiyun }; 183*4882a593Smuzhiyun }; 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun /* Core4_1V2 */ 186*4882a593Smuzhiyun dcdc4_reg: DCDC4 { 187*4882a593Smuzhiyun regulator-name = "DCDC4"; 188*4882a593Smuzhiyun regulator-min-microvolt = <1200000>; 189*4882a593Smuzhiyun regulator-max-microvolt = <1200000>; 190*4882a593Smuzhiyun regulator-always-on; 191*4882a593Smuzhiyun regulator-boot-on; 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun regulator-state-mem { 194*4882a593Smuzhiyun regulator-on-in-suspend; 195*4882a593Smuzhiyun regulator-suspend-max-microvolt = <1140000>; 196*4882a593Smuzhiyun regulator-suspend-min-microvolt = <1140000>; 197*4882a593Smuzhiyun }; 198*4882a593Smuzhiyun }; 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun /* Core4_1V8 */ 201*4882a593Smuzhiyun dcdc5_reg: DCDC5 { 202*4882a593Smuzhiyun regulator-name = "DCDC5"; 203*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 204*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 205*4882a593Smuzhiyun regulator-always-on; 206*4882a593Smuzhiyun regulator-boot-on; 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun regulator-state-mem { 209*4882a593Smuzhiyun regulator-on-in-suspend; 210*4882a593Smuzhiyun regulator-suspend-max-microvolt = <1700000>; 211*4882a593Smuzhiyun regulator-suspend-min-microvolt = <1700000>; 212*4882a593Smuzhiyun }; 213*4882a593Smuzhiyun }; 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun /* IR_3V3 */ 216*4882a593Smuzhiyun ldo1_reg: LDO1 { 217*4882a593Smuzhiyun regulator-name = "LDO1"; 218*4882a593Smuzhiyun regulator-boot-on; 219*4882a593Smuzhiyun }; 220*4882a593Smuzhiyun 221*4882a593Smuzhiyun /* Core1_3V3 */ 222*4882a593Smuzhiyun ldo2_reg: LDO2 { 223*4882a593Smuzhiyun regulator-name = "LDO2"; 224*4882a593Smuzhiyun regulator-always-on; 225*4882a593Smuzhiyun regulator-boot-on; 226*4882a593Smuzhiyun 227*4882a593Smuzhiyun regulator-state-mem { 228*4882a593Smuzhiyun regulator-on-in-suspend; 229*4882a593Smuzhiyun regulator-suspend-max-microvolt = <3000000>; 230*4882a593Smuzhiyun regulator-suspend-min-microvolt = <3000000>; 231*4882a593Smuzhiyun }; 232*4882a593Smuzhiyun }; 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun /* Core5_1V2 */ 235*4882a593Smuzhiyun ldo3_reg: LDO3 { 236*4882a593Smuzhiyun regulator-name = "LDO3"; 237*4882a593Smuzhiyun regulator-always-on; 238*4882a593Smuzhiyun regulator-boot-on; 239*4882a593Smuzhiyun }; 240*4882a593Smuzhiyun 241*4882a593Smuzhiyun ldo4_reg: LDO4 { 242*4882a593Smuzhiyun regulator-name = "LDO4"; 243*4882a593Smuzhiyun regulator-boot-on; 244*4882a593Smuzhiyun }; 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun /* SPD_3V3 */ 247*4882a593Smuzhiyun ldo5_reg: LDO5 { 248*4882a593Smuzhiyun regulator-name = "LDO5"; 249*4882a593Smuzhiyun regulator-always-on; 250*4882a593Smuzhiyun regulator-boot-on; 251*4882a593Smuzhiyun }; 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun /* DDR_0V6 */ 254*4882a593Smuzhiyun ldo6_reg: LDO6 { 255*4882a593Smuzhiyun regulator-name = "LDO6"; 256*4882a593Smuzhiyun regulator-always-on; 257*4882a593Smuzhiyun regulator-boot-on; 258*4882a593Smuzhiyun }; 259*4882a593Smuzhiyun 260*4882a593Smuzhiyun /* VDD_PWM */ 261*4882a593Smuzhiyun ldo7_reg: LDO7 { 262*4882a593Smuzhiyun regulator-name = "LDO7"; 263*4882a593Smuzhiyun regulator-always-on; 264*4882a593Smuzhiyun regulator-boot-on; 265*4882a593Smuzhiyun }; 266*4882a593Smuzhiyun 267*4882a593Smuzhiyun /* ldo_1v8 */ 268*4882a593Smuzhiyun ldo8_reg: LDO8 { 269*4882a593Smuzhiyun regulator-name = "LDO8"; 270*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 271*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 272*4882a593Smuzhiyun regulator-always-on; 273*4882a593Smuzhiyun regulator-boot-on; 274*4882a593Smuzhiyun }; 275*4882a593Smuzhiyun 276*4882a593Smuzhiyun ldo9_reg: LDO9 { 277*4882a593Smuzhiyun regulator-name = "LDO9"; 278*4882a593Smuzhiyun regulator-boot-on; 279*4882a593Smuzhiyun }; 280*4882a593Smuzhiyun 281*4882a593Smuzhiyun ldo10_reg: LDO10 { 282*4882a593Smuzhiyun regulator-name = "LDO10"; 283*4882a593Smuzhiyun regulator-boot-on; 284*4882a593Smuzhiyun }; 285*4882a593Smuzhiyun 286*4882a593Smuzhiyun ldortc1_reg: LDORTC1 { 287*4882a593Smuzhiyun regulator-name = "LDORTC1"; 288*4882a593Smuzhiyun regulator-always-on; 289*4882a593Smuzhiyun regulator-boot-on; 290*4882a593Smuzhiyun }; 291*4882a593Smuzhiyun }; 292*4882a593Smuzhiyun }; 293*4882a593Smuzhiyun}; 294*4882a593Smuzhiyun 295*4882a593Smuzhiyun&iomuxc { 296*4882a593Smuzhiyun pinctrl-names = "default"; 297*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_hog>; 298*4882a593Smuzhiyun 299*4882a593Smuzhiyun pinctrl_gpio_keys: gpio-keysgrp { 300*4882a593Smuzhiyun fsl,pins = < 301*4882a593Smuzhiyun MX6SL_PAD_SD1_DAT1__GPIO5_IO08 0x17059 302*4882a593Smuzhiyun MX6SL_PAD_SD1_DAT4__GPIO5_IO12 0x17059 303*4882a593Smuzhiyun MX6SL_PAD_KEY_COL1__GPIO3_IO26 0x17059 304*4882a593Smuzhiyun MX6SL_PAD_KEY_ROW0__GPIO3_IO25 0x17059 305*4882a593Smuzhiyun >; 306*4882a593Smuzhiyun }; 307*4882a593Smuzhiyun 308*4882a593Smuzhiyun pinctrl_hog: hoggrp { 309*4882a593Smuzhiyun fsl,pins = < 310*4882a593Smuzhiyun MX6SL_PAD_LCD_DAT0__GPIO2_IO20 0x79 311*4882a593Smuzhiyun MX6SL_PAD_LCD_DAT1__GPIO2_IO21 0x79 312*4882a593Smuzhiyun MX6SL_PAD_LCD_DAT2__GPIO2_IO22 0x79 313*4882a593Smuzhiyun MX6SL_PAD_LCD_DAT3__GPIO2_IO23 0x79 314*4882a593Smuzhiyun MX6SL_PAD_LCD_DAT4__GPIO2_IO24 0x79 315*4882a593Smuzhiyun MX6SL_PAD_LCD_DAT5__GPIO2_IO25 0x79 316*4882a593Smuzhiyun MX6SL_PAD_LCD_DAT6__GPIO2_IO26 0x79 317*4882a593Smuzhiyun MX6SL_PAD_LCD_DAT7__GPIO2_IO27 0x79 318*4882a593Smuzhiyun MX6SL_PAD_LCD_DAT8__GPIO2_IO28 0x79 319*4882a593Smuzhiyun MX6SL_PAD_LCD_DAT9__GPIO2_IO29 0x79 320*4882a593Smuzhiyun MX6SL_PAD_LCD_DAT10__GPIO2_IO30 0x79 321*4882a593Smuzhiyun MX6SL_PAD_LCD_DAT11__GPIO2_IO31 0x79 322*4882a593Smuzhiyun MX6SL_PAD_LCD_DAT12__GPIO3_IO00 0x79 323*4882a593Smuzhiyun MX6SL_PAD_LCD_DAT13__GPIO3_IO01 0x79 324*4882a593Smuzhiyun MX6SL_PAD_LCD_DAT14__GPIO3_IO02 0x79 325*4882a593Smuzhiyun MX6SL_PAD_LCD_DAT15__GPIO3_IO03 0x79 326*4882a593Smuzhiyun MX6SL_PAD_LCD_DAT16__GPIO3_IO04 0x79 327*4882a593Smuzhiyun MX6SL_PAD_LCD_DAT17__GPIO3_IO05 0x79 328*4882a593Smuzhiyun MX6SL_PAD_LCD_DAT18__GPIO3_IO06 0x79 329*4882a593Smuzhiyun MX6SL_PAD_LCD_DAT19__GPIO3_IO07 0x79 330*4882a593Smuzhiyun MX6SL_PAD_LCD_DAT20__GPIO3_IO08 0x79 331*4882a593Smuzhiyun MX6SL_PAD_LCD_DAT21__GPIO3_IO09 0x79 332*4882a593Smuzhiyun MX6SL_PAD_LCD_DAT22__GPIO3_IO10 0x79 333*4882a593Smuzhiyun MX6SL_PAD_LCD_DAT23__GPIO3_IO11 0x79 334*4882a593Smuzhiyun MX6SL_PAD_LCD_CLK__GPIO2_IO15 0x79 335*4882a593Smuzhiyun MX6SL_PAD_LCD_ENABLE__GPIO2_IO16 0x79 336*4882a593Smuzhiyun MX6SL_PAD_LCD_HSYNC__GPIO2_IO17 0x79 337*4882a593Smuzhiyun MX6SL_PAD_LCD_VSYNC__GPIO2_IO18 0x79 338*4882a593Smuzhiyun MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x79 339*4882a593Smuzhiyun MX6SL_PAD_KEY_COL3__GPIO3_IO30 0x79 340*4882a593Smuzhiyun MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x79 341*4882a593Smuzhiyun MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x79 342*4882a593Smuzhiyun MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x79 343*4882a593Smuzhiyun MX6SL_PAD_KEY_ROW6__GPIO4_IO05 0x79 344*4882a593Smuzhiyun >; 345*4882a593Smuzhiyun }; 346*4882a593Smuzhiyun 347*4882a593Smuzhiyun pinctrl_i2c1: i2c1grp { 348*4882a593Smuzhiyun fsl,pins = < 349*4882a593Smuzhiyun MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001f8b1 350*4882a593Smuzhiyun MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001f8b1 351*4882a593Smuzhiyun >; 352*4882a593Smuzhiyun }; 353*4882a593Smuzhiyun 354*4882a593Smuzhiyun pinctrl_i2c1_sleep: i2c1grp-sleep { 355*4882a593Smuzhiyun fsl,pins = < 356*4882a593Smuzhiyun MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1 357*4882a593Smuzhiyun MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1 358*4882a593Smuzhiyun >; 359*4882a593Smuzhiyun }; 360*4882a593Smuzhiyun 361*4882a593Smuzhiyun pinctrl_i2c2: i2c2grp { 362*4882a593Smuzhiyun fsl,pins = < 363*4882a593Smuzhiyun MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001f8b1 364*4882a593Smuzhiyun MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001f8b1 365*4882a593Smuzhiyun >; 366*4882a593Smuzhiyun }; 367*4882a593Smuzhiyun 368*4882a593Smuzhiyun pinctrl_i2c2_sleep: i2c2grp-sleep { 369*4882a593Smuzhiyun fsl,pins = < 370*4882a593Smuzhiyun MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1 371*4882a593Smuzhiyun MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1 372*4882a593Smuzhiyun >; 373*4882a593Smuzhiyun }; 374*4882a593Smuzhiyun 375*4882a593Smuzhiyun pinctrl_i2c3: i2c3grp { 376*4882a593Smuzhiyun fsl,pins = < 377*4882a593Smuzhiyun MX6SL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1 378*4882a593Smuzhiyun MX6SL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1 379*4882a593Smuzhiyun >; 380*4882a593Smuzhiyun }; 381*4882a593Smuzhiyun 382*4882a593Smuzhiyun pinctrl_led: ledgrp { 383*4882a593Smuzhiyun fsl,pins = < 384*4882a593Smuzhiyun MX6SL_PAD_SD1_DAT2__GPIO5_IO13 0x17059 385*4882a593Smuzhiyun >; 386*4882a593Smuzhiyun }; 387*4882a593Smuzhiyun 388*4882a593Smuzhiyun pinctrl_ricoh_gpio: ricoh_gpiogrp { 389*4882a593Smuzhiyun fsl,pins = < 390*4882a593Smuzhiyun MX6SL_PAD_SD1_CLK__GPIO5_IO15 0x1b8b1 /* ricoh619 chg */ 391*4882a593Smuzhiyun MX6SL_PAD_SD1_DAT0__GPIO5_IO11 0x1b8b1 /* ricoh619 irq */ 392*4882a593Smuzhiyun MX6SL_PAD_KEY_COL2__GPIO3_IO28 0x1b8b1 /* ricoh619 bat_low_int */ 393*4882a593Smuzhiyun >; 394*4882a593Smuzhiyun }; 395*4882a593Smuzhiyun 396*4882a593Smuzhiyun pinctrl_uart1: uart1grp { 397*4882a593Smuzhiyun fsl,pins = < 398*4882a593Smuzhiyun MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1 399*4882a593Smuzhiyun MX6SL_PAD_UART1_RXD__UART1_TX_DATA 0x1b0b1 400*4882a593Smuzhiyun >; 401*4882a593Smuzhiyun }; 402*4882a593Smuzhiyun 403*4882a593Smuzhiyun pinctrl_usbotg1: usbotg1grp { 404*4882a593Smuzhiyun fsl,pins = < 405*4882a593Smuzhiyun MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059 406*4882a593Smuzhiyun >; 407*4882a593Smuzhiyun }; 408*4882a593Smuzhiyun 409*4882a593Smuzhiyun pinctrl_usdhc2: usdhc2grp { 410*4882a593Smuzhiyun fsl,pins = < 411*4882a593Smuzhiyun MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059 412*4882a593Smuzhiyun MX6SL_PAD_SD2_CLK__SD2_CLK 0x13059 413*4882a593Smuzhiyun MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059 414*4882a593Smuzhiyun MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059 415*4882a593Smuzhiyun MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059 416*4882a593Smuzhiyun MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059 417*4882a593Smuzhiyun >; 418*4882a593Smuzhiyun }; 419*4882a593Smuzhiyun 420*4882a593Smuzhiyun pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { 421*4882a593Smuzhiyun fsl,pins = < 422*4882a593Smuzhiyun MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9 423*4882a593Smuzhiyun MX6SL_PAD_SD2_CLK__SD2_CLK 0x130b9 424*4882a593Smuzhiyun MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 425*4882a593Smuzhiyun MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 426*4882a593Smuzhiyun MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 427*4882a593Smuzhiyun MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 428*4882a593Smuzhiyun >; 429*4882a593Smuzhiyun }; 430*4882a593Smuzhiyun 431*4882a593Smuzhiyun pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { 432*4882a593Smuzhiyun fsl,pins = < 433*4882a593Smuzhiyun MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9 434*4882a593Smuzhiyun MX6SL_PAD_SD2_CLK__SD2_CLK 0x130f9 435*4882a593Smuzhiyun MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 436*4882a593Smuzhiyun MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 437*4882a593Smuzhiyun MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 438*4882a593Smuzhiyun MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 439*4882a593Smuzhiyun >; 440*4882a593Smuzhiyun }; 441*4882a593Smuzhiyun 442*4882a593Smuzhiyun pinctrl_usdhc2_sleep: usdhc2grp-sleep { 443*4882a593Smuzhiyun fsl,pins = < 444*4882a593Smuzhiyun MX6SL_PAD_SD2_CMD__GPIO5_IO04 0x100f9 445*4882a593Smuzhiyun MX6SL_PAD_SD2_CLK__GPIO5_IO05 0x100f9 446*4882a593Smuzhiyun MX6SL_PAD_SD2_DAT0__GPIO5_IO01 0x100f9 447*4882a593Smuzhiyun MX6SL_PAD_SD2_DAT1__GPIO4_IO30 0x100f9 448*4882a593Smuzhiyun MX6SL_PAD_SD2_DAT2__GPIO5_IO03 0x100f9 449*4882a593Smuzhiyun MX6SL_PAD_SD2_DAT3__GPIO4_IO28 0x100f9 450*4882a593Smuzhiyun >; 451*4882a593Smuzhiyun }; 452*4882a593Smuzhiyun 453*4882a593Smuzhiyun pinctrl_usdhc3: usdhc3grp { 454*4882a593Smuzhiyun fsl,pins = < 455*4882a593Smuzhiyun MX6SL_PAD_SD3_CMD__SD3_CMD 0x11059 456*4882a593Smuzhiyun MX6SL_PAD_SD3_CLK__SD3_CLK 0x11059 457*4882a593Smuzhiyun MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x11059 458*4882a593Smuzhiyun MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x11059 459*4882a593Smuzhiyun MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x11059 460*4882a593Smuzhiyun MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x11059 461*4882a593Smuzhiyun >; 462*4882a593Smuzhiyun }; 463*4882a593Smuzhiyun 464*4882a593Smuzhiyun pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { 465*4882a593Smuzhiyun fsl,pins = < 466*4882a593Smuzhiyun MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9 467*4882a593Smuzhiyun MX6SL_PAD_SD3_CLK__SD3_CLK 0x170b9 468*4882a593Smuzhiyun MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 469*4882a593Smuzhiyun MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 470*4882a593Smuzhiyun MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 471*4882a593Smuzhiyun MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 472*4882a593Smuzhiyun >; 473*4882a593Smuzhiyun }; 474*4882a593Smuzhiyun 475*4882a593Smuzhiyun pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { 476*4882a593Smuzhiyun fsl,pins = < 477*4882a593Smuzhiyun MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9 478*4882a593Smuzhiyun MX6SL_PAD_SD3_CLK__SD3_CLK 0x170f9 479*4882a593Smuzhiyun MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 480*4882a593Smuzhiyun MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 481*4882a593Smuzhiyun MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 482*4882a593Smuzhiyun MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 483*4882a593Smuzhiyun >; 484*4882a593Smuzhiyun }; 485*4882a593Smuzhiyun 486*4882a593Smuzhiyun pinctrl_usdhc3_sleep: usdhc3grp-sleep { 487*4882a593Smuzhiyun fsl,pins = < 488*4882a593Smuzhiyun MX6SL_PAD_SD3_CMD__GPIO5_IO21 0x100c1 489*4882a593Smuzhiyun MX6SL_PAD_SD3_CLK__GPIO5_IO18 0x100c1 490*4882a593Smuzhiyun MX6SL_PAD_SD3_DAT0__GPIO5_IO19 0x100c1 491*4882a593Smuzhiyun MX6SL_PAD_SD3_DAT1__GPIO5_IO20 0x100c1 492*4882a593Smuzhiyun MX6SL_PAD_SD3_DAT2__GPIO5_IO16 0x100c1 493*4882a593Smuzhiyun MX6SL_PAD_SD3_DAT3__GPIO5_IO17 0x100c1 494*4882a593Smuzhiyun >; 495*4882a593Smuzhiyun }; 496*4882a593Smuzhiyun 497*4882a593Smuzhiyun pinctrl_wifi_power: wifi-powergrp { 498*4882a593Smuzhiyun fsl,pins = < 499*4882a593Smuzhiyun MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x10059 /* WIFI_3V3_ON */ 500*4882a593Smuzhiyun >; 501*4882a593Smuzhiyun }; 502*4882a593Smuzhiyun 503*4882a593Smuzhiyun pinctrl_wifi_reset: wifi-resetgrp { 504*4882a593Smuzhiyun fsl,pins = < 505*4882a593Smuzhiyun MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x10059 /* WIFI_RST */ 506*4882a593Smuzhiyun >; 507*4882a593Smuzhiyun }; 508*4882a593Smuzhiyun 509*4882a593Smuzhiyun pinctrl_zforce: zforcegrp { 510*4882a593Smuzhiyun fsl,pins = < 511*4882a593Smuzhiyun MX6SL_PAD_SD1_DAT3__GPIO5_IO06 0x17059 /* TP_INT */ 512*4882a593Smuzhiyun MX6SL_PAD_SD1_DAT5__GPIO5_IO09 0x10059 /* TP_RST */ 513*4882a593Smuzhiyun >; 514*4882a593Smuzhiyun }; 515*4882a593Smuzhiyun}; 516*4882a593Smuzhiyun 517*4882a593Smuzhiyun®_vdd1p1 { 518*4882a593Smuzhiyun vin-supply = <&dcdc2_reg>; 519*4882a593Smuzhiyun}; 520*4882a593Smuzhiyun 521*4882a593Smuzhiyun®_vdd2p5 { 522*4882a593Smuzhiyun vin-supply = <&dcdc2_reg>; 523*4882a593Smuzhiyun}; 524*4882a593Smuzhiyun 525*4882a593Smuzhiyun®_arm { 526*4882a593Smuzhiyun vin-supply = <&dcdc3_reg>; 527*4882a593Smuzhiyun}; 528*4882a593Smuzhiyun 529*4882a593Smuzhiyun®_soc { 530*4882a593Smuzhiyun vin-supply = <&dcdc1_reg>; 531*4882a593Smuzhiyun}; 532*4882a593Smuzhiyun 533*4882a593Smuzhiyun®_pu { 534*4882a593Smuzhiyun vin-supply = <&dcdc1_reg>; 535*4882a593Smuzhiyun}; 536*4882a593Smuzhiyun 537*4882a593Smuzhiyun&snvs_rtc { 538*4882a593Smuzhiyun /* 539*4882a593Smuzhiyun * We are using the RTC in the PMIC, but this one is not disabled 540*4882a593Smuzhiyun * in imx6sl.dtsi. 541*4882a593Smuzhiyun */ 542*4882a593Smuzhiyun status = "disabled"; 543*4882a593Smuzhiyun}; 544*4882a593Smuzhiyun 545*4882a593Smuzhiyun&uart1 { 546*4882a593Smuzhiyun pinctrl-names = "default"; 547*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart1>; 548*4882a593Smuzhiyun status = "okay"; 549*4882a593Smuzhiyun}; 550*4882a593Smuzhiyun 551*4882a593Smuzhiyun&usdhc2 { 552*4882a593Smuzhiyun pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 553*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc2>; 554*4882a593Smuzhiyun pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 555*4882a593Smuzhiyun pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 556*4882a593Smuzhiyun pinctrl-3 = <&pinctrl_usdhc2_sleep>; 557*4882a593Smuzhiyun non-removable; 558*4882a593Smuzhiyun status = "okay"; 559*4882a593Smuzhiyun 560*4882a593Smuzhiyun /* internal uSD card */ 561*4882a593Smuzhiyun}; 562*4882a593Smuzhiyun 563*4882a593Smuzhiyun&usdhc3 { 564*4882a593Smuzhiyun pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 565*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc3>; 566*4882a593Smuzhiyun pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 567*4882a593Smuzhiyun pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 568*4882a593Smuzhiyun pinctrl-3 = <&pinctrl_usdhc3_sleep>; 569*4882a593Smuzhiyun vmmc-supply = <®_wifi>; 570*4882a593Smuzhiyun mmc-pwrseq = <&wifi_pwrseq>; 571*4882a593Smuzhiyun cap-power-off-card; 572*4882a593Smuzhiyun non-removable; 573*4882a593Smuzhiyun status = "okay"; 574*4882a593Smuzhiyun 575*4882a593Smuzhiyun /* 576*4882a593Smuzhiyun * 37NB-E60QF0+4A2: CyberTan WC121 (BCM43362) SDIO WiFi 577*4882a593Smuzhiyun * 37NB-E60QF0+4A3: RTL8189F SDIO WiFi 578*4882a593Smuzhiyun */ 579*4882a593Smuzhiyun}; 580*4882a593Smuzhiyun 581*4882a593Smuzhiyun&usbotg1 { 582*4882a593Smuzhiyun pinctrl-names = "default"; 583*4882a593Smuzhiyun disable-over-current; 584*4882a593Smuzhiyun srp-disable; 585*4882a593Smuzhiyun hnp-disable; 586*4882a593Smuzhiyun adp-disable; 587*4882a593Smuzhiyun status = "okay"; 588*4882a593Smuzhiyun}; 589