xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/imx6sl-evk.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun//
3*4882a593Smuzhiyun//Copyright (C) 2013 Freescale Semiconductor, Inc.
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun/dts-v1/;
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
8*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
9*4882a593Smuzhiyun#include "imx6sl.dtsi"
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun/ {
12*4882a593Smuzhiyun	model = "Freescale i.MX6 SoloLite EVK Board";
13*4882a593Smuzhiyun	compatible = "fsl,imx6sl-evk", "fsl,imx6sl";
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun	chosen {
16*4882a593Smuzhiyun		stdout-path = &uart1;
17*4882a593Smuzhiyun	};
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun	memory@80000000 {
20*4882a593Smuzhiyun		device_type = "memory";
21*4882a593Smuzhiyun		reg = <0x80000000 0x40000000>;
22*4882a593Smuzhiyun	};
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun	backlight_display: backlight_display {
25*4882a593Smuzhiyun		compatible = "pwm-backlight";
26*4882a593Smuzhiyun		pwms = <&pwm1 0 5000000>;
27*4882a593Smuzhiyun		brightness-levels = <0 4 8 16 32 64 128 255>;
28*4882a593Smuzhiyun		default-brightness-level = <6>;
29*4882a593Smuzhiyun	};
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun	leds {
32*4882a593Smuzhiyun		compatible = "gpio-leds";
33*4882a593Smuzhiyun		pinctrl-names = "default";
34*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_led>;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun		user {
37*4882a593Smuzhiyun			label = "debug";
38*4882a593Smuzhiyun			gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
39*4882a593Smuzhiyun			linux,default-trigger = "heartbeat";
40*4882a593Smuzhiyun		};
41*4882a593Smuzhiyun	};
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun	reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
44*4882a593Smuzhiyun		compatible = "regulator-fixed";
45*4882a593Smuzhiyun		regulator-name = "usb_otg1_vbus";
46*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
47*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
48*4882a593Smuzhiyun		gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>;
49*4882a593Smuzhiyun		enable-active-high;
50*4882a593Smuzhiyun		vin-supply = <&swbst_reg>;
51*4882a593Smuzhiyun	};
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun	reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
54*4882a593Smuzhiyun		compatible = "regulator-fixed";
55*4882a593Smuzhiyun		regulator-name = "usb_otg2_vbus";
56*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
57*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
58*4882a593Smuzhiyun		gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>;
59*4882a593Smuzhiyun		enable-active-high;
60*4882a593Smuzhiyun		vin-supply = <&swbst_reg>;
61*4882a593Smuzhiyun	};
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun	reg_aud3v: regulator-aud3v {
64*4882a593Smuzhiyun		compatible = "regulator-fixed";
65*4882a593Smuzhiyun		regulator-name = "wm8962-supply-3v15";
66*4882a593Smuzhiyun		regulator-min-microvolt = <3150000>;
67*4882a593Smuzhiyun		regulator-max-microvolt = <3150000>;
68*4882a593Smuzhiyun		regulator-boot-on;
69*4882a593Smuzhiyun	};
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun	reg_aud4v: regulator-aud4v {
72*4882a593Smuzhiyun		compatible = "regulator-fixed";
73*4882a593Smuzhiyun		regulator-name = "wm8962-supply-4v2";
74*4882a593Smuzhiyun		regulator-min-microvolt = <4325000>;
75*4882a593Smuzhiyun		regulator-max-microvolt = <4325000>;
76*4882a593Smuzhiyun		regulator-boot-on;
77*4882a593Smuzhiyun	};
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun	reg_lcd_3v3: regulator-lcd-3v3 {
80*4882a593Smuzhiyun		compatible = "regulator-fixed";
81*4882a593Smuzhiyun		pinctrl-names = "default";
82*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_reg_lcd_3v3>;
83*4882a593Smuzhiyun		regulator-name = "lcd-3v3";
84*4882a593Smuzhiyun		gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
85*4882a593Smuzhiyun		enable-active-high;
86*4882a593Smuzhiyun	};
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun	reg_lcd_5v: regulator-lcd-5v {
89*4882a593Smuzhiyun		compatible = "regulator-fixed";
90*4882a593Smuzhiyun		regulator-name = "lcd-5v0";
91*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
92*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
93*4882a593Smuzhiyun	};
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun	sound {
96*4882a593Smuzhiyun		compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962";
97*4882a593Smuzhiyun		pinctrl-names = "default";
98*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_hp>;
99*4882a593Smuzhiyun		model = "wm8962-audio";
100*4882a593Smuzhiyun		ssi-controller = <&ssi2>;
101*4882a593Smuzhiyun		audio-codec = <&codec>;
102*4882a593Smuzhiyun		audio-routing =
103*4882a593Smuzhiyun			"Headphone Jack", "HPOUTL",
104*4882a593Smuzhiyun			"Headphone Jack", "HPOUTR",
105*4882a593Smuzhiyun			"Ext Spk", "SPKOUTL",
106*4882a593Smuzhiyun			"Ext Spk", "SPKOUTR",
107*4882a593Smuzhiyun			"AMIC", "MICBIAS",
108*4882a593Smuzhiyun			"IN3R", "AMIC";
109*4882a593Smuzhiyun		mux-int-port = <2>;
110*4882a593Smuzhiyun		mux-ext-port = <3>;
111*4882a593Smuzhiyun		hp-det-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>;
112*4882a593Smuzhiyun	};
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun	panel {
115*4882a593Smuzhiyun		compatible = "sii,43wvf1g";
116*4882a593Smuzhiyun		backlight = <&backlight_display>;
117*4882a593Smuzhiyun		dvdd-supply = <&reg_lcd_3v3>;
118*4882a593Smuzhiyun		avdd-supply = <&reg_lcd_5v>;
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun		port {
121*4882a593Smuzhiyun			panel_in: endpoint {
122*4882a593Smuzhiyun				remote-endpoint = <&display_out>;
123*4882a593Smuzhiyun			};
124*4882a593Smuzhiyun		};
125*4882a593Smuzhiyun	};
126*4882a593Smuzhiyun};
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun&audmux {
129*4882a593Smuzhiyun	pinctrl-names = "default";
130*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_audmux3>;
131*4882a593Smuzhiyun	status = "okay";
132*4882a593Smuzhiyun};
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun&ecspi1 {
135*4882a593Smuzhiyun	cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
136*4882a593Smuzhiyun	pinctrl-names = "default";
137*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_ecspi1>;
138*4882a593Smuzhiyun	status = "okay";
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun	flash: flash@0 {
141*4882a593Smuzhiyun		#address-cells = <1>;
142*4882a593Smuzhiyun		#size-cells = <1>;
143*4882a593Smuzhiyun		compatible = "st,m25p32", "jedec,spi-nor";
144*4882a593Smuzhiyun		spi-max-frequency = <20000000>;
145*4882a593Smuzhiyun		reg = <0>;
146*4882a593Smuzhiyun	};
147*4882a593Smuzhiyun};
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun&fec {
150*4882a593Smuzhiyun	pinctrl-names = "default", "sleep";
151*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_fec>;
152*4882a593Smuzhiyun	pinctrl-1 = <&pinctrl_fec_sleep>;
153*4882a593Smuzhiyun	phy-mode = "rmii";
154*4882a593Smuzhiyun	status = "okay";
155*4882a593Smuzhiyun};
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun&i2c1 {
158*4882a593Smuzhiyun	clock-frequency = <100000>;
159*4882a593Smuzhiyun	pinctrl-names = "default";
160*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c1>;
161*4882a593Smuzhiyun	status = "okay";
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun	pmic: pfuze100@8 {
164*4882a593Smuzhiyun		compatible = "fsl,pfuze100";
165*4882a593Smuzhiyun		reg = <0x08>;
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun		regulators {
168*4882a593Smuzhiyun			sw1a_reg: sw1ab {
169*4882a593Smuzhiyun				regulator-min-microvolt = <300000>;
170*4882a593Smuzhiyun				regulator-max-microvolt = <1875000>;
171*4882a593Smuzhiyun				regulator-boot-on;
172*4882a593Smuzhiyun				regulator-always-on;
173*4882a593Smuzhiyun				regulator-ramp-delay = <6250>;
174*4882a593Smuzhiyun			};
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun			sw1c_reg: sw1c {
177*4882a593Smuzhiyun				regulator-min-microvolt = <300000>;
178*4882a593Smuzhiyun				regulator-max-microvolt = <1875000>;
179*4882a593Smuzhiyun				regulator-boot-on;
180*4882a593Smuzhiyun				regulator-always-on;
181*4882a593Smuzhiyun				regulator-ramp-delay = <6250>;
182*4882a593Smuzhiyun			};
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun			sw2_reg: sw2 {
185*4882a593Smuzhiyun				regulator-min-microvolt = <800000>;
186*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
187*4882a593Smuzhiyun				regulator-boot-on;
188*4882a593Smuzhiyun				regulator-always-on;
189*4882a593Smuzhiyun			};
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun			sw3a_reg: sw3a {
192*4882a593Smuzhiyun				regulator-min-microvolt = <400000>;
193*4882a593Smuzhiyun				regulator-max-microvolt = <1975000>;
194*4882a593Smuzhiyun				regulator-boot-on;
195*4882a593Smuzhiyun				regulator-always-on;
196*4882a593Smuzhiyun			};
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun			sw3b_reg: sw3b {
199*4882a593Smuzhiyun				regulator-min-microvolt = <400000>;
200*4882a593Smuzhiyun				regulator-max-microvolt = <1975000>;
201*4882a593Smuzhiyun				regulator-boot-on;
202*4882a593Smuzhiyun				regulator-always-on;
203*4882a593Smuzhiyun			};
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun			sw4_reg: sw4 {
206*4882a593Smuzhiyun				regulator-min-microvolt = <800000>;
207*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
208*4882a593Smuzhiyun				regulator-always-on;
209*4882a593Smuzhiyun			};
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun			swbst_reg: swbst {
212*4882a593Smuzhiyun				regulator-min-microvolt = <5000000>;
213*4882a593Smuzhiyun				regulator-max-microvolt = <5150000>;
214*4882a593Smuzhiyun			};
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun			snvs_reg: vsnvs {
217*4882a593Smuzhiyun				regulator-min-microvolt = <1000000>;
218*4882a593Smuzhiyun				regulator-max-microvolt = <3000000>;
219*4882a593Smuzhiyun				regulator-boot-on;
220*4882a593Smuzhiyun				regulator-always-on;
221*4882a593Smuzhiyun			};
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun			vref_reg: vrefddr {
224*4882a593Smuzhiyun				regulator-boot-on;
225*4882a593Smuzhiyun				regulator-always-on;
226*4882a593Smuzhiyun			};
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun			vgen1_reg: vgen1 {
229*4882a593Smuzhiyun				regulator-min-microvolt = <800000>;
230*4882a593Smuzhiyun				regulator-max-microvolt = <1550000>;
231*4882a593Smuzhiyun				regulator-always-on;
232*4882a593Smuzhiyun			};
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun			vgen2_reg: vgen2 {
235*4882a593Smuzhiyun				regulator-min-microvolt = <800000>;
236*4882a593Smuzhiyun				regulator-max-microvolt = <1550000>;
237*4882a593Smuzhiyun			};
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun			vgen3_reg: vgen3 {
240*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
241*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
242*4882a593Smuzhiyun			};
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun			vgen4_reg: vgen4 {
245*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
246*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
247*4882a593Smuzhiyun				regulator-always-on;
248*4882a593Smuzhiyun			};
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun			vgen5_reg: vgen5 {
251*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
252*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
253*4882a593Smuzhiyun				regulator-always-on;
254*4882a593Smuzhiyun			};
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun			vgen6_reg: vgen6 {
257*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
258*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
259*4882a593Smuzhiyun				regulator-always-on;
260*4882a593Smuzhiyun			};
261*4882a593Smuzhiyun		};
262*4882a593Smuzhiyun	};
263*4882a593Smuzhiyun};
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun&i2c2 {
266*4882a593Smuzhiyun	clock-frequency = <100000>;
267*4882a593Smuzhiyun	pinctrl-names = "default";
268*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c2>;
269*4882a593Smuzhiyun	status = "okay";
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun	codec: wm8962@1a {
272*4882a593Smuzhiyun		compatible = "wlf,wm8962";
273*4882a593Smuzhiyun		reg = <0x1a>;
274*4882a593Smuzhiyun		clocks = <&clks IMX6SL_CLK_EXTERN_AUDIO>;
275*4882a593Smuzhiyun		DCVDD-supply = <&vgen3_reg>;
276*4882a593Smuzhiyun		DBVDD-supply = <&reg_aud3v>;
277*4882a593Smuzhiyun		AVDD-supply = <&vgen3_reg>;
278*4882a593Smuzhiyun		CPVDD-supply = <&vgen3_reg>;
279*4882a593Smuzhiyun		MICVDD-supply = <&reg_aud3v>;
280*4882a593Smuzhiyun		PLLVDD-supply = <&vgen3_reg>;
281*4882a593Smuzhiyun		SPKVDD1-supply = <&reg_aud4v>;
282*4882a593Smuzhiyun		SPKVDD2-supply = <&reg_aud4v>;
283*4882a593Smuzhiyun	};
284*4882a593Smuzhiyun};
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun&iomuxc {
287*4882a593Smuzhiyun	pinctrl-names = "default";
288*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_hog>;
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun	imx6sl-evk {
291*4882a593Smuzhiyun		pinctrl_hog: hoggrp {
292*4882a593Smuzhiyun			fsl,pins = <
293*4882a593Smuzhiyun				MX6SL_PAD_KEY_ROW7__GPIO4_IO07    0x17059
294*4882a593Smuzhiyun				MX6SL_PAD_KEY_COL7__GPIO4_IO06    0x17059
295*4882a593Smuzhiyun				MX6SL_PAD_SD2_DAT7__GPIO5_IO00    0x17059
296*4882a593Smuzhiyun				MX6SL_PAD_SD2_DAT6__GPIO4_IO29    0x17059
297*4882a593Smuzhiyun				MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059
298*4882a593Smuzhiyun				MX6SL_PAD_KEY_COL4__GPIO4_IO00	0x80000000
299*4882a593Smuzhiyun				MX6SL_PAD_KEY_COL5__GPIO4_IO02	0x80000000
300*4882a593Smuzhiyun				MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0
301*4882a593Smuzhiyun			>;
302*4882a593Smuzhiyun		};
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun		pinctrl_audmux3: audmux3grp {
305*4882a593Smuzhiyun			fsl,pins = <
306*4882a593Smuzhiyun				MX6SL_PAD_AUD_RXD__AUD3_RXD	  0x4130b0
307*4882a593Smuzhiyun				MX6SL_PAD_AUD_TXC__AUD3_TXC	  0x4130b0
308*4882a593Smuzhiyun				MX6SL_PAD_AUD_TXD__AUD3_TXD	  0x4110b0
309*4882a593Smuzhiyun				MX6SL_PAD_AUD_TXFS__AUD3_TXFS	  0x4130b0
310*4882a593Smuzhiyun			>;
311*4882a593Smuzhiyun		};
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun		pinctrl_ecspi1: ecspi1grp {
314*4882a593Smuzhiyun			fsl,pins = <
315*4882a593Smuzhiyun				MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO	0x100b1
316*4882a593Smuzhiyun				MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI	0x100b1
317*4882a593Smuzhiyun				MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK	0x100b1
318*4882a593Smuzhiyun				MX6SL_PAD_ECSPI1_SS0__GPIO4_IO11	0x80000000
319*4882a593Smuzhiyun			>;
320*4882a593Smuzhiyun		};
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun		pinctrl_fec: fecgrp {
323*4882a593Smuzhiyun			fsl,pins = <
324*4882a593Smuzhiyun				MX6SL_PAD_FEC_MDC__FEC_MDC		0x1b0b0
325*4882a593Smuzhiyun				MX6SL_PAD_FEC_MDIO__FEC_MDIO		0x1b0b0
326*4882a593Smuzhiyun				MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV		0x1b0b0
327*4882a593Smuzhiyun				MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0	0x1b0b0
328*4882a593Smuzhiyun				MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1	0x1b0b0
329*4882a593Smuzhiyun				MX6SL_PAD_FEC_TX_EN__FEC_TX_EN		0x1b0b0
330*4882a593Smuzhiyun				MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0	0x1b0b0
331*4882a593Smuzhiyun				MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1	0x1b0b0
332*4882a593Smuzhiyun				MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT	0x4001b0a8
333*4882a593Smuzhiyun			>;
334*4882a593Smuzhiyun		};
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun		pinctrl_fec_sleep: fecgrp-sleep {
337*4882a593Smuzhiyun			fsl,pins = <
338*4882a593Smuzhiyun				MX6SL_PAD_FEC_MDC__GPIO4_IO23      0x3080
339*4882a593Smuzhiyun				MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25   0x3080
340*4882a593Smuzhiyun				MX6SL_PAD_FEC_RXD0__GPIO4_IO17     0x3080
341*4882a593Smuzhiyun				MX6SL_PAD_FEC_RXD1__GPIO4_IO18     0x3080
342*4882a593Smuzhiyun				MX6SL_PAD_FEC_TX_EN__GPIO4_IO22    0x3080
343*4882a593Smuzhiyun				MX6SL_PAD_FEC_TXD0__GPIO4_IO24     0x3080
344*4882a593Smuzhiyun				MX6SL_PAD_FEC_TXD1__GPIO4_IO16     0x3080
345*4882a593Smuzhiyun				MX6SL_PAD_FEC_REF_CLK__GPIO4_IO26  0x3080
346*4882a593Smuzhiyun			>;
347*4882a593Smuzhiyun		};
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun		pinctrl_hp: hpgrp {
350*4882a593Smuzhiyun			fsl,pins = <
351*4882a593Smuzhiyun				MX6SL_PAD_FEC_RX_ER__GPIO4_IO19	  0x1b0b0
352*4882a593Smuzhiyun			>;
353*4882a593Smuzhiyun		};
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun		pinctrl_i2c1: i2c1grp {
356*4882a593Smuzhiyun			fsl,pins = <
357*4882a593Smuzhiyun				MX6SL_PAD_I2C1_SCL__I2C1_SCL	0x4001b8b1
358*4882a593Smuzhiyun				MX6SL_PAD_I2C1_SDA__I2C1_SDA	0x4001b8b1
359*4882a593Smuzhiyun			>;
360*4882a593Smuzhiyun		};
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun		pinctrl_i2c2: i2c2grp {
364*4882a593Smuzhiyun			fsl,pins = <
365*4882a593Smuzhiyun				MX6SL_PAD_I2C2_SCL__I2C2_SCL	0x4001b8b1
366*4882a593Smuzhiyun				MX6SL_PAD_I2C2_SDA__I2C2_SDA	0x4001b8b1
367*4882a593Smuzhiyun			>;
368*4882a593Smuzhiyun		};
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun		pinctrl_kpp: kppgrp {
371*4882a593Smuzhiyun			fsl,pins = <
372*4882a593Smuzhiyun				MX6SL_PAD_KEY_ROW0__KEY_ROW0    0x1b010
373*4882a593Smuzhiyun				MX6SL_PAD_KEY_ROW1__KEY_ROW1    0x1b010
374*4882a593Smuzhiyun				MX6SL_PAD_KEY_ROW2__KEY_ROW2    0x1b0b0
375*4882a593Smuzhiyun				MX6SL_PAD_KEY_COL0__KEY_COL0    0x110b0
376*4882a593Smuzhiyun				MX6SL_PAD_KEY_COL1__KEY_COL1    0x110b0
377*4882a593Smuzhiyun				MX6SL_PAD_KEY_COL2__KEY_COL2    0x110b0
378*4882a593Smuzhiyun			>;
379*4882a593Smuzhiyun		};
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun		pinctrl_lcd: lcdgrp {
382*4882a593Smuzhiyun			fsl,pins = <
383*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT0__LCD_DATA00 0x1b0b0
384*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT1__LCD_DATA01 0x1b0b0
385*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT2__LCD_DATA02 0x1b0b0
386*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT3__LCD_DATA03 0x1b0b0
387*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT4__LCD_DATA04 0x1b0b0
388*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT5__LCD_DATA05 0x1b0b0
389*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT6__LCD_DATA06 0x1b0b0
390*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT7__LCD_DATA07 0x1b0b0
391*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT8__LCD_DATA08 0x1b0b0
392*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT9__LCD_DATA09 0x1b0b0
393*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT10__LCD_DATA10 0x1b0b0
394*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT11__LCD_DATA11 0x1b0b0
395*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT12__LCD_DATA12 0x1b0b0
396*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT13__LCD_DATA13 0x1b0b0
397*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT14__LCD_DATA14 0x1b0b0
398*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT15__LCD_DATA15 0x1b0b0
399*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT16__LCD_DATA16 0x1b0b0
400*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT17__LCD_DATA17 0x1b0b0
401*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT18__LCD_DATA18 0x1b0b0
402*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT19__LCD_DATA19 0x1b0b0
403*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT20__LCD_DATA20 0x1b0b0
404*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT21__LCD_DATA21 0x1b0b0
405*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT22__LCD_DATA22 0x1b0b0
406*4882a593Smuzhiyun				MX6SL_PAD_LCD_DAT23__LCD_DATA23 0x1b0b0
407*4882a593Smuzhiyun				MX6SL_PAD_LCD_CLK__LCD_CLK 0x1b0b0
408*4882a593Smuzhiyun				MX6SL_PAD_LCD_ENABLE__LCD_ENABLE 0x1b0b0
409*4882a593Smuzhiyun				MX6SL_PAD_LCD_HSYNC__LCD_HSYNC 0x1b0b0
410*4882a593Smuzhiyun				MX6SL_PAD_LCD_VSYNC__LCD_VSYNC 0x1b0b0
411*4882a593Smuzhiyun			>;
412*4882a593Smuzhiyun		};
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun		pinctrl_led: ledgrp {
415*4882a593Smuzhiyun			fsl,pins = <
416*4882a593Smuzhiyun				MX6SL_PAD_HSIC_STROBE__GPIO3_IO20 0x17059
417*4882a593Smuzhiyun			>;
418*4882a593Smuzhiyun		};
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun		pinctrl_pwm1: pwmgrp {
421*4882a593Smuzhiyun			fsl,pins = <
422*4882a593Smuzhiyun				MX6SL_PAD_PWM1__PWM1_OUT 0x110b0
423*4882a593Smuzhiyun			>;
424*4882a593Smuzhiyun		};
425*4882a593Smuzhiyun
426*4882a593Smuzhiyun		pinctrl_reg_lcd_3v3: reglcd3v3grp {
427*4882a593Smuzhiyun			fsl,pins = <
428*4882a593Smuzhiyun				MX6SL_PAD_KEY_ROW5__GPIO4_IO03    0x17059
429*4882a593Smuzhiyun			>;
430*4882a593Smuzhiyun		};
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun		pinctrl_uart1: uart1grp {
433*4882a593Smuzhiyun			fsl,pins = <
434*4882a593Smuzhiyun				MX6SL_PAD_UART1_RXD__UART1_RX_DATA	0x1b0b1
435*4882a593Smuzhiyun				MX6SL_PAD_UART1_TXD__UART1_TX_DATA	0x1b0b1
436*4882a593Smuzhiyun			>;
437*4882a593Smuzhiyun		};
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun		pinctrl_usbotg1: usbotg1grp {
440*4882a593Smuzhiyun			fsl,pins = <
441*4882a593Smuzhiyun				MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID	0x17059
442*4882a593Smuzhiyun			>;
443*4882a593Smuzhiyun		};
444*4882a593Smuzhiyun
445*4882a593Smuzhiyun		pinctrl_usdhc1: usdhc1grp {
446*4882a593Smuzhiyun			fsl,pins = <
447*4882a593Smuzhiyun				MX6SL_PAD_SD1_CMD__SD1_CMD		0x17059
448*4882a593Smuzhiyun				MX6SL_PAD_SD1_CLK__SD1_CLK		0x10059
449*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT0__SD1_DATA0		0x17059
450*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT1__SD1_DATA1		0x17059
451*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT2__SD1_DATA2		0x17059
452*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT3__SD1_DATA3		0x17059
453*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT4__SD1_DATA4		0x17059
454*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT5__SD1_DATA5		0x17059
455*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT6__SD1_DATA6		0x17059
456*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT7__SD1_DATA7		0x17059
457*4882a593Smuzhiyun			>;
458*4882a593Smuzhiyun		};
459*4882a593Smuzhiyun
460*4882a593Smuzhiyun		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
461*4882a593Smuzhiyun			fsl,pins = <
462*4882a593Smuzhiyun				MX6SL_PAD_SD1_CMD__SD1_CMD		0x170b9
463*4882a593Smuzhiyun				MX6SL_PAD_SD1_CLK__SD1_CLK		0x100b9
464*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT0__SD1_DATA0		0x170b9
465*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT1__SD1_DATA1		0x170b9
466*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT2__SD1_DATA2		0x170b9
467*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT3__SD1_DATA3		0x170b9
468*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT4__SD1_DATA4		0x170b9
469*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT5__SD1_DATA5		0x170b9
470*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT6__SD1_DATA6		0x170b9
471*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT7__SD1_DATA7		0x170b9
472*4882a593Smuzhiyun			>;
473*4882a593Smuzhiyun		};
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
476*4882a593Smuzhiyun			fsl,pins = <
477*4882a593Smuzhiyun				MX6SL_PAD_SD1_CMD__SD1_CMD		0x170f9
478*4882a593Smuzhiyun				MX6SL_PAD_SD1_CLK__SD1_CLK		0x100f9
479*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT0__SD1_DATA0		0x170f9
480*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT1__SD1_DATA1		0x170f9
481*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT2__SD1_DATA2		0x170f9
482*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT3__SD1_DATA3		0x170f9
483*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT4__SD1_DATA4		0x170f9
484*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT5__SD1_DATA5		0x170f9
485*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT6__SD1_DATA6		0x170f9
486*4882a593Smuzhiyun				MX6SL_PAD_SD1_DAT7__SD1_DATA7		0x170f9
487*4882a593Smuzhiyun			>;
488*4882a593Smuzhiyun		};
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun		pinctrl_usdhc2: usdhc2grp {
491*4882a593Smuzhiyun			fsl,pins = <
492*4882a593Smuzhiyun				MX6SL_PAD_SD2_CMD__SD2_CMD		0x17059
493*4882a593Smuzhiyun				MX6SL_PAD_SD2_CLK__SD2_CLK		0x10059
494*4882a593Smuzhiyun				MX6SL_PAD_SD2_DAT0__SD2_DATA0		0x17059
495*4882a593Smuzhiyun				MX6SL_PAD_SD2_DAT1__SD2_DATA1		0x17059
496*4882a593Smuzhiyun				MX6SL_PAD_SD2_DAT2__SD2_DATA2		0x17059
497*4882a593Smuzhiyun				MX6SL_PAD_SD2_DAT3__SD2_DATA3		0x17059
498*4882a593Smuzhiyun			>;
499*4882a593Smuzhiyun		};
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
502*4882a593Smuzhiyun			fsl,pins = <
503*4882a593Smuzhiyun				MX6SL_PAD_SD2_CMD__SD2_CMD		0x170b9
504*4882a593Smuzhiyun				MX6SL_PAD_SD2_CLK__SD2_CLK		0x100b9
505*4882a593Smuzhiyun				MX6SL_PAD_SD2_DAT0__SD2_DATA0		0x170b9
506*4882a593Smuzhiyun				MX6SL_PAD_SD2_DAT1__SD2_DATA1		0x170b9
507*4882a593Smuzhiyun				MX6SL_PAD_SD2_DAT2__SD2_DATA2		0x170b9
508*4882a593Smuzhiyun				MX6SL_PAD_SD2_DAT3__SD2_DATA3		0x170b9
509*4882a593Smuzhiyun			>;
510*4882a593Smuzhiyun		};
511*4882a593Smuzhiyun
512*4882a593Smuzhiyun		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
513*4882a593Smuzhiyun			fsl,pins = <
514*4882a593Smuzhiyun				MX6SL_PAD_SD2_CMD__SD2_CMD		0x170f9
515*4882a593Smuzhiyun				MX6SL_PAD_SD2_CLK__SD2_CLK		0x100f9
516*4882a593Smuzhiyun				MX6SL_PAD_SD2_DAT0__SD2_DATA0		0x170f9
517*4882a593Smuzhiyun				MX6SL_PAD_SD2_DAT1__SD2_DATA1		0x170f9
518*4882a593Smuzhiyun				MX6SL_PAD_SD2_DAT2__SD2_DATA2		0x170f9
519*4882a593Smuzhiyun				MX6SL_PAD_SD2_DAT3__SD2_DATA3		0x170f9
520*4882a593Smuzhiyun			>;
521*4882a593Smuzhiyun		};
522*4882a593Smuzhiyun
523*4882a593Smuzhiyun		pinctrl_usdhc3: usdhc3grp {
524*4882a593Smuzhiyun			fsl,pins = <
525*4882a593Smuzhiyun				MX6SL_PAD_SD3_CMD__SD3_CMD		0x17059
526*4882a593Smuzhiyun				MX6SL_PAD_SD3_CLK__SD3_CLK		0x10059
527*4882a593Smuzhiyun				MX6SL_PAD_SD3_DAT0__SD3_DATA0		0x17059
528*4882a593Smuzhiyun				MX6SL_PAD_SD3_DAT1__SD3_DATA1		0x17059
529*4882a593Smuzhiyun				MX6SL_PAD_SD3_DAT2__SD3_DATA2		0x17059
530*4882a593Smuzhiyun				MX6SL_PAD_SD3_DAT3__SD3_DATA3		0x17059
531*4882a593Smuzhiyun			>;
532*4882a593Smuzhiyun		};
533*4882a593Smuzhiyun
534*4882a593Smuzhiyun		pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
535*4882a593Smuzhiyun			fsl,pins = <
536*4882a593Smuzhiyun				MX6SL_PAD_SD3_CMD__SD3_CMD		0x170b9
537*4882a593Smuzhiyun				MX6SL_PAD_SD3_CLK__SD3_CLK		0x100b9
538*4882a593Smuzhiyun				MX6SL_PAD_SD3_DAT0__SD3_DATA0		0x170b9
539*4882a593Smuzhiyun				MX6SL_PAD_SD3_DAT1__SD3_DATA1		0x170b9
540*4882a593Smuzhiyun				MX6SL_PAD_SD3_DAT2__SD3_DATA2		0x170b9
541*4882a593Smuzhiyun				MX6SL_PAD_SD3_DAT3__SD3_DATA3		0x170b9
542*4882a593Smuzhiyun			>;
543*4882a593Smuzhiyun		};
544*4882a593Smuzhiyun
545*4882a593Smuzhiyun		pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
546*4882a593Smuzhiyun			fsl,pins = <
547*4882a593Smuzhiyun				MX6SL_PAD_SD3_CMD__SD3_CMD		0x170f9
548*4882a593Smuzhiyun				MX6SL_PAD_SD3_CLK__SD3_CLK		0x100f9
549*4882a593Smuzhiyun				MX6SL_PAD_SD3_DAT0__SD3_DATA0		0x170f9
550*4882a593Smuzhiyun				MX6SL_PAD_SD3_DAT1__SD3_DATA1		0x170f9
551*4882a593Smuzhiyun				MX6SL_PAD_SD3_DAT2__SD3_DATA2		0x170f9
552*4882a593Smuzhiyun				MX6SL_PAD_SD3_DAT3__SD3_DATA3		0x170f9
553*4882a593Smuzhiyun			>;
554*4882a593Smuzhiyun		};
555*4882a593Smuzhiyun	};
556*4882a593Smuzhiyun};
557*4882a593Smuzhiyun
558*4882a593Smuzhiyun&kpp {
559*4882a593Smuzhiyun	pinctrl-names = "default";
560*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_kpp>;
561*4882a593Smuzhiyun	linux,keymap = <
562*4882a593Smuzhiyun			MATRIX_KEY(0x0, 0x0, KEY_UP)         /* ROW0, COL0 */
563*4882a593Smuzhiyun			MATRIX_KEY(0x0, 0x1, KEY_DOWN)       /* ROW0, COL1 */
564*4882a593Smuzhiyun			MATRIX_KEY(0x0, 0x2, KEY_ENTER)      /* ROW0, COL2 */
565*4882a593Smuzhiyun			MATRIX_KEY(0x1, 0x0, KEY_HOME)       /* ROW1, COL0 */
566*4882a593Smuzhiyun			MATRIX_KEY(0x1, 0x1, KEY_RIGHT)      /* ROW1, COL1 */
567*4882a593Smuzhiyun			MATRIX_KEY(0x1, 0x2, KEY_LEFT)       /* ROW1, COL2 */
568*4882a593Smuzhiyun			MATRIX_KEY(0x2, 0x0, KEY_VOLUMEDOWN) /* ROW2, COL0 */
569*4882a593Smuzhiyun			MATRIX_KEY(0x2, 0x1, KEY_VOLUMEUP)   /* ROW2, COL1 */
570*4882a593Smuzhiyun	>;
571*4882a593Smuzhiyun	status = "okay";
572*4882a593Smuzhiyun};
573*4882a593Smuzhiyun
574*4882a593Smuzhiyun&lcdif {
575*4882a593Smuzhiyun	pinctrl-names = "default";
576*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_lcd>;
577*4882a593Smuzhiyun	status = "okay";
578*4882a593Smuzhiyun
579*4882a593Smuzhiyun	port {
580*4882a593Smuzhiyun		display_out: endpoint {
581*4882a593Smuzhiyun			remote-endpoint = <&panel_in>;
582*4882a593Smuzhiyun		};
583*4882a593Smuzhiyun	};
584*4882a593Smuzhiyun};
585*4882a593Smuzhiyun
586*4882a593Smuzhiyun&pwm1 {
587*4882a593Smuzhiyun	#pwm-cells = <2>;
588*4882a593Smuzhiyun	pinctrl-names = "default";
589*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pwm1>;
590*4882a593Smuzhiyun	status = "okay";
591*4882a593Smuzhiyun};
592*4882a593Smuzhiyun
593*4882a593Smuzhiyun&reg_vdd1p1 {
594*4882a593Smuzhiyun	vin-supply = <&sw2_reg>;
595*4882a593Smuzhiyun};
596*4882a593Smuzhiyun
597*4882a593Smuzhiyun&reg_vdd2p5 {
598*4882a593Smuzhiyun	vin-supply = <&sw2_reg>;
599*4882a593Smuzhiyun};
600*4882a593Smuzhiyun
601*4882a593Smuzhiyun&snvs_poweroff {
602*4882a593Smuzhiyun	status = "okay";
603*4882a593Smuzhiyun};
604*4882a593Smuzhiyun
605*4882a593Smuzhiyun&ssi2 {
606*4882a593Smuzhiyun	status = "okay";
607*4882a593Smuzhiyun};
608*4882a593Smuzhiyun
609*4882a593Smuzhiyun&uart1 {
610*4882a593Smuzhiyun	pinctrl-names = "default";
611*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart1>;
612*4882a593Smuzhiyun	status = "okay";
613*4882a593Smuzhiyun};
614*4882a593Smuzhiyun
615*4882a593Smuzhiyun&usbotg1 {
616*4882a593Smuzhiyun	vbus-supply = <&reg_usb_otg1_vbus>;
617*4882a593Smuzhiyun	pinctrl-names = "default";
618*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usbotg1>;
619*4882a593Smuzhiyun	disable-over-current;
620*4882a593Smuzhiyun	status = "okay";
621*4882a593Smuzhiyun};
622*4882a593Smuzhiyun
623*4882a593Smuzhiyun&usbotg2 {
624*4882a593Smuzhiyun	vbus-supply = <&reg_usb_otg2_vbus>;
625*4882a593Smuzhiyun	dr_mode = "host";
626*4882a593Smuzhiyun	disable-over-current;
627*4882a593Smuzhiyun	status = "okay";
628*4882a593Smuzhiyun};
629*4882a593Smuzhiyun
630*4882a593Smuzhiyun&usdhc1 {
631*4882a593Smuzhiyun	pinctrl-names = "default", "state_100mhz", "state_200mhz";
632*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc1>;
633*4882a593Smuzhiyun	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
634*4882a593Smuzhiyun	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
635*4882a593Smuzhiyun	bus-width = <8>;
636*4882a593Smuzhiyun	cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
637*4882a593Smuzhiyun	wp-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>;
638*4882a593Smuzhiyun	status = "okay";
639*4882a593Smuzhiyun};
640*4882a593Smuzhiyun
641*4882a593Smuzhiyun&usdhc2 {
642*4882a593Smuzhiyun	pinctrl-names = "default", "state_100mhz", "state_200mhz";
643*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc2>;
644*4882a593Smuzhiyun	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
645*4882a593Smuzhiyun	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
646*4882a593Smuzhiyun	cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
647*4882a593Smuzhiyun	wp-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
648*4882a593Smuzhiyun	status = "okay";
649*4882a593Smuzhiyun};
650*4882a593Smuzhiyun
651*4882a593Smuzhiyun&usdhc3 {
652*4882a593Smuzhiyun	pinctrl-names = "default", "state_100mhz", "state_200mhz";
653*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc3>;
654*4882a593Smuzhiyun	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
655*4882a593Smuzhiyun	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
656*4882a593Smuzhiyun	cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
657*4882a593Smuzhiyun	status = "okay";
658*4882a593Smuzhiyun};
659