xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/imx6qdl-wandboard.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright 2013 Freescale Semiconductor, Inc.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Author: Fabio Estevam <fabio.estevam@freescale.com>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun/ {
11*4882a593Smuzhiyun	chosen {
12*4882a593Smuzhiyun		stdout-path = &uart1;
13*4882a593Smuzhiyun	};
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun	sound {
16*4882a593Smuzhiyun		compatible = "fsl,imx6-wandboard-sgtl5000",
17*4882a593Smuzhiyun			     "fsl,imx-audio-sgtl5000";
18*4882a593Smuzhiyun		model = "imx6-wandboard-sgtl5000";
19*4882a593Smuzhiyun		ssi-controller = <&ssi1>;
20*4882a593Smuzhiyun		audio-codec = <&codec>;
21*4882a593Smuzhiyun		audio-routing =
22*4882a593Smuzhiyun			"MIC_IN", "Mic Jack",
23*4882a593Smuzhiyun			"Mic Jack", "Mic Bias",
24*4882a593Smuzhiyun			"Headphone Jack", "HP_OUT";
25*4882a593Smuzhiyun		mux-int-port = <1>;
26*4882a593Smuzhiyun		mux-ext-port = <3>;
27*4882a593Smuzhiyun	};
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun	sound-spdif {
30*4882a593Smuzhiyun		compatible = "fsl,imx-audio-spdif";
31*4882a593Smuzhiyun		model = "imx-spdif";
32*4882a593Smuzhiyun		spdif-controller = <&spdif>;
33*4882a593Smuzhiyun		spdif-out;
34*4882a593Smuzhiyun	};
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun	reg_1p5v: regulator-1p5v {
37*4882a593Smuzhiyun		compatible = "regulator-fixed";
38*4882a593Smuzhiyun		regulator-name = "1P5V";
39*4882a593Smuzhiyun		regulator-min-microvolt = <1500000>;
40*4882a593Smuzhiyun		regulator-max-microvolt = <1500000>;
41*4882a593Smuzhiyun		regulator-always-on;
42*4882a593Smuzhiyun	};
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun	reg_1p8v: regulator-1p8v {
45*4882a593Smuzhiyun		compatible = "regulator-fixed";
46*4882a593Smuzhiyun		regulator-name = "1P8V";
47*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
48*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
49*4882a593Smuzhiyun		regulator-always-on;
50*4882a593Smuzhiyun	};
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun	reg_2p8v: regulator-2p8v {
53*4882a593Smuzhiyun		compatible = "regulator-fixed";
54*4882a593Smuzhiyun		regulator-name = "2P8V";
55*4882a593Smuzhiyun		regulator-min-microvolt = <2800000>;
56*4882a593Smuzhiyun		regulator-max-microvolt = <2800000>;
57*4882a593Smuzhiyun		regulator-always-on;
58*4882a593Smuzhiyun	};
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun	reg_2p5v: regulator-2p5v {
61*4882a593Smuzhiyun		compatible = "regulator-fixed";
62*4882a593Smuzhiyun		regulator-name = "2P5V";
63*4882a593Smuzhiyun		regulator-min-microvolt = <2500000>;
64*4882a593Smuzhiyun		regulator-max-microvolt = <2500000>;
65*4882a593Smuzhiyun		regulator-always-on;
66*4882a593Smuzhiyun	};
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun	reg_3p3v: regulator-3p3v {
69*4882a593Smuzhiyun		compatible = "regulator-fixed";
70*4882a593Smuzhiyun		regulator-name = "3P3V";
71*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
72*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
73*4882a593Smuzhiyun		regulator-always-on;
74*4882a593Smuzhiyun	};
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun	reg_usb_otg_vbus: regulator-usbotgvbus {
77*4882a593Smuzhiyun		compatible = "regulator-fixed";
78*4882a593Smuzhiyun		regulator-name = "usb_otg_vbus";
79*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
80*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
81*4882a593Smuzhiyun		pinctrl-names = "default";
82*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_usbotgvbus>;
83*4882a593Smuzhiyun		gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
84*4882a593Smuzhiyun	};
85*4882a593Smuzhiyun};
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun&audmux {
88*4882a593Smuzhiyun	pinctrl-names = "default";
89*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_audmux>;
90*4882a593Smuzhiyun	status = "okay";
91*4882a593Smuzhiyun};
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun&hdmi {
94*4882a593Smuzhiyun	ddc-i2c-bus = <&i2c1>;
95*4882a593Smuzhiyun	status = "okay";
96*4882a593Smuzhiyun};
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun&i2c1 {
99*4882a593Smuzhiyun	clock-frequency = <100000>;
100*4882a593Smuzhiyun	pinctrl-names = "default";
101*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c1>;
102*4882a593Smuzhiyun	status = "okay";
103*4882a593Smuzhiyun};
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun&i2c2 {
106*4882a593Smuzhiyun	clock-frequency = <100000>;
107*4882a593Smuzhiyun	pinctrl-names = "default";
108*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c2>;
109*4882a593Smuzhiyun	status = "okay";
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun	codec: sgtl5000@a {
112*4882a593Smuzhiyun		pinctrl-names = "default";
113*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_mclk>;
114*4882a593Smuzhiyun		compatible = "fsl,sgtl5000";
115*4882a593Smuzhiyun		reg = <0x0a>;
116*4882a593Smuzhiyun		clocks = <&clks IMX6QDL_CLK_CKO>;
117*4882a593Smuzhiyun		VDDA-supply = <&reg_2p5v>;
118*4882a593Smuzhiyun		VDDIO-supply = <&reg_3p3v>;
119*4882a593Smuzhiyun		lrclk-strength = <3>;
120*4882a593Smuzhiyun	};
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun	camera@3c {
123*4882a593Smuzhiyun		compatible = "ovti,ov5645";
124*4882a593Smuzhiyun		pinctrl-names = "default";
125*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_ov5645>;
126*4882a593Smuzhiyun		reg = <0x3c>;
127*4882a593Smuzhiyun		clocks = <&clks IMX6QDL_CLK_CKO2>;
128*4882a593Smuzhiyun		clock-names = "xclk";
129*4882a593Smuzhiyun		clock-frequency = <24000000>;
130*4882a593Smuzhiyun		vdddo-supply = <&reg_1p8v>;
131*4882a593Smuzhiyun		vdda-supply = <&reg_2p8v>;
132*4882a593Smuzhiyun		vddd-supply = <&reg_1p5v>;
133*4882a593Smuzhiyun		enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
134*4882a593Smuzhiyun		reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun		port {
137*4882a593Smuzhiyun			ov5645_to_mipi_csi2: endpoint {
138*4882a593Smuzhiyun				remote-endpoint = <&mipi_csi2_in>;
139*4882a593Smuzhiyun				clock-lanes = <0>;
140*4882a593Smuzhiyun				data-lanes = <1 2>;
141*4882a593Smuzhiyun			};
142*4882a593Smuzhiyun		};
143*4882a593Smuzhiyun	};
144*4882a593Smuzhiyun};
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun&iomuxc {
147*4882a593Smuzhiyun	pinctrl-names = "default";
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun	imx6qdl-wandboard {
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun		pinctrl_audmux: audmuxgrp {
152*4882a593Smuzhiyun			fsl,pins = <
153*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT7__AUD3_RXD		0x130b0
154*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT4__AUD3_TXC		0x130b0
155*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT5__AUD3_TXD		0x110b0
156*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS		0x130b0
157*4882a593Smuzhiyun			>;
158*4882a593Smuzhiyun		};
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun		pinctrl_enet: enetgrp {
161*4882a593Smuzhiyun			fsl,pins = <
162*4882a593Smuzhiyun				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
163*4882a593Smuzhiyun				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
164*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
165*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
166*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
167*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
168*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
169*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
170*4882a593Smuzhiyun				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
171*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
172*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
173*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
174*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
175*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
176*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
177*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
178*4882a593Smuzhiyun			>;
179*4882a593Smuzhiyun		};
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun		pinctrl_i2c1: i2c1grp {
182*4882a593Smuzhiyun			fsl,pins = <
183*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1
184*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1
185*4882a593Smuzhiyun			>;
186*4882a593Smuzhiyun		};
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun		pinctrl_i2c2: i2c2grp {
189*4882a593Smuzhiyun			fsl,pins = <
190*4882a593Smuzhiyun				MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
191*4882a593Smuzhiyun				MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
192*4882a593Smuzhiyun			>;
193*4882a593Smuzhiyun		};
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun		pinctrl_mclk: mclkgrp {
196*4882a593Smuzhiyun			fsl,pins = <
197*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_0__CCM_CLKO1		0x130b0
198*4882a593Smuzhiyun			>;
199*4882a593Smuzhiyun		};
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun		pinctrl_ov5645: ov5645grp {
202*4882a593Smuzhiyun			fsl,pins = <
203*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_3__CCM_CLKO2		0x000b0
204*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_6__GPIO1_IO06		0x1b0b0
205*4882a593Smuzhiyun				MX6QDL_PAD_KEY_COL4__GPIO4_IO14		0x1b0b0
206*4882a593Smuzhiyun			>;
207*4882a593Smuzhiyun		};
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun		pinctrl_spdif: spdifgrp {
210*4882a593Smuzhiyun			fsl,pins = <
211*4882a593Smuzhiyun				MX6QDL_PAD_ENET_RXD0__SPDIF_OUT		0x1b0b0
212*4882a593Smuzhiyun			>;
213*4882a593Smuzhiyun		};
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun		pinctrl_uart1: uart1grp {
216*4882a593Smuzhiyun			fsl,pins = <
217*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA	0x1b0b1
218*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA	0x1b0b1
219*4882a593Smuzhiyun			>;
220*4882a593Smuzhiyun		};
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun		pinctrl_uart3: uart3grp {
223*4882a593Smuzhiyun			fsl,pins = <
224*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D24__UART3_TX_DATA	0x1b0b1
225*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D25__UART3_RX_DATA	0x1b0b1
226*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D23__UART3_CTS_B		0x1b0b1
227*4882a593Smuzhiyun				MX6QDL_PAD_EIM_EB3__UART3_RTS_B		0x1b0b1
228*4882a593Smuzhiyun			>;
229*4882a593Smuzhiyun		};
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun		pinctrl_usbotg: usbotggrp {
232*4882a593Smuzhiyun			fsl,pins = <
233*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x17059
234*4882a593Smuzhiyun			>;
235*4882a593Smuzhiyun		};
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun		pinctrl_usbotgvbus: usbotgvbusgrp {
238*4882a593Smuzhiyun			fsl,pins = <
239*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D22__GPIO3_IO22		0x130b0
240*4882a593Smuzhiyun			>;
241*4882a593Smuzhiyun		};
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun		pinctrl_usdhc1: usdhc1grp {
244*4882a593Smuzhiyun			fsl,pins = <
245*4882a593Smuzhiyun				MX6QDL_PAD_SD1_CMD__SD1_CMD		0x17059
246*4882a593Smuzhiyun				MX6QDL_PAD_SD1_CLK__SD1_CLK		0x10059
247*4882a593Smuzhiyun				MX6QDL_PAD_SD1_DAT0__SD1_DATA0		0x17059
248*4882a593Smuzhiyun				MX6QDL_PAD_SD1_DAT1__SD1_DATA1		0x17059
249*4882a593Smuzhiyun				MX6QDL_PAD_SD1_DAT2__SD1_DATA2		0x17059
250*4882a593Smuzhiyun				MX6QDL_PAD_SD1_DAT3__SD1_DATA3		0x17059
251*4882a593Smuzhiyun			>;
252*4882a593Smuzhiyun		};
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun		pinctrl_usdhc2: usdhc2grp {
255*4882a593Smuzhiyun			fsl,pins = <
256*4882a593Smuzhiyun				MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
257*4882a593Smuzhiyun				MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10059
258*4882a593Smuzhiyun				MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
259*4882a593Smuzhiyun				MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
260*4882a593Smuzhiyun				MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
261*4882a593Smuzhiyun				MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
262*4882a593Smuzhiyun			>;
263*4882a593Smuzhiyun		};
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun		pinctrl_usdhc3: usdhc3grp {
266*4882a593Smuzhiyun			fsl,pins = <
267*4882a593Smuzhiyun				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
268*4882a593Smuzhiyun				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
269*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
270*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
271*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
272*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
273*4882a593Smuzhiyun			>;
274*4882a593Smuzhiyun		};
275*4882a593Smuzhiyun	};
276*4882a593Smuzhiyun};
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun&fec {
279*4882a593Smuzhiyun	pinctrl-names = "default";
280*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_enet>;
281*4882a593Smuzhiyun	phy-mode = "rgmii-id";
282*4882a593Smuzhiyun	phy-handle = <&ethphy>;
283*4882a593Smuzhiyun	phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
284*4882a593Smuzhiyun	status = "okay";
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun	mdio {
287*4882a593Smuzhiyun		#address-cells = <1>;
288*4882a593Smuzhiyun		#size-cells = <0>;
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun		ethphy: ethernet-phy@1 {
291*4882a593Smuzhiyun			reg = <1>;
292*4882a593Smuzhiyun			qca,clk-out-frequency = <125000000>;
293*4882a593Smuzhiyun		};
294*4882a593Smuzhiyun	};
295*4882a593Smuzhiyun};
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun&mipi_csi {
298*4882a593Smuzhiyun	status = "okay";
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun	port@0 {
301*4882a593Smuzhiyun		reg = <0>;
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun		mipi_csi2_in: endpoint {
304*4882a593Smuzhiyun			remote-endpoint = <&ov5645_to_mipi_csi2>;
305*4882a593Smuzhiyun			clock-lanes = <0>;
306*4882a593Smuzhiyun			data-lanes = <1 2>;
307*4882a593Smuzhiyun		};
308*4882a593Smuzhiyun	};
309*4882a593Smuzhiyun};
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun&spdif {
312*4882a593Smuzhiyun	pinctrl-names = "default";
313*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_spdif>;
314*4882a593Smuzhiyun	status = "okay";
315*4882a593Smuzhiyun};
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun&ssi1 {
318*4882a593Smuzhiyun	status = "okay";
319*4882a593Smuzhiyun};
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun&uart1 {
322*4882a593Smuzhiyun	pinctrl-names = "default";
323*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart1>;
324*4882a593Smuzhiyun	status = "okay";
325*4882a593Smuzhiyun};
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun&uart3 {
328*4882a593Smuzhiyun	pinctrl-names = "default";
329*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart3>;
330*4882a593Smuzhiyun	uart-has-rtscts;
331*4882a593Smuzhiyun	status = "okay";
332*4882a593Smuzhiyun};
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun&usbh1 {
335*4882a593Smuzhiyun	status = "okay";
336*4882a593Smuzhiyun};
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun&usbotg {
339*4882a593Smuzhiyun	vbus-supply = <&reg_usb_otg_vbus>;
340*4882a593Smuzhiyun	pinctrl-names = "default";
341*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usbotg>;
342*4882a593Smuzhiyun	disable-over-current;
343*4882a593Smuzhiyun	dr_mode = "otg";
344*4882a593Smuzhiyun	status = "okay";
345*4882a593Smuzhiyun};
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun&usdhc1 {
348*4882a593Smuzhiyun	pinctrl-names = "default";
349*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc1>;
350*4882a593Smuzhiyun	cd-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
351*4882a593Smuzhiyun	status = "okay";
352*4882a593Smuzhiyun};
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun&usdhc3 {
355*4882a593Smuzhiyun	pinctrl-names = "default";
356*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc3>;
357*4882a593Smuzhiyun	cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
358*4882a593Smuzhiyun	status = "okay";
359*4882a593Smuzhiyun};
360