1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright 2013 Freescale Semiconductor, Inc. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Author: Fabio Estevam <fabio.estevam@freescale.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun aliases { 12*4882a593Smuzhiyun backlight = &backlight; 13*4882a593Smuzhiyun panelchan = &panelchan; 14*4882a593Smuzhiyun panel7 = &panel7; 15*4882a593Smuzhiyun touchscreenp7 = &touchscreenp7; 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun chosen { 19*4882a593Smuzhiyun stdout-path = &uart2; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun backlight: backlight { 23*4882a593Smuzhiyun compatible = "gpio-backlight"; 24*4882a593Smuzhiyun gpios = <&gpio1 4 0>; 25*4882a593Smuzhiyun default-on; 26*4882a593Smuzhiyun status = "disabled"; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun gpio-poweroff { 30*4882a593Smuzhiyun compatible = "gpio-poweroff"; 31*4882a593Smuzhiyun gpios = <&gpio2 4 0>; 32*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_power_off>; 33*4882a593Smuzhiyun pinctrl-names = "default"; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun memory@10000000 { 37*4882a593Smuzhiyun device_type = "memory"; 38*4882a593Smuzhiyun reg = <0x10000000 0x40000000>; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun panel7: panel7 { 42*4882a593Smuzhiyun /* 43*4882a593Smuzhiyun * in reality it is a -20t (parallel) model, 44*4882a593Smuzhiyun * but with LVDS bridge chip attached, 45*4882a593Smuzhiyun * so it is equivalent to -19t model in drive 46*4882a593Smuzhiyun * characteristics 47*4882a593Smuzhiyun */ 48*4882a593Smuzhiyun compatible = "urt,umsh-8596md-19t"; 49*4882a593Smuzhiyun pinctrl-names = "default"; 50*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_panel>; 51*4882a593Smuzhiyun power-supply = <®_panel>; 52*4882a593Smuzhiyun backlight = <&backlight>; 53*4882a593Smuzhiyun status = "disabled"; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun port { 56*4882a593Smuzhiyun panel_in: endpoint { 57*4882a593Smuzhiyun remote-endpoint = <&lvds0_out>; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun regulators { 63*4882a593Smuzhiyun compatible = "simple-bus"; 64*4882a593Smuzhiyun #address-cells = <1>; 65*4882a593Smuzhiyun #size-cells = <0>; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun reg_usb_h1_vbus: regulator@0 { 68*4882a593Smuzhiyun compatible = "regulator-fixed"; 69*4882a593Smuzhiyun reg = <0>; 70*4882a593Smuzhiyun regulator-name = "usb_h1_vbus"; 71*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 72*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 73*4882a593Smuzhiyun enable-active-high; 74*4882a593Smuzhiyun startup-delay-us = <2>; /* USB2415 requires a POR of 1 us minimum */ 75*4882a593Smuzhiyun gpio = <&gpio7 12 0>; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun reg_panel: regulator@1 { 79*4882a593Smuzhiyun compatible = "regulator-fixed"; 80*4882a593Smuzhiyun reg = <1>; 81*4882a593Smuzhiyun regulator-name = "lcd_panel"; 82*4882a593Smuzhiyun enable-active-high; 83*4882a593Smuzhiyun gpio = <&gpio1 2 0>; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun sound { 88*4882a593Smuzhiyun compatible = "fsl,imx6q-udoo-ac97", 89*4882a593Smuzhiyun "fsl,imx-audio-ac97"; 90*4882a593Smuzhiyun model = "fsl,imx6q-udoo-ac97"; 91*4882a593Smuzhiyun audio-cpu = <&ssi1>; 92*4882a593Smuzhiyun audio-routing = 93*4882a593Smuzhiyun "RX", "Mic Jack", 94*4882a593Smuzhiyun "Headphone Jack", "TX"; 95*4882a593Smuzhiyun mux-int-port = <1>; 96*4882a593Smuzhiyun mux-ext-port = <6>; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun}; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun&fec { 101*4882a593Smuzhiyun pinctrl-names = "default"; 102*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_enet>; 103*4882a593Smuzhiyun phy-mode = "rgmii-id"; 104*4882a593Smuzhiyun status = "okay"; 105*4882a593Smuzhiyun}; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun&hdmi { 108*4882a593Smuzhiyun ddc-i2c-bus = <&i2c2>; 109*4882a593Smuzhiyun status = "okay"; 110*4882a593Smuzhiyun}; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun&i2c2 { 113*4882a593Smuzhiyun clock-frequency = <100000>; 114*4882a593Smuzhiyun pinctrl-names = "default"; 115*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c2>; 116*4882a593Smuzhiyun status = "okay"; 117*4882a593Smuzhiyun}; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun&i2c3 { 120*4882a593Smuzhiyun clock-frequency = <100000>; 121*4882a593Smuzhiyun pinctrl-names = "default"; 122*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c3>; 123*4882a593Smuzhiyun status = "okay"; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun touchscreenp7: touchscreenp7@55 { 126*4882a593Smuzhiyun compatible = "sitronix,st1232"; 127*4882a593Smuzhiyun pinctrl-names = "default"; 128*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_touchscreenp7>; 129*4882a593Smuzhiyun reg = <0x55>; 130*4882a593Smuzhiyun interrupt-parent = <&gpio1>; 131*4882a593Smuzhiyun interrupts = <13 8>; 132*4882a593Smuzhiyun gpios = <&gpio1 15 0>; 133*4882a593Smuzhiyun status = "disabled"; 134*4882a593Smuzhiyun }; 135*4882a593Smuzhiyun}; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun&iomuxc { 138*4882a593Smuzhiyun imx6q-udoo { 139*4882a593Smuzhiyun pinctrl_enet: enetgrp { 140*4882a593Smuzhiyun fsl,pins = < 141*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 142*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 143*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 144*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 145*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 146*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 147*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 148*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 149*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 150*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 151*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 152*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 153*4882a593Smuzhiyun MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 154*4882a593Smuzhiyun MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 155*4882a593Smuzhiyun MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 156*4882a593Smuzhiyun MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 157*4882a593Smuzhiyun >; 158*4882a593Smuzhiyun }; 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun pinctrl_i2c2: i2c2grp { 161*4882a593Smuzhiyun fsl,pins = < 162*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 163*4882a593Smuzhiyun MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 164*4882a593Smuzhiyun >; 165*4882a593Smuzhiyun }; 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun pinctrl_i2c3: i2c3grp { 168*4882a593Smuzhiyun fsl,pins = < 169*4882a593Smuzhiyun MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001f8b1 170*4882a593Smuzhiyun MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001f8b1 171*4882a593Smuzhiyun >; 172*4882a593Smuzhiyun }; 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun pinctrl_panel: panelgrp { 175*4882a593Smuzhiyun fsl,pins = < 176*4882a593Smuzhiyun MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x70 177*4882a593Smuzhiyun MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x70 178*4882a593Smuzhiyun >; 179*4882a593Smuzhiyun }; 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun pinctrl_power_off: poweroffgrp { 182*4882a593Smuzhiyun fsl,pins = < 183*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x30 184*4882a593Smuzhiyun >; 185*4882a593Smuzhiyun }; 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun pinctrl_touchscreenp7: touchscreenp7grp { 188*4882a593Smuzhiyun fsl,pins = < 189*4882a593Smuzhiyun MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x70 190*4882a593Smuzhiyun MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0 191*4882a593Smuzhiyun >; 192*4882a593Smuzhiyun }; 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun pinctrl_uart2: uart2grp { 195*4882a593Smuzhiyun fsl,pins = < 196*4882a593Smuzhiyun MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 197*4882a593Smuzhiyun MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 198*4882a593Smuzhiyun >; 199*4882a593Smuzhiyun }; 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun pinctrl_uart4: uart4grp { 202*4882a593Smuzhiyun fsl,pins = < 203*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 204*4882a593Smuzhiyun MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 205*4882a593Smuzhiyun >; 206*4882a593Smuzhiyun }; 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun pinctrl_usbh: usbhgrp { 209*4882a593Smuzhiyun fsl,pins = < 210*4882a593Smuzhiyun MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 211*4882a593Smuzhiyun MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x130b0 212*4882a593Smuzhiyun >; 213*4882a593Smuzhiyun }; 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun pinctrl_usbotg: usbotg { 216*4882a593Smuzhiyun fsl,pins = < 217*4882a593Smuzhiyun MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 218*4882a593Smuzhiyun MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x17059 219*4882a593Smuzhiyun MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x17059 220*4882a593Smuzhiyun >; 221*4882a593Smuzhiyun }; 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun pinctrl_usdhc3: usdhc3grp { 224*4882a593Smuzhiyun fsl,pins = < 225*4882a593Smuzhiyun MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 226*4882a593Smuzhiyun MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 227*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 228*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 229*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 230*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 231*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 232*4882a593Smuzhiyun >; 233*4882a593Smuzhiyun }; 234*4882a593Smuzhiyun 235*4882a593Smuzhiyun pinctrl_ac97_running: ac97running { 236*4882a593Smuzhiyun fsl,pins = < 237*4882a593Smuzhiyun MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x1b0b0 238*4882a593Smuzhiyun MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x1b0b0 239*4882a593Smuzhiyun MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x13080 240*4882a593Smuzhiyun MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x13080 241*4882a593Smuzhiyun MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 242*4882a593Smuzhiyun >; 243*4882a593Smuzhiyun }; 244*4882a593Smuzhiyun 245*4882a593Smuzhiyun pinctrl_ac97_warm_reset: ac97warmreset { 246*4882a593Smuzhiyun fsl,pins = < 247*4882a593Smuzhiyun MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x1b0b0 248*4882a593Smuzhiyun MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b0 249*4882a593Smuzhiyun MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x13080 250*4882a593Smuzhiyun MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x13080 251*4882a593Smuzhiyun MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 252*4882a593Smuzhiyun >; 253*4882a593Smuzhiyun }; 254*4882a593Smuzhiyun 255*4882a593Smuzhiyun pinctrl_ac97_reset: ac97reset { 256*4882a593Smuzhiyun fsl,pins = < 257*4882a593Smuzhiyun MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 258*4882a593Smuzhiyun MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b0 259*4882a593Smuzhiyun MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x13080 260*4882a593Smuzhiyun MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x13080 261*4882a593Smuzhiyun MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 262*4882a593Smuzhiyun >; 263*4882a593Smuzhiyun }; 264*4882a593Smuzhiyun }; 265*4882a593Smuzhiyun}; 266*4882a593Smuzhiyun 267*4882a593Smuzhiyun&ldb { 268*4882a593Smuzhiyun status = "okay"; 269*4882a593Smuzhiyun 270*4882a593Smuzhiyun panelchan: lvds-channel@0 { 271*4882a593Smuzhiyun port@4 { 272*4882a593Smuzhiyun reg = <4>; 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun lvds0_out: endpoint { 275*4882a593Smuzhiyun remote-endpoint = <&panel_in>; 276*4882a593Smuzhiyun }; 277*4882a593Smuzhiyun }; 278*4882a593Smuzhiyun }; 279*4882a593Smuzhiyun}; 280*4882a593Smuzhiyun 281*4882a593Smuzhiyun&uart2 { 282*4882a593Smuzhiyun pinctrl-names = "default"; 283*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart2>; 284*4882a593Smuzhiyun status = "okay"; 285*4882a593Smuzhiyun}; 286*4882a593Smuzhiyun 287*4882a593Smuzhiyun&uart4 { 288*4882a593Smuzhiyun pinctrl-names = "default"; 289*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart4>; 290*4882a593Smuzhiyun status = "okay"; 291*4882a593Smuzhiyun}; 292*4882a593Smuzhiyun 293*4882a593Smuzhiyun&usbh1 { 294*4882a593Smuzhiyun pinctrl-names = "default"; 295*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usbh>; 296*4882a593Smuzhiyun vbus-supply = <®_usb_h1_vbus>; 297*4882a593Smuzhiyun clocks = <&clks IMX6QDL_CLK_CKO>; 298*4882a593Smuzhiyun status = "okay"; 299*4882a593Smuzhiyun}; 300*4882a593Smuzhiyun 301*4882a593Smuzhiyun&usbotg { 302*4882a593Smuzhiyun pinctrl-names = "default"; 303*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usbotg>; 304*4882a593Smuzhiyun status = "okay"; 305*4882a593Smuzhiyun}; 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun&usdhc3 { 308*4882a593Smuzhiyun pinctrl-names = "default"; 309*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc3>; 310*4882a593Smuzhiyun cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; 311*4882a593Smuzhiyun status = "okay"; 312*4882a593Smuzhiyun}; 313*4882a593Smuzhiyun 314*4882a593Smuzhiyun&audmux { 315*4882a593Smuzhiyun status = "okay"; 316*4882a593Smuzhiyun}; 317*4882a593Smuzhiyun 318*4882a593Smuzhiyun&ssi1 { 319*4882a593Smuzhiyun cell-index = <0>; 320*4882a593Smuzhiyun fsl,mode = "ac97-slave"; 321*4882a593Smuzhiyun pinctrl-names = "ac97-running", "ac97-reset", "ac97-warm-reset"; 322*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_ac97_running>; 323*4882a593Smuzhiyun pinctrl-1 = <&pinctrl_ac97_reset>; 324*4882a593Smuzhiyun pinctrl-2 = <&pinctrl_ac97_warm_reset>; 325*4882a593Smuzhiyun ac97-gpios = <&gpio4 19 0 &gpio4 18 0 &gpio2 30 0>; 326*4882a593Smuzhiyun status = "okay"; 327*4882a593Smuzhiyun}; 328