xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/imx6qdl-sabresd.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun//
3*4882a593Smuzhiyun// Copyright 2012 Freescale Semiconductor, Inc.
4*4882a593Smuzhiyun// Copyright 2011 Linaro Ltd.
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun#include <dt-bindings/clock/imx6qdl-clock.h>
7*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
8*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun/ {
11*4882a593Smuzhiyun	chosen {
12*4882a593Smuzhiyun		stdout-path = &uart1;
13*4882a593Smuzhiyun	};
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun	memory@10000000 {
16*4882a593Smuzhiyun		device_type = "memory";
17*4882a593Smuzhiyun		reg = <0x10000000 0x40000000>;
18*4882a593Smuzhiyun	};
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun	reg_usb_otg_vbus: regulator-usb-otg-vbus {
21*4882a593Smuzhiyun		compatible = "regulator-fixed";
22*4882a593Smuzhiyun		regulator-name = "usb_otg_vbus";
23*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
24*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
25*4882a593Smuzhiyun		gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
26*4882a593Smuzhiyun		enable-active-high;
27*4882a593Smuzhiyun		vin-supply = <&swbst_reg>;
28*4882a593Smuzhiyun	};
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun	reg_usb_h1_vbus: regulator-usb-h1-vbus {
31*4882a593Smuzhiyun		compatible = "regulator-fixed";
32*4882a593Smuzhiyun		regulator-name = "usb_h1_vbus";
33*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
34*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
35*4882a593Smuzhiyun		gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
36*4882a593Smuzhiyun		enable-active-high;
37*4882a593Smuzhiyun		vin-supply = <&swbst_reg>;
38*4882a593Smuzhiyun	};
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun	reg_audio: regulator-audio {
41*4882a593Smuzhiyun		compatible = "regulator-fixed";
42*4882a593Smuzhiyun		regulator-name = "wm8962-supply";
43*4882a593Smuzhiyun		gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>;
44*4882a593Smuzhiyun		enable-active-high;
45*4882a593Smuzhiyun	};
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun	reg_pcie: regulator-pcie {
48*4882a593Smuzhiyun		compatible = "regulator-fixed";
49*4882a593Smuzhiyun		pinctrl-names = "default";
50*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_pcie_reg>;
51*4882a593Smuzhiyun		regulator-name = "MPCIE_3V3";
52*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
53*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
54*4882a593Smuzhiyun		gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>;
55*4882a593Smuzhiyun		enable-active-high;
56*4882a593Smuzhiyun	};
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun	reg_sensors: regulator-sensors {
59*4882a593Smuzhiyun		compatible = "regulator-fixed";
60*4882a593Smuzhiyun		pinctrl-names = "default";
61*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_sensors_reg>;
62*4882a593Smuzhiyun		regulator-name = "sensors-supply";
63*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
64*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
65*4882a593Smuzhiyun		gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
66*4882a593Smuzhiyun		enable-active-high;
67*4882a593Smuzhiyun	};
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun	gpio-keys {
70*4882a593Smuzhiyun		compatible = "gpio-keys";
71*4882a593Smuzhiyun		pinctrl-names = "default";
72*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_gpio_keys>;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun		power {
75*4882a593Smuzhiyun			label = "Power Button";
76*4882a593Smuzhiyun			gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
77*4882a593Smuzhiyun			wakeup-source;
78*4882a593Smuzhiyun			linux,code = <KEY_POWER>;
79*4882a593Smuzhiyun		};
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun		volume-up {
82*4882a593Smuzhiyun			label = "Volume Up";
83*4882a593Smuzhiyun			gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
84*4882a593Smuzhiyun			wakeup-source;
85*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEUP>;
86*4882a593Smuzhiyun		};
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun		volume-down {
89*4882a593Smuzhiyun			label = "Volume Down";
90*4882a593Smuzhiyun			gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
91*4882a593Smuzhiyun			wakeup-source;
92*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEDOWN>;
93*4882a593Smuzhiyun		};
94*4882a593Smuzhiyun	};
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun	sound {
97*4882a593Smuzhiyun		compatible = "fsl,imx6q-sabresd-wm8962",
98*4882a593Smuzhiyun			   "fsl,imx-audio-wm8962";
99*4882a593Smuzhiyun		model = "wm8962-audio";
100*4882a593Smuzhiyun		ssi-controller = <&ssi2>;
101*4882a593Smuzhiyun		audio-codec = <&codec>;
102*4882a593Smuzhiyun		audio-routing =
103*4882a593Smuzhiyun			"Headphone Jack", "HPOUTL",
104*4882a593Smuzhiyun			"Headphone Jack", "HPOUTR",
105*4882a593Smuzhiyun			"Ext Spk", "SPKOUTL",
106*4882a593Smuzhiyun			"Ext Spk", "SPKOUTR",
107*4882a593Smuzhiyun			"AMIC", "MICBIAS",
108*4882a593Smuzhiyun			"IN3R", "AMIC",
109*4882a593Smuzhiyun			"DMIC", "MICBIAS",
110*4882a593Smuzhiyun			"DMICDAT", "DMIC";
111*4882a593Smuzhiyun		mux-int-port = <2>;
112*4882a593Smuzhiyun		mux-ext-port = <3>;
113*4882a593Smuzhiyun		hp-det-gpio = <&gpio7 8 GPIO_ACTIVE_LOW>;
114*4882a593Smuzhiyun		mic-det-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
115*4882a593Smuzhiyun	};
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun	backlight_lvds: backlight-lvds {
118*4882a593Smuzhiyun		compatible = "pwm-backlight";
119*4882a593Smuzhiyun		pwms = <&pwm1 0 5000000>;
120*4882a593Smuzhiyun		brightness-levels = <0 4 8 16 32 64 128 255>;
121*4882a593Smuzhiyun		default-brightness-level = <7>;
122*4882a593Smuzhiyun		status = "okay";
123*4882a593Smuzhiyun	};
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun	leds {
126*4882a593Smuzhiyun		compatible = "gpio-leds";
127*4882a593Smuzhiyun		pinctrl-names = "default";
128*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_gpio_leds>;
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun		red {
131*4882a593Smuzhiyun			gpios = <&gpio1 2 0>;
132*4882a593Smuzhiyun			default-state = "on";
133*4882a593Smuzhiyun		};
134*4882a593Smuzhiyun	};
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun	panel {
137*4882a593Smuzhiyun		compatible = "hannstar,hsd100pxn1";
138*4882a593Smuzhiyun		backlight = <&backlight_lvds>;
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun		port {
141*4882a593Smuzhiyun			panel_in: endpoint {
142*4882a593Smuzhiyun				remote-endpoint = <&lvds0_out>;
143*4882a593Smuzhiyun			};
144*4882a593Smuzhiyun		};
145*4882a593Smuzhiyun	};
146*4882a593Smuzhiyun};
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun&ipu1_csi0_from_ipu1_csi0_mux {
149*4882a593Smuzhiyun	bus-width = <8>;
150*4882a593Smuzhiyun	data-shift = <12>; /* Lines 19:12 used */
151*4882a593Smuzhiyun	hsync-active = <1>;
152*4882a593Smuzhiyun	vsync-active = <1>;
153*4882a593Smuzhiyun};
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun&ipu1_csi0_mux_from_parallel_sensor {
156*4882a593Smuzhiyun	remote-endpoint = <&ov5642_to_ipu1_csi0_mux>;
157*4882a593Smuzhiyun};
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun&ipu1_csi0 {
160*4882a593Smuzhiyun	pinctrl-names = "default";
161*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_ipu1_csi0>;
162*4882a593Smuzhiyun};
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun&mipi_csi {
165*4882a593Smuzhiyun	status = "okay";
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun	port@0 {
168*4882a593Smuzhiyun		reg = <0>;
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun		mipi_csi2_in: endpoint {
171*4882a593Smuzhiyun			remote-endpoint = <&ov5640_to_mipi_csi2>;
172*4882a593Smuzhiyun			clock-lanes = <0>;
173*4882a593Smuzhiyun			data-lanes = <1 2>;
174*4882a593Smuzhiyun		};
175*4882a593Smuzhiyun	};
176*4882a593Smuzhiyun};
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun&audmux {
179*4882a593Smuzhiyun	pinctrl-names = "default";
180*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_audmux>;
181*4882a593Smuzhiyun	status = "okay";
182*4882a593Smuzhiyun};
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun&clks {
185*4882a593Smuzhiyun	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
186*4882a593Smuzhiyun			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
187*4882a593Smuzhiyun	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
188*4882a593Smuzhiyun				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
189*4882a593Smuzhiyun};
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun&ecspi1 {
192*4882a593Smuzhiyun	cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
193*4882a593Smuzhiyun	pinctrl-names = "default";
194*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_ecspi1>;
195*4882a593Smuzhiyun	status = "okay";
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun	flash: flash@0 {
198*4882a593Smuzhiyun		#address-cells = <1>;
199*4882a593Smuzhiyun		#size-cells = <1>;
200*4882a593Smuzhiyun		compatible = "st,m25p32", "jedec,spi-nor";
201*4882a593Smuzhiyun		spi-max-frequency = <20000000>;
202*4882a593Smuzhiyun		reg = <0>;
203*4882a593Smuzhiyun	};
204*4882a593Smuzhiyun};
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun&fec {
207*4882a593Smuzhiyun	pinctrl-names = "default";
208*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_enet>;
209*4882a593Smuzhiyun	phy-mode = "rgmii-id";
210*4882a593Smuzhiyun	phy-handle = <&phy>;
211*4882a593Smuzhiyun	fsl,magic-packet;
212*4882a593Smuzhiyun	status = "okay";
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun	mdio {
215*4882a593Smuzhiyun		#address-cells = <1>;
216*4882a593Smuzhiyun		#size-cells = <0>;
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun		phy: ethernet-phy@1 {
219*4882a593Smuzhiyun			reg = <1>;
220*4882a593Smuzhiyun			qca,clk-out-frequency = <125000000>;
221*4882a593Smuzhiyun			reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
222*4882a593Smuzhiyun			reset-assert-us = <10000>;
223*4882a593Smuzhiyun		};
224*4882a593Smuzhiyun	};
225*4882a593Smuzhiyun};
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun&hdmi {
228*4882a593Smuzhiyun	pinctrl-names = "default";
229*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_hdmi_cec>;
230*4882a593Smuzhiyun	ddc-i2c-bus = <&i2c2>;
231*4882a593Smuzhiyun	status = "okay";
232*4882a593Smuzhiyun};
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun&i2c1 {
235*4882a593Smuzhiyun	clock-frequency = <100000>;
236*4882a593Smuzhiyun	pinctrl-names = "default";
237*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c1>;
238*4882a593Smuzhiyun	status = "okay";
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun	codec: wm8962@1a {
241*4882a593Smuzhiyun		compatible = "wlf,wm8962";
242*4882a593Smuzhiyun		reg = <0x1a>;
243*4882a593Smuzhiyun		clocks = <&clks IMX6QDL_CLK_CKO>;
244*4882a593Smuzhiyun		DCVDD-supply = <&reg_audio>;
245*4882a593Smuzhiyun		DBVDD-supply = <&reg_audio>;
246*4882a593Smuzhiyun		AVDD-supply = <&reg_audio>;
247*4882a593Smuzhiyun		CPVDD-supply = <&reg_audio>;
248*4882a593Smuzhiyun		MICVDD-supply = <&reg_audio>;
249*4882a593Smuzhiyun		PLLVDD-supply = <&reg_audio>;
250*4882a593Smuzhiyun		SPKVDD1-supply = <&reg_audio>;
251*4882a593Smuzhiyun		SPKVDD2-supply = <&reg_audio>;
252*4882a593Smuzhiyun		gpio-cfg = <
253*4882a593Smuzhiyun			0x0000 /* 0:Default */
254*4882a593Smuzhiyun			0x0000 /* 1:Default */
255*4882a593Smuzhiyun			0x0013 /* 2:FN_DMICCLK */
256*4882a593Smuzhiyun			0x0000 /* 3:Default */
257*4882a593Smuzhiyun			0x8014 /* 4:FN_DMICCDAT */
258*4882a593Smuzhiyun			0x0000 /* 5:Default */
259*4882a593Smuzhiyun		>;
260*4882a593Smuzhiyun	};
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun	accelerometer@1c {
263*4882a593Smuzhiyun		compatible = "fsl,mma8451";
264*4882a593Smuzhiyun		reg = <0x1c>;
265*4882a593Smuzhiyun		pinctrl-names = "default";
266*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_i2c1_mma8451_int>;
267*4882a593Smuzhiyun		interrupt-parent = <&gpio1>;
268*4882a593Smuzhiyun		interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
269*4882a593Smuzhiyun		vdd-supply = <&reg_sensors>;
270*4882a593Smuzhiyun		vddio-supply = <&reg_sensors>;
271*4882a593Smuzhiyun	};
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun	ov5642: camera@3c {
274*4882a593Smuzhiyun		compatible = "ovti,ov5642";
275*4882a593Smuzhiyun		pinctrl-names = "default";
276*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_ov5642>;
277*4882a593Smuzhiyun		clocks = <&clks IMX6QDL_CLK_CKO>;
278*4882a593Smuzhiyun		clock-names = "xclk";
279*4882a593Smuzhiyun		reg = <0x3c>;
280*4882a593Smuzhiyun		DOVDD-supply = <&vgen4_reg>; /* 1.8v */
281*4882a593Smuzhiyun		AVDD-supply = <&vgen3_reg>;  /* 2.8v, rev C board is VGEN3
282*4882a593Smuzhiyun						rev B board is VGEN5 */
283*4882a593Smuzhiyun		DVDD-supply = <&vgen2_reg>;  /* 1.5v*/
284*4882a593Smuzhiyun		powerdown-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
285*4882a593Smuzhiyun		reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
286*4882a593Smuzhiyun		status = "disabled";
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun		port {
289*4882a593Smuzhiyun			ov5642_to_ipu1_csi0_mux: endpoint {
290*4882a593Smuzhiyun				remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
291*4882a593Smuzhiyun				bus-width = <8>;
292*4882a593Smuzhiyun				hsync-active = <1>;
293*4882a593Smuzhiyun				vsync-active = <1>;
294*4882a593Smuzhiyun			};
295*4882a593Smuzhiyun		};
296*4882a593Smuzhiyun	};
297*4882a593Smuzhiyun};
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun&i2c2 {
300*4882a593Smuzhiyun	clock-frequency = <100000>;
301*4882a593Smuzhiyun	pinctrl-names = "default";
302*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c2>;
303*4882a593Smuzhiyun	status = "okay";
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun	touchscreen@4 {
306*4882a593Smuzhiyun		compatible = "eeti,egalax_ts";
307*4882a593Smuzhiyun		reg = <0x04>;
308*4882a593Smuzhiyun		pinctrl-names = "default";
309*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_i2c2_egalax_int>;
310*4882a593Smuzhiyun		interrupt-parent = <&gpio6>;
311*4882a593Smuzhiyun		interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
312*4882a593Smuzhiyun		wakeup-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>;
313*4882a593Smuzhiyun	};
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun	ov5640: camera@3c {
316*4882a593Smuzhiyun		compatible = "ovti,ov5640";
317*4882a593Smuzhiyun		pinctrl-names = "default";
318*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_ov5640>;
319*4882a593Smuzhiyun		reg = <0x3c>;
320*4882a593Smuzhiyun		clocks = <&clks IMX6QDL_CLK_CKO>;
321*4882a593Smuzhiyun		clock-names = "xclk";
322*4882a593Smuzhiyun		DOVDD-supply = <&vgen4_reg>; /* 1.8v */
323*4882a593Smuzhiyun		AVDD-supply = <&vgen3_reg>;  /* 2.8v, rev C board is VGEN3
324*4882a593Smuzhiyun						rev B board is VGEN5 */
325*4882a593Smuzhiyun		DVDD-supply = <&vgen2_reg>;  /* 1.5v*/
326*4882a593Smuzhiyun		powerdown-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
327*4882a593Smuzhiyun		reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun		port {
330*4882a593Smuzhiyun			ov5640_to_mipi_csi2: endpoint {
331*4882a593Smuzhiyun				remote-endpoint = <&mipi_csi2_in>;
332*4882a593Smuzhiyun				clock-lanes = <0>;
333*4882a593Smuzhiyun				data-lanes = <1 2>;
334*4882a593Smuzhiyun			};
335*4882a593Smuzhiyun		};
336*4882a593Smuzhiyun	};
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun	pmic: pfuze100@8 {
339*4882a593Smuzhiyun		compatible = "fsl,pfuze100";
340*4882a593Smuzhiyun		reg = <0x08>;
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun		regulators {
343*4882a593Smuzhiyun			sw1a_reg: sw1ab {
344*4882a593Smuzhiyun				regulator-min-microvolt = <300000>;
345*4882a593Smuzhiyun				regulator-max-microvolt = <1875000>;
346*4882a593Smuzhiyun				regulator-boot-on;
347*4882a593Smuzhiyun				regulator-always-on;
348*4882a593Smuzhiyun				regulator-ramp-delay = <6250>;
349*4882a593Smuzhiyun			};
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun			sw1c_reg: sw1c {
352*4882a593Smuzhiyun				regulator-min-microvolt = <300000>;
353*4882a593Smuzhiyun				regulator-max-microvolt = <1875000>;
354*4882a593Smuzhiyun				regulator-boot-on;
355*4882a593Smuzhiyun				regulator-always-on;
356*4882a593Smuzhiyun				regulator-ramp-delay = <6250>;
357*4882a593Smuzhiyun			};
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun			sw2_reg: sw2 {
360*4882a593Smuzhiyun				regulator-min-microvolt = <800000>;
361*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
362*4882a593Smuzhiyun				regulator-boot-on;
363*4882a593Smuzhiyun				regulator-always-on;
364*4882a593Smuzhiyun				regulator-ramp-delay = <6250>;
365*4882a593Smuzhiyun			};
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun			sw3a_reg: sw3a {
368*4882a593Smuzhiyun				regulator-min-microvolt = <400000>;
369*4882a593Smuzhiyun				regulator-max-microvolt = <1975000>;
370*4882a593Smuzhiyun				regulator-boot-on;
371*4882a593Smuzhiyun				regulator-always-on;
372*4882a593Smuzhiyun			};
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun			sw3b_reg: sw3b {
375*4882a593Smuzhiyun				regulator-min-microvolt = <400000>;
376*4882a593Smuzhiyun				regulator-max-microvolt = <1975000>;
377*4882a593Smuzhiyun				regulator-boot-on;
378*4882a593Smuzhiyun				regulator-always-on;
379*4882a593Smuzhiyun			};
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun			sw4_reg: sw4 {
382*4882a593Smuzhiyun				regulator-min-microvolt = <800000>;
383*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
384*4882a593Smuzhiyun				regulator-always-on;
385*4882a593Smuzhiyun			};
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun			swbst_reg: swbst {
388*4882a593Smuzhiyun				regulator-min-microvolt = <5000000>;
389*4882a593Smuzhiyun				regulator-max-microvolt = <5150000>;
390*4882a593Smuzhiyun			};
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun			snvs_reg: vsnvs {
393*4882a593Smuzhiyun				regulator-min-microvolt = <1000000>;
394*4882a593Smuzhiyun				regulator-max-microvolt = <3000000>;
395*4882a593Smuzhiyun				regulator-boot-on;
396*4882a593Smuzhiyun				regulator-always-on;
397*4882a593Smuzhiyun			};
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun			vref_reg: vrefddr {
400*4882a593Smuzhiyun				regulator-boot-on;
401*4882a593Smuzhiyun				regulator-always-on;
402*4882a593Smuzhiyun			};
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun			vgen1_reg: vgen1 {
405*4882a593Smuzhiyun				regulator-min-microvolt = <800000>;
406*4882a593Smuzhiyun				regulator-max-microvolt = <1550000>;
407*4882a593Smuzhiyun			};
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun			vgen2_reg: vgen2 {
410*4882a593Smuzhiyun				regulator-min-microvolt = <800000>;
411*4882a593Smuzhiyun				regulator-max-microvolt = <1550000>;
412*4882a593Smuzhiyun			};
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun			vgen3_reg: vgen3 {
415*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
416*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
417*4882a593Smuzhiyun			};
418*4882a593Smuzhiyun
419*4882a593Smuzhiyun			vgen4_reg: vgen4 {
420*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
421*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
422*4882a593Smuzhiyun				regulator-always-on;
423*4882a593Smuzhiyun			};
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun			vgen5_reg: vgen5 {
426*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
427*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
428*4882a593Smuzhiyun				regulator-always-on;
429*4882a593Smuzhiyun			};
430*4882a593Smuzhiyun
431*4882a593Smuzhiyun			vgen6_reg: vgen6 {
432*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
433*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
434*4882a593Smuzhiyun				regulator-always-on;
435*4882a593Smuzhiyun			};
436*4882a593Smuzhiyun		};
437*4882a593Smuzhiyun	};
438*4882a593Smuzhiyun};
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun&i2c3 {
441*4882a593Smuzhiyun	clock-frequency = <100000>;
442*4882a593Smuzhiyun	pinctrl-names = "default";
443*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c3>;
444*4882a593Smuzhiyun	status = "okay";
445*4882a593Smuzhiyun
446*4882a593Smuzhiyun	egalax_ts@4 {
447*4882a593Smuzhiyun		compatible = "eeti,egalax_ts";
448*4882a593Smuzhiyun		reg = <0x04>;
449*4882a593Smuzhiyun		interrupt-parent = <&gpio6>;
450*4882a593Smuzhiyun		interrupts = <7 2>;
451*4882a593Smuzhiyun		wakeup-gpios = <&gpio6 7 0>;
452*4882a593Smuzhiyun	};
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun	magnetometer@e {
455*4882a593Smuzhiyun		compatible = "fsl,mag3110";
456*4882a593Smuzhiyun		reg = <0x0e>;
457*4882a593Smuzhiyun		pinctrl-names = "default";
458*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_i2c3_mag3110_int>;
459*4882a593Smuzhiyun		interrupt-parent = <&gpio3>;
460*4882a593Smuzhiyun		interrupts = <16 IRQ_TYPE_EDGE_RISING>;
461*4882a593Smuzhiyun		vdd-supply = <&reg_sensors>;
462*4882a593Smuzhiyun		vddio-supply = <&reg_sensors>;
463*4882a593Smuzhiyun	};
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun	light-sensor@44 {
466*4882a593Smuzhiyun		compatible = "isil,isl29023";
467*4882a593Smuzhiyun		reg = <0x44>;
468*4882a593Smuzhiyun		pinctrl-names = "default";
469*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_i2c3_isl29023_int>;
470*4882a593Smuzhiyun		interrupt-parent = <&gpio3>;
471*4882a593Smuzhiyun		interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
472*4882a593Smuzhiyun		vcc-supply = <&reg_sensors>;
473*4882a593Smuzhiyun	};
474*4882a593Smuzhiyun};
475*4882a593Smuzhiyun
476*4882a593Smuzhiyun&iomuxc {
477*4882a593Smuzhiyun	pinctrl-names = "default";
478*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_hog>;
479*4882a593Smuzhiyun
480*4882a593Smuzhiyun	imx6qdl-sabresd {
481*4882a593Smuzhiyun		pinctrl_hog: hoggrp {
482*4882a593Smuzhiyun			fsl,pins = <
483*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
484*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
485*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
486*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
487*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x130b0
488*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
489*4882a593Smuzhiyun				MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
490*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x1b0b0
491*4882a593Smuzhiyun				MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
492*4882a593Smuzhiyun			>;
493*4882a593Smuzhiyun		};
494*4882a593Smuzhiyun
495*4882a593Smuzhiyun		pinctrl_audmux: audmuxgrp {
496*4882a593Smuzhiyun			fsl,pins = <
497*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT7__AUD3_RXD		0x130b0
498*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT4__AUD3_TXC		0x130b0
499*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT5__AUD3_TXD		0x110b0
500*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS		0x130b0
501*4882a593Smuzhiyun			>;
502*4882a593Smuzhiyun		};
503*4882a593Smuzhiyun
504*4882a593Smuzhiyun		pinctrl_ecspi1: ecspi1grp {
505*4882a593Smuzhiyun			fsl,pins = <
506*4882a593Smuzhiyun				MX6QDL_PAD_KEY_COL1__ECSPI1_MISO	0x100b1
507*4882a593Smuzhiyun				MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI	0x100b1
508*4882a593Smuzhiyun				MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK	0x100b1
509*4882a593Smuzhiyun				MX6QDL_PAD_KEY_ROW1__GPIO4_IO09		0x1b0b0
510*4882a593Smuzhiyun			>;
511*4882a593Smuzhiyun		};
512*4882a593Smuzhiyun
513*4882a593Smuzhiyun		pinctrl_enet: enetgrp {
514*4882a593Smuzhiyun			fsl,pins = <
515*4882a593Smuzhiyun				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
516*4882a593Smuzhiyun				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
517*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
518*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
519*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
520*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
521*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
522*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
523*4882a593Smuzhiyun				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
524*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
525*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
526*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
527*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
528*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
529*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
530*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
531*4882a593Smuzhiyun			>;
532*4882a593Smuzhiyun		};
533*4882a593Smuzhiyun
534*4882a593Smuzhiyun		pinctrl_gpio_keys: gpio_keysgrp {
535*4882a593Smuzhiyun			fsl,pins = <
536*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
537*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_4__GPIO1_IO04  0x1b0b0
538*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_5__GPIO1_IO05  0x1b0b0
539*4882a593Smuzhiyun			>;
540*4882a593Smuzhiyun		};
541*4882a593Smuzhiyun
542*4882a593Smuzhiyun		pinctrl_hdmi_cec: hdmicecgrp {
543*4882a593Smuzhiyun			fsl,pins = <
544*4882a593Smuzhiyun				MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE	0x1f8b0
545*4882a593Smuzhiyun			>;
546*4882a593Smuzhiyun		};
547*4882a593Smuzhiyun
548*4882a593Smuzhiyun		pinctrl_i2c1: i2c1grp {
549*4882a593Smuzhiyun			fsl,pins = <
550*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT8__I2C1_SDA		0x4001b8b1
551*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT9__I2C1_SCL		0x4001b8b1
552*4882a593Smuzhiyun			>;
553*4882a593Smuzhiyun		};
554*4882a593Smuzhiyun
555*4882a593Smuzhiyun		pinctrl_i2c1_mma8451_int: i2c1mma8451intgrp {
556*4882a593Smuzhiyun			fsl,pins = <
557*4882a593Smuzhiyun				MX6QDL_PAD_SD1_CMD__GPIO1_IO18		0xb0b1
558*4882a593Smuzhiyun			>;
559*4882a593Smuzhiyun		};
560*4882a593Smuzhiyun
561*4882a593Smuzhiyun		pinctrl_i2c2: i2c2grp {
562*4882a593Smuzhiyun			fsl,pins = <
563*4882a593Smuzhiyun				MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
564*4882a593Smuzhiyun				MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
565*4882a593Smuzhiyun			>;
566*4882a593Smuzhiyun		};
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun		pinctrl_i2c2_egalax_int: i2c2egalaxintgrp {
569*4882a593Smuzhiyun			fsl,pins = <
570*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_ALE__GPIO6_IO08	0x1b0b0
571*4882a593Smuzhiyun			>;
572*4882a593Smuzhiyun		};
573*4882a593Smuzhiyun
574*4882a593Smuzhiyun		pinctrl_i2c3: i2c3grp {
575*4882a593Smuzhiyun			fsl,pins = <
576*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_3__I2C3_SCL		0x4001b8b1
577*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001b8b1
578*4882a593Smuzhiyun			>;
579*4882a593Smuzhiyun		};
580*4882a593Smuzhiyun
581*4882a593Smuzhiyun		pinctrl_i2c3_isl29023_int: i2c3isl29023intgrp {
582*4882a593Smuzhiyun			fsl,pins = <
583*4882a593Smuzhiyun				MX6QDL_PAD_EIM_DA9__GPIO3_IO09		0xb0b1
584*4882a593Smuzhiyun			>;
585*4882a593Smuzhiyun		};
586*4882a593Smuzhiyun
587*4882a593Smuzhiyun		pinctrl_i2c3_mag3110_int: i2c3mag3110intgrp {
588*4882a593Smuzhiyun			fsl,pins = <
589*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D16__GPIO3_IO16		0xb0b1
590*4882a593Smuzhiyun			>;
591*4882a593Smuzhiyun		};
592*4882a593Smuzhiyun
593*4882a593Smuzhiyun		pinctrl_ipu1_csi0: ipu1csi0grp {
594*4882a593Smuzhiyun			fsl,pins = <
595*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12    0x1b0b0
596*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13    0x1b0b0
597*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14    0x1b0b0
598*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15    0x1b0b0
599*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16    0x1b0b0
600*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17    0x1b0b0
601*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18    0x1b0b0
602*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19    0x1b0b0
603*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK   0x1b0b0
604*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC      0x1b0b0
605*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC     0x1b0b0
606*4882a593Smuzhiyun			>;
607*4882a593Smuzhiyun		};
608*4882a593Smuzhiyun
609*4882a593Smuzhiyun		pinctrl_ov5640: ov5640grp {
610*4882a593Smuzhiyun			fsl,pins = <
611*4882a593Smuzhiyun				MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0
612*4882a593Smuzhiyun				MX6QDL_PAD_SD1_CLK__GPIO1_IO20  0x1b0b0
613*4882a593Smuzhiyun			>;
614*4882a593Smuzhiyun		};
615*4882a593Smuzhiyun
616*4882a593Smuzhiyun		pinctrl_ov5642: ov5642grp {
617*4882a593Smuzhiyun			fsl,pins = <
618*4882a593Smuzhiyun				MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
619*4882a593Smuzhiyun				MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0
620*4882a593Smuzhiyun			>;
621*4882a593Smuzhiyun		};
622*4882a593Smuzhiyun
623*4882a593Smuzhiyun		pinctrl_pcie: pciegrp {
624*4882a593Smuzhiyun			fsl,pins = <
625*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_17__GPIO7_IO12	0x1b0b0
626*4882a593Smuzhiyun			>;
627*4882a593Smuzhiyun		};
628*4882a593Smuzhiyun
629*4882a593Smuzhiyun		pinctrl_pcie_reg: pciereggrp {
630*4882a593Smuzhiyun			fsl,pins = <
631*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D19__GPIO3_IO19	0x1b0b0
632*4882a593Smuzhiyun			>;
633*4882a593Smuzhiyun		};
634*4882a593Smuzhiyun
635*4882a593Smuzhiyun		pinctrl_pwm1: pwm1grp {
636*4882a593Smuzhiyun			fsl,pins = <
637*4882a593Smuzhiyun				MX6QDL_PAD_SD1_DAT3__PWM1_OUT		0x1b0b1
638*4882a593Smuzhiyun			>;
639*4882a593Smuzhiyun		};
640*4882a593Smuzhiyun
641*4882a593Smuzhiyun		pinctrl_sensors_reg: sensorsreggrp {
642*4882a593Smuzhiyun			fsl,pins = <
643*4882a593Smuzhiyun				MX6QDL_PAD_EIM_EB3__GPIO2_IO31		0x1b0b0
644*4882a593Smuzhiyun			>;
645*4882a593Smuzhiyun		};
646*4882a593Smuzhiyun
647*4882a593Smuzhiyun		pinctrl_uart1: uart1grp {
648*4882a593Smuzhiyun			fsl,pins = <
649*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA	0x1b0b1
650*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA	0x1b0b1
651*4882a593Smuzhiyun			>;
652*4882a593Smuzhiyun		};
653*4882a593Smuzhiyun
654*4882a593Smuzhiyun		pinctrl_usbotg: usbotggrp {
655*4882a593Smuzhiyun			fsl,pins = <
656*4882a593Smuzhiyun				MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID	0x17059
657*4882a593Smuzhiyun			>;
658*4882a593Smuzhiyun		};
659*4882a593Smuzhiyun
660*4882a593Smuzhiyun		pinctrl_usdhc2: usdhc2grp {
661*4882a593Smuzhiyun			fsl,pins = <
662*4882a593Smuzhiyun				MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
663*4882a593Smuzhiyun				MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10059
664*4882a593Smuzhiyun				MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
665*4882a593Smuzhiyun				MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
666*4882a593Smuzhiyun				MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
667*4882a593Smuzhiyun				MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
668*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_D4__SD2_DATA4		0x17059
669*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_D5__SD2_DATA5		0x17059
670*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_D6__SD2_DATA6		0x17059
671*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_D7__SD2_DATA7		0x17059
672*4882a593Smuzhiyun			>;
673*4882a593Smuzhiyun		};
674*4882a593Smuzhiyun
675*4882a593Smuzhiyun		pinctrl_usdhc3: usdhc3grp {
676*4882a593Smuzhiyun			fsl,pins = <
677*4882a593Smuzhiyun				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
678*4882a593Smuzhiyun				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
679*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
680*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
681*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
682*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
683*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x17059
684*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x17059
685*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x17059
686*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x17059
687*4882a593Smuzhiyun			>;
688*4882a593Smuzhiyun		};
689*4882a593Smuzhiyun
690*4882a593Smuzhiyun		pinctrl_usdhc4: usdhc4grp {
691*4882a593Smuzhiyun			fsl,pins = <
692*4882a593Smuzhiyun				MX6QDL_PAD_SD4_CMD__SD4_CMD		0x17059
693*4882a593Smuzhiyun				MX6QDL_PAD_SD4_CLK__SD4_CLK		0x10059
694*4882a593Smuzhiyun				MX6QDL_PAD_SD4_DAT0__SD4_DATA0		0x17059
695*4882a593Smuzhiyun				MX6QDL_PAD_SD4_DAT1__SD4_DATA1		0x17059
696*4882a593Smuzhiyun				MX6QDL_PAD_SD4_DAT2__SD4_DATA2		0x17059
697*4882a593Smuzhiyun				MX6QDL_PAD_SD4_DAT3__SD4_DATA3		0x17059
698*4882a593Smuzhiyun				MX6QDL_PAD_SD4_DAT4__SD4_DATA4		0x17059
699*4882a593Smuzhiyun				MX6QDL_PAD_SD4_DAT5__SD4_DATA5		0x17059
700*4882a593Smuzhiyun				MX6QDL_PAD_SD4_DAT6__SD4_DATA6		0x17059
701*4882a593Smuzhiyun				MX6QDL_PAD_SD4_DAT7__SD4_DATA7		0x17059
702*4882a593Smuzhiyun			>;
703*4882a593Smuzhiyun		};
704*4882a593Smuzhiyun
705*4882a593Smuzhiyun		pinctrl_wdog: wdoggrp {
706*4882a593Smuzhiyun			fsl,pins = <
707*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_1__WDOG2_B		0x1b0b0
708*4882a593Smuzhiyun			>;
709*4882a593Smuzhiyun		};
710*4882a593Smuzhiyun	};
711*4882a593Smuzhiyun
712*4882a593Smuzhiyun	gpio_leds {
713*4882a593Smuzhiyun		pinctrl_gpio_leds: gpioledsgrp {
714*4882a593Smuzhiyun			fsl,pins = <
715*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
716*4882a593Smuzhiyun			>;
717*4882a593Smuzhiyun		};
718*4882a593Smuzhiyun	};
719*4882a593Smuzhiyun};
720*4882a593Smuzhiyun
721*4882a593Smuzhiyun&ldb {
722*4882a593Smuzhiyun	status = "okay";
723*4882a593Smuzhiyun
724*4882a593Smuzhiyun	lvds-channel@1 {
725*4882a593Smuzhiyun		fsl,data-mapping = "spwg";
726*4882a593Smuzhiyun		fsl,data-width = <18>;
727*4882a593Smuzhiyun		status = "okay";
728*4882a593Smuzhiyun
729*4882a593Smuzhiyun		port@4 {
730*4882a593Smuzhiyun			reg = <4>;
731*4882a593Smuzhiyun
732*4882a593Smuzhiyun			lvds0_out: endpoint {
733*4882a593Smuzhiyun				remote-endpoint = <&panel_in>;
734*4882a593Smuzhiyun			};
735*4882a593Smuzhiyun		};
736*4882a593Smuzhiyun	};
737*4882a593Smuzhiyun};
738*4882a593Smuzhiyun
739*4882a593Smuzhiyun&pcie {
740*4882a593Smuzhiyun	pinctrl-names = "default";
741*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pcie>;
742*4882a593Smuzhiyun	reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
743*4882a593Smuzhiyun	vpcie-supply = <&reg_pcie>;
744*4882a593Smuzhiyun	status = "okay";
745*4882a593Smuzhiyun};
746*4882a593Smuzhiyun
747*4882a593Smuzhiyun&pwm1 {
748*4882a593Smuzhiyun	#pwm-cells = <2>;
749*4882a593Smuzhiyun	pinctrl-names = "default";
750*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pwm1>;
751*4882a593Smuzhiyun	status = "okay";
752*4882a593Smuzhiyun};
753*4882a593Smuzhiyun
754*4882a593Smuzhiyun&reg_arm {
755*4882a593Smuzhiyun       vin-supply = <&sw1a_reg>;
756*4882a593Smuzhiyun};
757*4882a593Smuzhiyun
758*4882a593Smuzhiyun&reg_pu {
759*4882a593Smuzhiyun       vin-supply = <&sw1c_reg>;
760*4882a593Smuzhiyun};
761*4882a593Smuzhiyun
762*4882a593Smuzhiyun&reg_soc {
763*4882a593Smuzhiyun       vin-supply = <&sw1c_reg>;
764*4882a593Smuzhiyun};
765*4882a593Smuzhiyun
766*4882a593Smuzhiyun&reg_vdd1p1 {
767*4882a593Smuzhiyun	vin-supply = <&vgen5_reg>;
768*4882a593Smuzhiyun};
769*4882a593Smuzhiyun
770*4882a593Smuzhiyun&reg_vdd2p5 {
771*4882a593Smuzhiyun	vin-supply = <&vgen5_reg>;
772*4882a593Smuzhiyun};
773*4882a593Smuzhiyun
774*4882a593Smuzhiyun&snvs_poweroff {
775*4882a593Smuzhiyun	status = "okay";
776*4882a593Smuzhiyun};
777*4882a593Smuzhiyun
778*4882a593Smuzhiyun&snvs_pwrkey {
779*4882a593Smuzhiyun	status = "okay";
780*4882a593Smuzhiyun};
781*4882a593Smuzhiyun
782*4882a593Smuzhiyun&ssi2 {
783*4882a593Smuzhiyun	status = "okay";
784*4882a593Smuzhiyun};
785*4882a593Smuzhiyun
786*4882a593Smuzhiyun&uart1 {
787*4882a593Smuzhiyun	pinctrl-names = "default";
788*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart1>;
789*4882a593Smuzhiyun	status = "okay";
790*4882a593Smuzhiyun};
791*4882a593Smuzhiyun
792*4882a593Smuzhiyun&usbh1 {
793*4882a593Smuzhiyun	vbus-supply = <&reg_usb_h1_vbus>;
794*4882a593Smuzhiyun	status = "okay";
795*4882a593Smuzhiyun};
796*4882a593Smuzhiyun
797*4882a593Smuzhiyun&usbotg {
798*4882a593Smuzhiyun	vbus-supply = <&reg_usb_otg_vbus>;
799*4882a593Smuzhiyun	pinctrl-names = "default";
800*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usbotg>;
801*4882a593Smuzhiyun	disable-over-current;
802*4882a593Smuzhiyun	status = "okay";
803*4882a593Smuzhiyun};
804*4882a593Smuzhiyun
805*4882a593Smuzhiyun&usdhc2 {
806*4882a593Smuzhiyun	pinctrl-names = "default";
807*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc2>;
808*4882a593Smuzhiyun	bus-width = <8>;
809*4882a593Smuzhiyun	cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
810*4882a593Smuzhiyun	wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
811*4882a593Smuzhiyun	status = "okay";
812*4882a593Smuzhiyun};
813*4882a593Smuzhiyun
814*4882a593Smuzhiyun&usdhc3 {
815*4882a593Smuzhiyun	pinctrl-names = "default";
816*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc3>;
817*4882a593Smuzhiyun	bus-width = <8>;
818*4882a593Smuzhiyun	cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
819*4882a593Smuzhiyun	wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
820*4882a593Smuzhiyun	status = "okay";
821*4882a593Smuzhiyun};
822*4882a593Smuzhiyun
823*4882a593Smuzhiyun&usdhc4 {
824*4882a593Smuzhiyun	pinctrl-names = "default";
825*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc4>;
826*4882a593Smuzhiyun	bus-width = <8>;
827*4882a593Smuzhiyun	non-removable;
828*4882a593Smuzhiyun	no-1-8-v;
829*4882a593Smuzhiyun	status = "okay";
830*4882a593Smuzhiyun};
831*4882a593Smuzhiyun
832*4882a593Smuzhiyun&wdog1 {
833*4882a593Smuzhiyun	status = "disabled";
834*4882a593Smuzhiyun};
835*4882a593Smuzhiyun
836*4882a593Smuzhiyun&wdog2 {
837*4882a593Smuzhiyun	pinctrl-names = "default";
838*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_wdog>;
839*4882a593Smuzhiyun	fsl,ext-reset-output;
840*4882a593Smuzhiyun	status = "okay";
841*4882a593Smuzhiyun};
842