xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * Copyright 2011 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun * Copyright 2011 Linaro Ltd.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * This file is dual-licensed: you can use it either under the terms
6*4882a593Smuzhiyun * of the GPL or the X11 license, at your option. Note that this dual
7*4882a593Smuzhiyun * licensing only applies to this file, and not this project as a
8*4882a593Smuzhiyun * whole.
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun *  a) This file is free software; you can redistribute it and/or
11*4882a593Smuzhiyun *     modify it under the terms of the GNU General Public License
12*4882a593Smuzhiyun *     version 2 as published by the Free Software Foundation.
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun *     This file is distributed in the hope that it will be useful,
15*4882a593Smuzhiyun *     but WITHOUT ANY WARRANTY; without even the implied warranty of
16*4882a593Smuzhiyun *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17*4882a593Smuzhiyun *     GNU General Public License for more details.
18*4882a593Smuzhiyun *
19*4882a593Smuzhiyun * Or, alternatively,
20*4882a593Smuzhiyun *
21*4882a593Smuzhiyun *  b) Permission is hereby granted, free of charge, to any person
22*4882a593Smuzhiyun *     obtaining a copy of this software and associated documentation
23*4882a593Smuzhiyun *     files (the "Software"), to deal in the Software without
24*4882a593Smuzhiyun *     restriction, including without limitation the rights to use,
25*4882a593Smuzhiyun *     copy, modify, merge, publish, distribute, sublicense, and/or
26*4882a593Smuzhiyun *     sell copies of the Software, and to permit persons to whom the
27*4882a593Smuzhiyun *     Software is furnished to do so, subject to the following
28*4882a593Smuzhiyun *     conditions:
29*4882a593Smuzhiyun *
30*4882a593Smuzhiyun *     The above copyright notice and this permission notice shall be
31*4882a593Smuzhiyun *     included in all copies or substantial portions of the Software.
32*4882a593Smuzhiyun *
33*4882a593Smuzhiyun *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34*4882a593Smuzhiyun *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35*4882a593Smuzhiyun *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36*4882a593Smuzhiyun *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37*4882a593Smuzhiyun *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38*4882a593Smuzhiyun *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39*4882a593Smuzhiyun *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40*4882a593Smuzhiyun *     OTHER DEALINGS IN THE SOFTWARE.
41*4882a593Smuzhiyun */
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun#include <dt-bindings/clock/imx6qdl-clock.h>
44*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
45*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun/ {
48*4882a593Smuzhiyun	chosen {
49*4882a593Smuzhiyun		stdout-path = &uart2;
50*4882a593Smuzhiyun	};
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun	memory@10000000 {
53*4882a593Smuzhiyun		device_type = "memory";
54*4882a593Smuzhiyun		reg = <0x10000000 0x40000000>;
55*4882a593Smuzhiyun	};
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun	regulators {
58*4882a593Smuzhiyun		compatible = "simple-bus";
59*4882a593Smuzhiyun		#address-cells = <1>;
60*4882a593Smuzhiyun		#size-cells = <0>;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun		reg_2p5v: regulator@0 {
63*4882a593Smuzhiyun			compatible = "regulator-fixed";
64*4882a593Smuzhiyun			reg = <0>;
65*4882a593Smuzhiyun			regulator-name = "2P5V";
66*4882a593Smuzhiyun			regulator-min-microvolt = <2500000>;
67*4882a593Smuzhiyun			regulator-max-microvolt = <2500000>;
68*4882a593Smuzhiyun			regulator-always-on;
69*4882a593Smuzhiyun		};
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun		reg_3p3v: regulator@1 {
72*4882a593Smuzhiyun			compatible = "regulator-fixed";
73*4882a593Smuzhiyun			reg = <1>;
74*4882a593Smuzhiyun			regulator-name = "3P3V";
75*4882a593Smuzhiyun			regulator-min-microvolt = <3300000>;
76*4882a593Smuzhiyun			regulator-max-microvolt = <3300000>;
77*4882a593Smuzhiyun			regulator-always-on;
78*4882a593Smuzhiyun		};
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun		reg_usb_otg_vbus: regulator@2 {
81*4882a593Smuzhiyun			compatible = "regulator-fixed";
82*4882a593Smuzhiyun			reg = <2>;
83*4882a593Smuzhiyun			regulator-name = "usb_otg_vbus";
84*4882a593Smuzhiyun			regulator-min-microvolt = <5000000>;
85*4882a593Smuzhiyun			regulator-max-microvolt = <5000000>;
86*4882a593Smuzhiyun			gpio = <&gpio3 22 0>;
87*4882a593Smuzhiyun			enable-active-high;
88*4882a593Smuzhiyun		};
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun		reg_can_xcvr: regulator@3 {
91*4882a593Smuzhiyun			compatible = "regulator-fixed";
92*4882a593Smuzhiyun			reg = <3>;
93*4882a593Smuzhiyun			regulator-name = "CAN XCVR";
94*4882a593Smuzhiyun			regulator-min-microvolt = <3300000>;
95*4882a593Smuzhiyun			regulator-max-microvolt = <3300000>;
96*4882a593Smuzhiyun			pinctrl-names = "default";
97*4882a593Smuzhiyun			pinctrl-0 = <&pinctrl_can_xcvr>;
98*4882a593Smuzhiyun			gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
99*4882a593Smuzhiyun		};
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun		reg_1p5v: regulator@4 {
102*4882a593Smuzhiyun			compatible = "regulator-fixed";
103*4882a593Smuzhiyun			reg = <4>;
104*4882a593Smuzhiyun			regulator-name = "1P5V";
105*4882a593Smuzhiyun			regulator-min-microvolt = <1500000>;
106*4882a593Smuzhiyun			regulator-max-microvolt = <1500000>;
107*4882a593Smuzhiyun			regulator-always-on;
108*4882a593Smuzhiyun		};
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun		reg_1p8v: regulator@5 {
111*4882a593Smuzhiyun			compatible = "regulator-fixed";
112*4882a593Smuzhiyun			reg = <5>;
113*4882a593Smuzhiyun			regulator-name = "1P8V";
114*4882a593Smuzhiyun			regulator-min-microvolt = <1800000>;
115*4882a593Smuzhiyun			regulator-max-microvolt = <1800000>;
116*4882a593Smuzhiyun			regulator-always-on;
117*4882a593Smuzhiyun		};
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun		reg_2p8v: regulator@6 {
120*4882a593Smuzhiyun			compatible = "regulator-fixed";
121*4882a593Smuzhiyun			reg = <6>;
122*4882a593Smuzhiyun			regulator-name = "2P8V";
123*4882a593Smuzhiyun			regulator-min-microvolt = <2800000>;
124*4882a593Smuzhiyun			regulator-max-microvolt = <2800000>;
125*4882a593Smuzhiyun			regulator-always-on;
126*4882a593Smuzhiyun		};
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun		reg_usb_h1_vbus: regulator@7 {
129*4882a593Smuzhiyun			compatible = "regulator-fixed";
130*4882a593Smuzhiyun			reg = <7>;
131*4882a593Smuzhiyun			pinctrl-names = "default";
132*4882a593Smuzhiyun			pinctrl-0 = <&pinctrl_usbh1>;
133*4882a593Smuzhiyun			regulator-name = "usb_h1_vbus";
134*4882a593Smuzhiyun			regulator-min-microvolt = <3300000>;
135*4882a593Smuzhiyun			regulator-max-microvolt = <3300000>;
136*4882a593Smuzhiyun			gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
137*4882a593Smuzhiyun			enable-active-high;
138*4882a593Smuzhiyun		};
139*4882a593Smuzhiyun	};
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun	mipi_xclk: mipi_xclk {
142*4882a593Smuzhiyun		compatible = "pwm-clock";
143*4882a593Smuzhiyun		#clock-cells = <0>;
144*4882a593Smuzhiyun		clock-frequency = <22000000>;
145*4882a593Smuzhiyun		clock-output-names = "mipi_pwm3";
146*4882a593Smuzhiyun		pwms = <&pwm3 0 45>; /* 1 / 45 ns = 22 MHz */
147*4882a593Smuzhiyun		status = "okay";
148*4882a593Smuzhiyun	};
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun	gpio-keys {
151*4882a593Smuzhiyun		compatible = "gpio-keys";
152*4882a593Smuzhiyun		pinctrl-names = "default";
153*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_gpio_keys>;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun		power {
156*4882a593Smuzhiyun			label = "Power Button";
157*4882a593Smuzhiyun			gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
158*4882a593Smuzhiyun			linux,code = <KEY_POWER>;
159*4882a593Smuzhiyun			wakeup-source;
160*4882a593Smuzhiyun		};
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun		menu {
163*4882a593Smuzhiyun			label = "Menu";
164*4882a593Smuzhiyun			gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
165*4882a593Smuzhiyun			linux,code = <KEY_MENU>;
166*4882a593Smuzhiyun		};
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun		home {
169*4882a593Smuzhiyun			label = "Home";
170*4882a593Smuzhiyun			gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
171*4882a593Smuzhiyun			linux,code = <KEY_HOME>;
172*4882a593Smuzhiyun		};
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun		back {
175*4882a593Smuzhiyun			label = "Back";
176*4882a593Smuzhiyun			gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
177*4882a593Smuzhiyun			linux,code = <KEY_BACK>;
178*4882a593Smuzhiyun		};
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun		volume-up {
181*4882a593Smuzhiyun			label = "Volume Up";
182*4882a593Smuzhiyun			gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
183*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEUP>;
184*4882a593Smuzhiyun		};
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun		volume-down {
187*4882a593Smuzhiyun			label = "Volume Down";
188*4882a593Smuzhiyun			gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
189*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEDOWN>;
190*4882a593Smuzhiyun		};
191*4882a593Smuzhiyun	};
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun	sound {
194*4882a593Smuzhiyun		compatible = "fsl,imx6q-sabrelite-sgtl5000",
195*4882a593Smuzhiyun			     "fsl,imx-audio-sgtl5000";
196*4882a593Smuzhiyun		model = "imx6q-sabrelite-sgtl5000";
197*4882a593Smuzhiyun		ssi-controller = <&ssi1>;
198*4882a593Smuzhiyun		audio-codec = <&codec>;
199*4882a593Smuzhiyun		audio-routing =
200*4882a593Smuzhiyun			"MIC_IN", "Mic Jack",
201*4882a593Smuzhiyun			"Mic Jack", "Mic Bias",
202*4882a593Smuzhiyun			"Headphone Jack", "HP_OUT";
203*4882a593Smuzhiyun		mux-int-port = <1>;
204*4882a593Smuzhiyun		mux-ext-port = <4>;
205*4882a593Smuzhiyun	};
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun	backlight_lcd: backlight-lcd {
208*4882a593Smuzhiyun		compatible = "pwm-backlight";
209*4882a593Smuzhiyun		pwms = <&pwm1 0 5000000>;
210*4882a593Smuzhiyun		brightness-levels = <0 4 8 16 32 64 128 255>;
211*4882a593Smuzhiyun		default-brightness-level = <7>;
212*4882a593Smuzhiyun		power-supply = <&reg_3p3v>;
213*4882a593Smuzhiyun		status = "okay";
214*4882a593Smuzhiyun	};
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun	backlight_lvds: backlight-lvds {
217*4882a593Smuzhiyun		compatible = "pwm-backlight";
218*4882a593Smuzhiyun		pwms = <&pwm4 0 5000000>;
219*4882a593Smuzhiyun		brightness-levels = <0 4 8 16 32 64 128 255>;
220*4882a593Smuzhiyun		default-brightness-level = <7>;
221*4882a593Smuzhiyun		power-supply = <&reg_3p3v>;
222*4882a593Smuzhiyun		status = "okay";
223*4882a593Smuzhiyun	};
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun	lcd_display: disp0 {
226*4882a593Smuzhiyun		compatible = "fsl,imx-parallel-display";
227*4882a593Smuzhiyun		#address-cells = <1>;
228*4882a593Smuzhiyun		#size-cells = <0>;
229*4882a593Smuzhiyun		interface-pix-fmt = "bgr666";
230*4882a593Smuzhiyun		pinctrl-names = "default";
231*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_j15>;
232*4882a593Smuzhiyun		status = "okay";
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun		port@0 {
235*4882a593Smuzhiyun			reg = <0>;
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun			lcd_display_in: endpoint {
238*4882a593Smuzhiyun				remote-endpoint = <&ipu1_di0_disp0>;
239*4882a593Smuzhiyun			};
240*4882a593Smuzhiyun		};
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun		port@1 {
243*4882a593Smuzhiyun			reg = <1>;
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun			lcd_display_out: endpoint {
246*4882a593Smuzhiyun				remote-endpoint = <&lcd_panel_in>;
247*4882a593Smuzhiyun			};
248*4882a593Smuzhiyun		};
249*4882a593Smuzhiyun	};
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun	panel-lcd {
252*4882a593Smuzhiyun		compatible = "okaya,rs800480t-7x0gp";
253*4882a593Smuzhiyun		backlight = <&backlight_lcd>;
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun		port {
256*4882a593Smuzhiyun			lcd_panel_in: endpoint {
257*4882a593Smuzhiyun				remote-endpoint = <&lcd_display_out>;
258*4882a593Smuzhiyun			};
259*4882a593Smuzhiyun		};
260*4882a593Smuzhiyun	};
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun	panel-lvds0 {
263*4882a593Smuzhiyun		compatible = "hannstar,hsd100pxn1";
264*4882a593Smuzhiyun		backlight = <&backlight_lvds>;
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun		port {
267*4882a593Smuzhiyun			panel_in: endpoint {
268*4882a593Smuzhiyun				remote-endpoint = <&lvds0_out>;
269*4882a593Smuzhiyun			};
270*4882a593Smuzhiyun		};
271*4882a593Smuzhiyun	};
272*4882a593Smuzhiyun};
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun&ipu1_csi0_from_ipu1_csi0_mux {
275*4882a593Smuzhiyun	bus-width = <8>;
276*4882a593Smuzhiyun	data-shift = <12>; /* Lines 19:12 used */
277*4882a593Smuzhiyun	hsync-active = <1>;
278*4882a593Smuzhiyun	vync-active = <1>;
279*4882a593Smuzhiyun};
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun&ipu1_csi0_mux_from_parallel_sensor {
282*4882a593Smuzhiyun	remote-endpoint = <&ov5642_to_ipu1_csi0_mux>;
283*4882a593Smuzhiyun};
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun&ipu1_csi0 {
286*4882a593Smuzhiyun	pinctrl-names = "default";
287*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_ipu1_csi0>;
288*4882a593Smuzhiyun};
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun&audmux {
291*4882a593Smuzhiyun	pinctrl-names = "default";
292*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_audmux>;
293*4882a593Smuzhiyun	status = "okay";
294*4882a593Smuzhiyun};
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun&can1 {
297*4882a593Smuzhiyun	pinctrl-names = "default";
298*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_can1>;
299*4882a593Smuzhiyun	xceiver-supply = <&reg_can_xcvr>;
300*4882a593Smuzhiyun	status = "okay";
301*4882a593Smuzhiyun};
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun&clks {
304*4882a593Smuzhiyun	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
305*4882a593Smuzhiyun			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
306*4882a593Smuzhiyun	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
307*4882a593Smuzhiyun				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
308*4882a593Smuzhiyun};
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun&ecspi1 {
311*4882a593Smuzhiyun	cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
312*4882a593Smuzhiyun	pinctrl-names = "default";
313*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_ecspi1>;
314*4882a593Smuzhiyun	status = "okay";
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun	flash: flash@0 {
317*4882a593Smuzhiyun		compatible = "sst,sst25vf016b", "jedec,spi-nor";
318*4882a593Smuzhiyun		spi-max-frequency = <20000000>;
319*4882a593Smuzhiyun		reg = <0>;
320*4882a593Smuzhiyun	};
321*4882a593Smuzhiyun};
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun&fec {
324*4882a593Smuzhiyun	pinctrl-names = "default";
325*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_enet>;
326*4882a593Smuzhiyun	phy-mode = "rgmii";
327*4882a593Smuzhiyun	phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
328*4882a593Smuzhiyun	txen-skew-ps = <0>;
329*4882a593Smuzhiyun	txc-skew-ps = <3000>;
330*4882a593Smuzhiyun	rxdv-skew-ps = <0>;
331*4882a593Smuzhiyun	rxc-skew-ps = <3000>;
332*4882a593Smuzhiyun	rxd0-skew-ps = <0>;
333*4882a593Smuzhiyun	rxd1-skew-ps = <0>;
334*4882a593Smuzhiyun	rxd2-skew-ps = <0>;
335*4882a593Smuzhiyun	rxd3-skew-ps = <0>;
336*4882a593Smuzhiyun	txd0-skew-ps = <0>;
337*4882a593Smuzhiyun	txd1-skew-ps = <0>;
338*4882a593Smuzhiyun	txd2-skew-ps = <0>;
339*4882a593Smuzhiyun	txd3-skew-ps = <0>;
340*4882a593Smuzhiyun	status = "okay";
341*4882a593Smuzhiyun};
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun&hdmi {
344*4882a593Smuzhiyun	ddc-i2c-bus = <&i2c2>;
345*4882a593Smuzhiyun	status = "okay";
346*4882a593Smuzhiyun};
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun&i2c1 {
349*4882a593Smuzhiyun	clock-frequency = <100000>;
350*4882a593Smuzhiyun	pinctrl-names = "default";
351*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c1>;
352*4882a593Smuzhiyun	status = "okay";
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun	codec: sgtl5000@a {
355*4882a593Smuzhiyun		compatible = "fsl,sgtl5000";
356*4882a593Smuzhiyun		reg = <0x0a>;
357*4882a593Smuzhiyun		clocks = <&clks IMX6QDL_CLK_CKO>;
358*4882a593Smuzhiyun		VDDA-supply = <&reg_2p5v>;
359*4882a593Smuzhiyun		VDDIO-supply = <&reg_3p3v>;
360*4882a593Smuzhiyun	};
361*4882a593Smuzhiyun};
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun&i2c2 {
364*4882a593Smuzhiyun	clock-frequency = <100000>;
365*4882a593Smuzhiyun	pinctrl-names = "default";
366*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c2>;
367*4882a593Smuzhiyun	status = "okay";
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun	ov5640: camera@40 {
370*4882a593Smuzhiyun		compatible = "ovti,ov5640";
371*4882a593Smuzhiyun		pinctrl-names = "default";
372*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_ov5640>;
373*4882a593Smuzhiyun		reg = <0x40>;
374*4882a593Smuzhiyun		clocks = <&mipi_xclk>;
375*4882a593Smuzhiyun		clock-names = "xclk";
376*4882a593Smuzhiyun		DOVDD-supply = <&reg_1p8v>;
377*4882a593Smuzhiyun		AVDD-supply = <&reg_2p8v>;
378*4882a593Smuzhiyun		DVDD-supply = <&reg_1p5v>;
379*4882a593Smuzhiyun		reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* NANDF_D5 */
380*4882a593Smuzhiyun		powerdown-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* NANDF_WP_B */
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun		port {
383*4882a593Smuzhiyun			ov5640_to_mipi_csi2: endpoint {
384*4882a593Smuzhiyun				remote-endpoint = <&mipi_csi2_in>;
385*4882a593Smuzhiyun				clock-lanes = <0>;
386*4882a593Smuzhiyun				data-lanes = <1 2>;
387*4882a593Smuzhiyun			};
388*4882a593Smuzhiyun		};
389*4882a593Smuzhiyun	};
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun	ov5642: camera@42 {
392*4882a593Smuzhiyun		compatible = "ovti,ov5642";
393*4882a593Smuzhiyun		pinctrl-names = "default";
394*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_ov5642>;
395*4882a593Smuzhiyun		clocks = <&clks IMX6QDL_CLK_CKO2>;
396*4882a593Smuzhiyun		clock-names = "xclk";
397*4882a593Smuzhiyun		reg = <0x42>;
398*4882a593Smuzhiyun		reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
399*4882a593Smuzhiyun		powerdown-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
400*4882a593Smuzhiyun		gp-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
401*4882a593Smuzhiyun		status = "disabled";
402*4882a593Smuzhiyun
403*4882a593Smuzhiyun		port {
404*4882a593Smuzhiyun			ov5642_to_ipu1_csi0_mux: endpoint {
405*4882a593Smuzhiyun				remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
406*4882a593Smuzhiyun				bus-width = <8>;
407*4882a593Smuzhiyun				hsync-active = <1>;
408*4882a593Smuzhiyun				vsync-active = <1>;
409*4882a593Smuzhiyun			};
410*4882a593Smuzhiyun		};
411*4882a593Smuzhiyun	};
412*4882a593Smuzhiyun};
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun&i2c3 {
415*4882a593Smuzhiyun	clock-frequency = <100000>;
416*4882a593Smuzhiyun	pinctrl-names = "default";
417*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c3>;
418*4882a593Smuzhiyun	status = "okay";
419*4882a593Smuzhiyun};
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun&iomuxc {
422*4882a593Smuzhiyun	pinctrl-names = "default";
423*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_hog>;
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun	imx6q-sabrelite {
426*4882a593Smuzhiyun		pinctrl_hog: hoggrp {
427*4882a593Smuzhiyun			fsl,pins = <
428*4882a593Smuzhiyun				/* SGTL5000 sys_mclk */
429*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x030b0
430*4882a593Smuzhiyun			>;
431*4882a593Smuzhiyun		};
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun		pinctrl_audmux: audmuxgrp {
434*4882a593Smuzhiyun			fsl,pins = <
435*4882a593Smuzhiyun				MX6QDL_PAD_SD2_DAT0__AUD4_RXD		0x130b0
436*4882a593Smuzhiyun				MX6QDL_PAD_SD2_DAT3__AUD4_TXC		0x130b0
437*4882a593Smuzhiyun				MX6QDL_PAD_SD2_DAT2__AUD4_TXD		0x110b0
438*4882a593Smuzhiyun				MX6QDL_PAD_SD2_DAT1__AUD4_TXFS		0x130b0
439*4882a593Smuzhiyun			>;
440*4882a593Smuzhiyun		};
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun		pinctrl_can1: can1grp {
443*4882a593Smuzhiyun			fsl,pins = <
444*4882a593Smuzhiyun				MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX	0x1b0b0
445*4882a593Smuzhiyun				MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX	0x1b0b0
446*4882a593Smuzhiyun			>;
447*4882a593Smuzhiyun		};
448*4882a593Smuzhiyun
449*4882a593Smuzhiyun		pinctrl_can_xcvr: can-xcvrgrp {
450*4882a593Smuzhiyun			fsl,pins = <
451*4882a593Smuzhiyun				/* Flexcan XCVR enable */
452*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_2__GPIO1_IO02		0x1b0b0
453*4882a593Smuzhiyun			>;
454*4882a593Smuzhiyun		};
455*4882a593Smuzhiyun
456*4882a593Smuzhiyun		pinctrl_ecspi1: ecspi1grp {
457*4882a593Smuzhiyun			fsl,pins = <
458*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D17__ECSPI1_MISO		0x100b1
459*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D18__ECSPI1_MOSI		0x100b1
460*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D16__ECSPI1_SCLK		0x100b1
461*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D19__GPIO3_IO19  0x000b1	/* CS */
462*4882a593Smuzhiyun			>;
463*4882a593Smuzhiyun		};
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun		pinctrl_enet: enetgrp {
466*4882a593Smuzhiyun			fsl,pins = <
467*4882a593Smuzhiyun				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x100b0
468*4882a593Smuzhiyun				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x100b0
469*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x10030
470*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x10030
471*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x10030
472*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x10030
473*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x10030
474*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x10030
475*4882a593Smuzhiyun				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x100b0
476*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
477*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
478*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
479*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
480*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
481*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
482*4882a593Smuzhiyun				/* Phy reset */
483*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D23__GPIO3_IO23		0x000b0
484*4882a593Smuzhiyun			>;
485*4882a593Smuzhiyun		};
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun		pinctrl_gpio_keys: gpio-keysgrp {
488*4882a593Smuzhiyun			fsl,pins = <
489*4882a593Smuzhiyun				/* Power Button */
490*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_D3__GPIO2_IO03		0x1b0b0
491*4882a593Smuzhiyun				/* Menu Button */
492*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_D1__GPIO2_IO01		0x1b0b0
493*4882a593Smuzhiyun				/* Home Button */
494*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_D4__GPIO2_IO04		0x1b0b0
495*4882a593Smuzhiyun				/* Back Button */
496*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_D2__GPIO2_IO02		0x1b0b0
497*4882a593Smuzhiyun				/* Volume Up Button */
498*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_18__GPIO7_IO13		0x1b0b0
499*4882a593Smuzhiyun				/* Volume Down Button */
500*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_19__GPIO4_IO05		0x1b0b0
501*4882a593Smuzhiyun			>;
502*4882a593Smuzhiyun		};
503*4882a593Smuzhiyun
504*4882a593Smuzhiyun		pinctrl_i2c1: i2c1grp {
505*4882a593Smuzhiyun			fsl,pins = <
506*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1
507*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1
508*4882a593Smuzhiyun			>;
509*4882a593Smuzhiyun		};
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun		pinctrl_i2c2: i2c2grp {
512*4882a593Smuzhiyun			fsl,pins = <
513*4882a593Smuzhiyun				MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
514*4882a593Smuzhiyun				MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
515*4882a593Smuzhiyun			>;
516*4882a593Smuzhiyun		};
517*4882a593Smuzhiyun
518*4882a593Smuzhiyun		pinctrl_i2c3: i2c3grp {
519*4882a593Smuzhiyun			fsl,pins = <
520*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_5__I2C3_SCL		0x4001b8b1
521*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_16__I2C3_SDA		0x4001b8b1
522*4882a593Smuzhiyun			>;
523*4882a593Smuzhiyun		};
524*4882a593Smuzhiyun
525*4882a593Smuzhiyun		pinctrl_ipu1_csi0: ipu1csi0grp {
526*4882a593Smuzhiyun			fsl,pins = <
527*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12    0x1b0b0
528*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13    0x1b0b0
529*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14    0x1b0b0
530*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15    0x1b0b0
531*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16    0x1b0b0
532*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17    0x1b0b0
533*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18    0x1b0b0
534*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19    0x1b0b0
535*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK   0x1b0b0
536*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC      0x1b0b0
537*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC     0x1b0b0
538*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x1b0b0
539*4882a593Smuzhiyun			>;
540*4882a593Smuzhiyun		};
541*4882a593Smuzhiyun
542*4882a593Smuzhiyun		pinctrl_j15: j15grp {
543*4882a593Smuzhiyun			fsl,pins = <
544*4882a593Smuzhiyun				MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
545*4882a593Smuzhiyun				MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
546*4882a593Smuzhiyun				MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
547*4882a593Smuzhiyun				MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
548*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
549*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
550*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
551*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
552*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
553*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
554*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
555*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
556*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
557*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
558*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
559*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
560*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
561*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
562*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
563*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
564*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
565*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
566*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
567*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
568*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
569*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
570*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
571*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
572*4882a593Smuzhiyun			>;
573*4882a593Smuzhiyun		};
574*4882a593Smuzhiyun
575*4882a593Smuzhiyun		pinctrl_ov5640: ov5640grp {
576*4882a593Smuzhiyun			fsl,pins = <
577*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_D5__GPIO2_IO05   0x000b0
578*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0
579*4882a593Smuzhiyun			>;
580*4882a593Smuzhiyun		};
581*4882a593Smuzhiyun
582*4882a593Smuzhiyun		pinctrl_ov5642: ov5642grp {
583*4882a593Smuzhiyun			fsl,pins = <
584*4882a593Smuzhiyun				MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
585*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_6__GPIO1_IO06   0x1b0b0
586*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_8__GPIO1_IO08   0x130b0
587*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_3__CCM_CLKO2    0x000b0
588*4882a593Smuzhiyun			>;
589*4882a593Smuzhiyun		};
590*4882a593Smuzhiyun
591*4882a593Smuzhiyun		pinctrl_pwm1: pwm1grp {
592*4882a593Smuzhiyun			fsl,pins = <
593*4882a593Smuzhiyun				MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
594*4882a593Smuzhiyun			>;
595*4882a593Smuzhiyun		};
596*4882a593Smuzhiyun
597*4882a593Smuzhiyun		pinctrl_pwm3: pwm3grp {
598*4882a593Smuzhiyun			fsl,pins = <
599*4882a593Smuzhiyun				MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
600*4882a593Smuzhiyun			>;
601*4882a593Smuzhiyun		};
602*4882a593Smuzhiyun
603*4882a593Smuzhiyun		pinctrl_pwm4: pwm4grp {
604*4882a593Smuzhiyun			fsl,pins = <
605*4882a593Smuzhiyun				MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
606*4882a593Smuzhiyun			>;
607*4882a593Smuzhiyun		};
608*4882a593Smuzhiyun
609*4882a593Smuzhiyun		pinctrl_uart1: uart1grp {
610*4882a593Smuzhiyun			fsl,pins = <
611*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA	0x1b0b1
612*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA	0x1b0b1
613*4882a593Smuzhiyun			>;
614*4882a593Smuzhiyun		};
615*4882a593Smuzhiyun
616*4882a593Smuzhiyun		pinctrl_uart2: uart2grp {
617*4882a593Smuzhiyun			fsl,pins = <
618*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D26__UART2_TX_DATA	0x1b0b1
619*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D27__UART2_RX_DATA	0x1b0b1
620*4882a593Smuzhiyun			>;
621*4882a593Smuzhiyun		};
622*4882a593Smuzhiyun
623*4882a593Smuzhiyun		pinctrl_usbh1: usbh1grp {
624*4882a593Smuzhiyun			fsl,pins = <
625*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_17__GPIO7_IO12		0x030b0
626*4882a593Smuzhiyun			>;
627*4882a593Smuzhiyun		};
628*4882a593Smuzhiyun
629*4882a593Smuzhiyun		pinctrl_usbotg: usbotggrp {
630*4882a593Smuzhiyun			fsl,pins = <
631*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x17059
632*4882a593Smuzhiyun				MX6QDL_PAD_KEY_COL4__USB_OTG_OC	0x1b0b0
633*4882a593Smuzhiyun				/* power enable, high active */
634*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x000b0
635*4882a593Smuzhiyun			>;
636*4882a593Smuzhiyun		};
637*4882a593Smuzhiyun
638*4882a593Smuzhiyun		pinctrl_usdhc3: usdhc3grp {
639*4882a593Smuzhiyun			fsl,pins = <
640*4882a593Smuzhiyun				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
641*4882a593Smuzhiyun				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
642*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
643*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
644*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
645*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
646*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0	/* CD */
647*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0	/* WP */
648*4882a593Smuzhiyun			>;
649*4882a593Smuzhiyun		};
650*4882a593Smuzhiyun
651*4882a593Smuzhiyun		pinctrl_usdhc4: usdhc4grp {
652*4882a593Smuzhiyun			fsl,pins = <
653*4882a593Smuzhiyun				MX6QDL_PAD_SD4_CMD__SD4_CMD		0x17059
654*4882a593Smuzhiyun				MX6QDL_PAD_SD4_CLK__SD4_CLK		0x10059
655*4882a593Smuzhiyun				MX6QDL_PAD_SD4_DAT0__SD4_DATA0		0x17059
656*4882a593Smuzhiyun				MX6QDL_PAD_SD4_DAT1__SD4_DATA1		0x17059
657*4882a593Smuzhiyun				MX6QDL_PAD_SD4_DAT2__SD4_DATA2		0x17059
658*4882a593Smuzhiyun				MX6QDL_PAD_SD4_DAT3__SD4_DATA3		0x17059
659*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0	/* CD */
660*4882a593Smuzhiyun			>;
661*4882a593Smuzhiyun		};
662*4882a593Smuzhiyun	};
663*4882a593Smuzhiyun};
664*4882a593Smuzhiyun
665*4882a593Smuzhiyun&ipu1_di0_disp0 {
666*4882a593Smuzhiyun	remote-endpoint = <&lcd_display_in>;
667*4882a593Smuzhiyun};
668*4882a593Smuzhiyun
669*4882a593Smuzhiyun&ldb {
670*4882a593Smuzhiyun	status = "okay";
671*4882a593Smuzhiyun
672*4882a593Smuzhiyun	lvds-channel@0 {
673*4882a593Smuzhiyun		status = "okay";
674*4882a593Smuzhiyun
675*4882a593Smuzhiyun		port@4 {
676*4882a593Smuzhiyun			reg = <4>;
677*4882a593Smuzhiyun
678*4882a593Smuzhiyun			lvds0_out: endpoint {
679*4882a593Smuzhiyun				remote-endpoint = <&panel_in>;
680*4882a593Smuzhiyun			};
681*4882a593Smuzhiyun		};
682*4882a593Smuzhiyun	};
683*4882a593Smuzhiyun};
684*4882a593Smuzhiyun
685*4882a593Smuzhiyun&pcie {
686*4882a593Smuzhiyun	status = "okay";
687*4882a593Smuzhiyun};
688*4882a593Smuzhiyun
689*4882a593Smuzhiyun&pwm1 {
690*4882a593Smuzhiyun	#pwm-cells = <2>;
691*4882a593Smuzhiyun	pinctrl-names = "default";
692*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pwm1>;
693*4882a593Smuzhiyun	status = "okay";
694*4882a593Smuzhiyun};
695*4882a593Smuzhiyun
696*4882a593Smuzhiyun&pwm3 {
697*4882a593Smuzhiyun	#pwm-cells = <2>;
698*4882a593Smuzhiyun	pinctrl-names = "default";
699*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pwm3>;
700*4882a593Smuzhiyun	status = "okay";
701*4882a593Smuzhiyun};
702*4882a593Smuzhiyun
703*4882a593Smuzhiyun&pwm4 {
704*4882a593Smuzhiyun	#pwm-cells = <2>;
705*4882a593Smuzhiyun	pinctrl-names = "default";
706*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pwm4>;
707*4882a593Smuzhiyun	status = "okay";
708*4882a593Smuzhiyun};
709*4882a593Smuzhiyun
710*4882a593Smuzhiyun&ssi1 {
711*4882a593Smuzhiyun	status = "okay";
712*4882a593Smuzhiyun};
713*4882a593Smuzhiyun
714*4882a593Smuzhiyun&uart1 {
715*4882a593Smuzhiyun	pinctrl-names = "default";
716*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart1>;
717*4882a593Smuzhiyun	status = "okay";
718*4882a593Smuzhiyun};
719*4882a593Smuzhiyun
720*4882a593Smuzhiyun&uart2 {
721*4882a593Smuzhiyun	pinctrl-names = "default";
722*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart2>;
723*4882a593Smuzhiyun	status = "okay";
724*4882a593Smuzhiyun};
725*4882a593Smuzhiyun
726*4882a593Smuzhiyun&usbh1 {
727*4882a593Smuzhiyun	vbus-supply = <&reg_usb_h1_vbus>;
728*4882a593Smuzhiyun	status = "okay";
729*4882a593Smuzhiyun};
730*4882a593Smuzhiyun
731*4882a593Smuzhiyun&usbotg {
732*4882a593Smuzhiyun	vbus-supply = <&reg_usb_otg_vbus>;
733*4882a593Smuzhiyun	pinctrl-names = "default";
734*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usbotg>;
735*4882a593Smuzhiyun	disable-over-current;
736*4882a593Smuzhiyun	status = "okay";
737*4882a593Smuzhiyun};
738*4882a593Smuzhiyun
739*4882a593Smuzhiyun&usdhc3 {
740*4882a593Smuzhiyun	pinctrl-names = "default";
741*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc3>;
742*4882a593Smuzhiyun	cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
743*4882a593Smuzhiyun	wp-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
744*4882a593Smuzhiyun	vmmc-supply = <&reg_3p3v>;
745*4882a593Smuzhiyun	status = "okay";
746*4882a593Smuzhiyun};
747*4882a593Smuzhiyun
748*4882a593Smuzhiyun&usdhc4 {
749*4882a593Smuzhiyun	pinctrl-names = "default";
750*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc4>;
751*4882a593Smuzhiyun	cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
752*4882a593Smuzhiyun	vmmc-supply = <&reg_3p3v>;
753*4882a593Smuzhiyun	status = "okay";
754*4882a593Smuzhiyun};
755*4882a593Smuzhiyun
756*4882a593Smuzhiyun&mipi_csi {
757*4882a593Smuzhiyun	status = "okay";
758*4882a593Smuzhiyun
759*4882a593Smuzhiyun	port@0 {
760*4882a593Smuzhiyun		reg = <0>;
761*4882a593Smuzhiyun
762*4882a593Smuzhiyun		mipi_csi2_in: endpoint {
763*4882a593Smuzhiyun			remote-endpoint = <&ov5640_to_mipi_csi2>;
764*4882a593Smuzhiyun			clock-lanes = <0>;
765*4882a593Smuzhiyun			data-lanes = <1 2>;
766*4882a593Smuzhiyun		};
767*4882a593Smuzhiyun	};
768*4882a593Smuzhiyun};
769