1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0+ OR MIT 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun#include "imx6qdl-pico.dtsi" 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun/ { 6*4882a593Smuzhiyun leds { 7*4882a593Smuzhiyun compatible = "gpio-leds"; 8*4882a593Smuzhiyun pinctrl-names = "default"; 9*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_gpio_leds>; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun led { 12*4882a593Smuzhiyun label = "gpio-led"; 13*4882a593Smuzhiyun gpios = <&gpio5 31 GPIO_ACTIVE_HIGH>; 14*4882a593Smuzhiyun }; 15*4882a593Smuzhiyun }; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun}; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun&i2c1 { 20*4882a593Smuzhiyun adc@52 { 21*4882a593Smuzhiyun compatible = "ti,adc081c"; 22*4882a593Smuzhiyun reg = <0x52>; 23*4882a593Smuzhiyun vref-supply = <®_2p5v>; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun}; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun&i2c2 { 28*4882a593Smuzhiyun io-expander@25 { 29*4882a593Smuzhiyun compatible = "nxp,pca9554"; 30*4882a593Smuzhiyun reg = <0x25>; 31*4882a593Smuzhiyun gpio-controller; 32*4882a593Smuzhiyun #gpio-cells = <2>; 33*4882a593Smuzhiyun #interrupt-cells = <2>; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun}; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun&i2c3 { 38*4882a593Smuzhiyun rtc@68 { 39*4882a593Smuzhiyun compatible = "dallas,ds1337"; 40*4882a593Smuzhiyun reg = <0x68>; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun}; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun&pcie { 45*4882a593Smuzhiyun status = "okay"; 46*4882a593Smuzhiyun}; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun&iomuxc { 49*4882a593Smuzhiyun pinctrl_gpio_leds: gpioledsgrp { 50*4882a593Smuzhiyun fsl,pins = < 51*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b0 52*4882a593Smuzhiyun >; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun}; 55