xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 OR X11
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright 2013 Boundary Devices, Inc.
4*4882a593Smuzhiyun * Copyright 2011 Freescale Semiconductor, Inc.
5*4882a593Smuzhiyun * Copyright 2011 Linaro Ltd.
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
8*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun/ {
11*4882a593Smuzhiyun	chosen {
12*4882a593Smuzhiyun		stdout-path = &uart2;
13*4882a593Smuzhiyun	};
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun	memory@10000000 {
16*4882a593Smuzhiyun		device_type = "memory";
17*4882a593Smuzhiyun		reg = <0x10000000 0x40000000>;
18*4882a593Smuzhiyun	};
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun	regulators {
21*4882a593Smuzhiyun		compatible = "simple-bus";
22*4882a593Smuzhiyun		#address-cells = <1>;
23*4882a593Smuzhiyun		#size-cells = <0>;
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun		reg_2p5v: regulator@0 {
26*4882a593Smuzhiyun			compatible = "regulator-fixed";
27*4882a593Smuzhiyun			reg = <0>;
28*4882a593Smuzhiyun			regulator-name = "2P5V";
29*4882a593Smuzhiyun			regulator-min-microvolt = <2500000>;
30*4882a593Smuzhiyun			regulator-max-microvolt = <2500000>;
31*4882a593Smuzhiyun			regulator-always-on;
32*4882a593Smuzhiyun		};
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun		reg_3p3v: regulator@1 {
35*4882a593Smuzhiyun			compatible = "regulator-fixed";
36*4882a593Smuzhiyun			reg = <1>;
37*4882a593Smuzhiyun			regulator-name = "3P3V";
38*4882a593Smuzhiyun			regulator-min-microvolt = <3300000>;
39*4882a593Smuzhiyun			regulator-max-microvolt = <3300000>;
40*4882a593Smuzhiyun			regulator-always-on;
41*4882a593Smuzhiyun		};
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun		reg_usb_otg_vbus: regulator@2 {
44*4882a593Smuzhiyun			compatible = "regulator-fixed";
45*4882a593Smuzhiyun			reg = <2>;
46*4882a593Smuzhiyun			regulator-name = "usb_otg_vbus";
47*4882a593Smuzhiyun			regulator-min-microvolt = <5000000>;
48*4882a593Smuzhiyun			regulator-max-microvolt = <5000000>;
49*4882a593Smuzhiyun			gpio = <&gpio3 22 0>;
50*4882a593Smuzhiyun			enable-active-high;
51*4882a593Smuzhiyun		};
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun		reg_can_xcvr: regulator@3 {
54*4882a593Smuzhiyun			compatible = "regulator-fixed";
55*4882a593Smuzhiyun			reg = <3>;
56*4882a593Smuzhiyun			regulator-name = "CAN XCVR";
57*4882a593Smuzhiyun			regulator-min-microvolt = <3300000>;
58*4882a593Smuzhiyun			regulator-max-microvolt = <3300000>;
59*4882a593Smuzhiyun			pinctrl-names = "default";
60*4882a593Smuzhiyun			pinctrl-0 = <&pinctrl_can_xcvr>;
61*4882a593Smuzhiyun			gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
62*4882a593Smuzhiyun		};
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun		reg_wlan_vmmc: regulator@4 {
65*4882a593Smuzhiyun			compatible = "regulator-fixed";
66*4882a593Smuzhiyun			reg = <4>;
67*4882a593Smuzhiyun			pinctrl-names = "default";
68*4882a593Smuzhiyun			pinctrl-0 = <&pinctrl_wlan_vmmc>;
69*4882a593Smuzhiyun			regulator-name = "reg_wlan_vmmc";
70*4882a593Smuzhiyun			regulator-min-microvolt = <3300000>;
71*4882a593Smuzhiyun			regulator-max-microvolt = <3300000>;
72*4882a593Smuzhiyun			gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>;
73*4882a593Smuzhiyun			startup-delay-us = <70000>;
74*4882a593Smuzhiyun			enable-active-high;
75*4882a593Smuzhiyun		};
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun		reg_usb_h1_vbus: regulator@5 {
78*4882a593Smuzhiyun			compatible = "regulator-fixed";
79*4882a593Smuzhiyun			reg = <5>;
80*4882a593Smuzhiyun			pinctrl-names = "default";
81*4882a593Smuzhiyun			pinctrl-0 = <&pinctrl_usbh1>;
82*4882a593Smuzhiyun			regulator-name = "usb_h1_vbus";
83*4882a593Smuzhiyun			regulator-min-microvolt = <3300000>;
84*4882a593Smuzhiyun			regulator-max-microvolt = <3300000>;
85*4882a593Smuzhiyun			gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
86*4882a593Smuzhiyun			enable-active-high;
87*4882a593Smuzhiyun		};
88*4882a593Smuzhiyun	};
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun	gpio-keys {
91*4882a593Smuzhiyun		compatible = "gpio-keys";
92*4882a593Smuzhiyun		pinctrl-names = "default";
93*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_gpio_keys>;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun		power {
96*4882a593Smuzhiyun			label = "Power Button";
97*4882a593Smuzhiyun			gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
98*4882a593Smuzhiyun			linux,code = <KEY_POWER>;
99*4882a593Smuzhiyun			wakeup-source;
100*4882a593Smuzhiyun		};
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun		menu {
103*4882a593Smuzhiyun			label = "Menu";
104*4882a593Smuzhiyun			gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
105*4882a593Smuzhiyun			linux,code = <KEY_MENU>;
106*4882a593Smuzhiyun		};
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun		home {
109*4882a593Smuzhiyun			label = "Home";
110*4882a593Smuzhiyun			gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
111*4882a593Smuzhiyun			linux,code = <KEY_HOME>;
112*4882a593Smuzhiyun		};
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun		back {
115*4882a593Smuzhiyun			label = "Back";
116*4882a593Smuzhiyun			gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
117*4882a593Smuzhiyun			linux,code = <KEY_BACK>;
118*4882a593Smuzhiyun		};
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun		volume-up {
121*4882a593Smuzhiyun			label = "Volume Up";
122*4882a593Smuzhiyun			gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
123*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEUP>;
124*4882a593Smuzhiyun		};
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun		volume-down {
127*4882a593Smuzhiyun			label = "Volume Down";
128*4882a593Smuzhiyun			gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
129*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEDOWN>;
130*4882a593Smuzhiyun		};
131*4882a593Smuzhiyun	};
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun	sound {
134*4882a593Smuzhiyun		compatible = "fsl,imx6q-nitrogen6x-sgtl5000",
135*4882a593Smuzhiyun			     "fsl,imx-audio-sgtl5000";
136*4882a593Smuzhiyun		model = "imx6q-nitrogen6x-sgtl5000";
137*4882a593Smuzhiyun		ssi-controller = <&ssi1>;
138*4882a593Smuzhiyun		audio-codec = <&codec>;
139*4882a593Smuzhiyun		audio-routing =
140*4882a593Smuzhiyun			"MIC_IN", "Mic Jack",
141*4882a593Smuzhiyun			"Mic Jack", "Mic Bias",
142*4882a593Smuzhiyun			"Headphone Jack", "HP_OUT";
143*4882a593Smuzhiyun		mux-int-port = <1>;
144*4882a593Smuzhiyun		mux-ext-port = <3>;
145*4882a593Smuzhiyun	};
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun	backlight_lcd: backlight-lcd {
148*4882a593Smuzhiyun		compatible = "pwm-backlight";
149*4882a593Smuzhiyun		pwms = <&pwm1 0 5000000>;
150*4882a593Smuzhiyun		brightness-levels = <0 4 8 16 32 64 128 255>;
151*4882a593Smuzhiyun		default-brightness-level = <7>;
152*4882a593Smuzhiyun		power-supply = <&reg_3p3v>;
153*4882a593Smuzhiyun		status = "okay";
154*4882a593Smuzhiyun	};
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun	backlight_lvds: backlight-lvds {
157*4882a593Smuzhiyun		compatible = "pwm-backlight";
158*4882a593Smuzhiyun		pwms = <&pwm4 0 5000000>;
159*4882a593Smuzhiyun		brightness-levels = <0 4 8 16 32 64 128 255>;
160*4882a593Smuzhiyun		default-brightness-level = <7>;
161*4882a593Smuzhiyun		power-supply = <&reg_3p3v>;
162*4882a593Smuzhiyun		status = "okay";
163*4882a593Smuzhiyun	};
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun	lcd_display: disp0 {
166*4882a593Smuzhiyun		compatible = "fsl,imx-parallel-display";
167*4882a593Smuzhiyun		#address-cells = <1>;
168*4882a593Smuzhiyun		#size-cells = <0>;
169*4882a593Smuzhiyun		interface-pix-fmt = "bgr666";
170*4882a593Smuzhiyun		pinctrl-names = "default";
171*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_j15>;
172*4882a593Smuzhiyun		status = "okay";
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun		port@0 {
175*4882a593Smuzhiyun			reg = <0>;
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun			lcd_display_in: endpoint {
178*4882a593Smuzhiyun				remote-endpoint = <&ipu1_di0_disp0>;
179*4882a593Smuzhiyun			};
180*4882a593Smuzhiyun		};
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun		port@1 {
183*4882a593Smuzhiyun			reg = <1>;
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun			lcd_display_out: endpoint {
186*4882a593Smuzhiyun				remote-endpoint = <&lcd_panel_in>;
187*4882a593Smuzhiyun			};
188*4882a593Smuzhiyun		};
189*4882a593Smuzhiyun	};
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun	panel-lcd {
192*4882a593Smuzhiyun		compatible = "okaya,rs800480t-7x0gp";
193*4882a593Smuzhiyun		backlight = <&backlight_lcd>;
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun		port {
196*4882a593Smuzhiyun			lcd_panel_in: endpoint {
197*4882a593Smuzhiyun				remote-endpoint = <&lcd_display_out>;
198*4882a593Smuzhiyun			};
199*4882a593Smuzhiyun		};
200*4882a593Smuzhiyun	};
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun	panel-lvds0 {
203*4882a593Smuzhiyun		compatible = "hannstar,hsd100pxn1";
204*4882a593Smuzhiyun		backlight = <&backlight_lvds>;
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun		port {
207*4882a593Smuzhiyun			panel_in: endpoint {
208*4882a593Smuzhiyun				remote-endpoint = <&lvds0_out>;
209*4882a593Smuzhiyun			};
210*4882a593Smuzhiyun		};
211*4882a593Smuzhiyun	};
212*4882a593Smuzhiyun};
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun&audmux {
215*4882a593Smuzhiyun	pinctrl-names = "default";
216*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_audmux>;
217*4882a593Smuzhiyun	status = "okay";
218*4882a593Smuzhiyun};
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun&can1 {
221*4882a593Smuzhiyun	pinctrl-names = "default";
222*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_can1>;
223*4882a593Smuzhiyun	xceiver-supply = <&reg_can_xcvr>;
224*4882a593Smuzhiyun	status = "okay";
225*4882a593Smuzhiyun};
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun&clks {
228*4882a593Smuzhiyun	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
229*4882a593Smuzhiyun			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
230*4882a593Smuzhiyun	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
231*4882a593Smuzhiyun				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
232*4882a593Smuzhiyun};
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun&ecspi1 {
235*4882a593Smuzhiyun	cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
236*4882a593Smuzhiyun	pinctrl-names = "default";
237*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_ecspi1>;
238*4882a593Smuzhiyun	status = "okay";
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun	flash: flash@0 {
241*4882a593Smuzhiyun		compatible = "sst,sst25vf016b", "jedec,spi-nor";
242*4882a593Smuzhiyun		spi-max-frequency = <20000000>;
243*4882a593Smuzhiyun		reg = <0>;
244*4882a593Smuzhiyun		#address-cells = <1>;
245*4882a593Smuzhiyun		#size-cells = <1>;
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun		partition@0 {
248*4882a593Smuzhiyun			label = "bootloader";
249*4882a593Smuzhiyun			reg = <0x0 0xc0000>;
250*4882a593Smuzhiyun		};
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun		partition@c0000 {
253*4882a593Smuzhiyun			label = "env";
254*4882a593Smuzhiyun			reg = <0xc0000 0x2000>;
255*4882a593Smuzhiyun		};
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun		partition@c2000 {
258*4882a593Smuzhiyun			label = "splash";
259*4882a593Smuzhiyun			reg = <0xc2000 0x13e000>;
260*4882a593Smuzhiyun		};
261*4882a593Smuzhiyun	};
262*4882a593Smuzhiyun};
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun&fec {
265*4882a593Smuzhiyun	pinctrl-names = "default";
266*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_enet>;
267*4882a593Smuzhiyun	phy-mode = "rgmii";
268*4882a593Smuzhiyun	phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
269*4882a593Smuzhiyun	txen-skew-ps = <0>;
270*4882a593Smuzhiyun	txc-skew-ps = <3000>;
271*4882a593Smuzhiyun	rxdv-skew-ps = <0>;
272*4882a593Smuzhiyun	rxc-skew-ps = <3000>;
273*4882a593Smuzhiyun	rxd0-skew-ps = <0>;
274*4882a593Smuzhiyun	rxd1-skew-ps = <0>;
275*4882a593Smuzhiyun	rxd2-skew-ps = <0>;
276*4882a593Smuzhiyun	rxd3-skew-ps = <0>;
277*4882a593Smuzhiyun	txd0-skew-ps = <0>;
278*4882a593Smuzhiyun	txd1-skew-ps = <0>;
279*4882a593Smuzhiyun	txd2-skew-ps = <0>;
280*4882a593Smuzhiyun	txd3-skew-ps = <0>;
281*4882a593Smuzhiyun	interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
282*4882a593Smuzhiyun			      <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
283*4882a593Smuzhiyun	fsl,err006687-workaround-present;
284*4882a593Smuzhiyun	status = "okay";
285*4882a593Smuzhiyun};
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun&hdmi {
288*4882a593Smuzhiyun	ddc-i2c-bus = <&i2c2>;
289*4882a593Smuzhiyun	status = "okay";
290*4882a593Smuzhiyun};
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun&i2c1 {
293*4882a593Smuzhiyun	clock-frequency = <100000>;
294*4882a593Smuzhiyun	pinctrl-names = "default";
295*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c1>;
296*4882a593Smuzhiyun	status = "okay";
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun	codec: sgtl5000@a {
299*4882a593Smuzhiyun		compatible = "fsl,sgtl5000";
300*4882a593Smuzhiyun		reg = <0x0a>;
301*4882a593Smuzhiyun		clocks = <&clks IMX6QDL_CLK_CKO>;
302*4882a593Smuzhiyun		VDDA-supply = <&reg_2p5v>;
303*4882a593Smuzhiyun		VDDIO-supply = <&reg_3p3v>;
304*4882a593Smuzhiyun	};
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun	rtc: rtc@6f {
307*4882a593Smuzhiyun		compatible = "isil,isl1208";
308*4882a593Smuzhiyun		reg = <0x6f>;
309*4882a593Smuzhiyun	};
310*4882a593Smuzhiyun};
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun&i2c2 {
313*4882a593Smuzhiyun	clock-frequency = <100000>;
314*4882a593Smuzhiyun	pinctrl-names = "default";
315*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c2>;
316*4882a593Smuzhiyun	status = "okay";
317*4882a593Smuzhiyun};
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun&i2c3 {
320*4882a593Smuzhiyun	clock-frequency = <100000>;
321*4882a593Smuzhiyun	pinctrl-names = "default";
322*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c3>;
323*4882a593Smuzhiyun	status = "okay";
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun	touchscreen@4 {
326*4882a593Smuzhiyun		compatible = "eeti,egalax_ts";
327*4882a593Smuzhiyun		reg = <0x04>;
328*4882a593Smuzhiyun		interrupt-parent = <&gpio1>;
329*4882a593Smuzhiyun		interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
330*4882a593Smuzhiyun		wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
331*4882a593Smuzhiyun	};
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun	touchscreen@38 {
334*4882a593Smuzhiyun		compatible = "edt,edt-ft5x06";
335*4882a593Smuzhiyun		reg = <0x38>;
336*4882a593Smuzhiyun		interrupt-parent = <&gpio1>;
337*4882a593Smuzhiyun		interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
338*4882a593Smuzhiyun		wakeup-source;
339*4882a593Smuzhiyun	};
340*4882a593Smuzhiyun};
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun&iomuxc {
343*4882a593Smuzhiyun	pinctrl-names = "default";
344*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_hog>;
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun	imx6q-nitrogen6x {
347*4882a593Smuzhiyun		pinctrl_hog: hoggrp {
348*4882a593Smuzhiyun			fsl,pins = <
349*4882a593Smuzhiyun				/* SGTL5000 sys_mclk */
350*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x030b0
351*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_9__GPIO1_IO09	0x1b0b0
352*4882a593Smuzhiyun			>;
353*4882a593Smuzhiyun		};
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun		pinctrl_audmux: audmuxgrp {
356*4882a593Smuzhiyun			fsl,pins = <
357*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT7__AUD3_RXD		0x130b0
358*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT4__AUD3_TXC		0x130b0
359*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT5__AUD3_TXD		0x110b0
360*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS		0x130b0
361*4882a593Smuzhiyun			>;
362*4882a593Smuzhiyun		};
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun		pinctrl_can1: can1grp {
365*4882a593Smuzhiyun			fsl,pins = <
366*4882a593Smuzhiyun				MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX	0x1b0b0
367*4882a593Smuzhiyun				MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX	0x1b0b0
368*4882a593Smuzhiyun			>;
369*4882a593Smuzhiyun		};
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun		pinctrl_can_xcvr: can-xcvrgrp {
372*4882a593Smuzhiyun			fsl,pins = <
373*4882a593Smuzhiyun				/* Flexcan XCVR enable */
374*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_2__GPIO1_IO02		0x1b0b0
375*4882a593Smuzhiyun			>;
376*4882a593Smuzhiyun		};
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun		pinctrl_ecspi1: ecspi1grp {
379*4882a593Smuzhiyun			fsl,pins = <
380*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D17__ECSPI1_MISO		0x100b1
381*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D18__ECSPI1_MOSI		0x100b1
382*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D16__ECSPI1_SCLK		0x100b1
383*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D19__GPIO3_IO19  0x000b1	/* CS */
384*4882a593Smuzhiyun			>;
385*4882a593Smuzhiyun		};
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun		pinctrl_enet: enetgrp {
388*4882a593Smuzhiyun			fsl,pins = <
389*4882a593Smuzhiyun				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x100b0
390*4882a593Smuzhiyun				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x100b0
391*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x10030
392*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x10030
393*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x10030
394*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x10030
395*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x10030
396*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x10030
397*4882a593Smuzhiyun				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x100b0
398*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
399*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
400*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
401*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
402*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
403*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
404*4882a593Smuzhiyun				/* Phy reset */
405*4882a593Smuzhiyun				MX6QDL_PAD_ENET_RXD0__GPIO1_IO27	0x000b0
406*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_6__ENET_IRQ		0x000b1
407*4882a593Smuzhiyun			>;
408*4882a593Smuzhiyun		};
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun		pinctrl_gpio_keys: gpio-keysgrp {
411*4882a593Smuzhiyun			fsl,pins = <
412*4882a593Smuzhiyun				/* Power Button */
413*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_D3__GPIO2_IO03		0x1b0b0
414*4882a593Smuzhiyun				/* Menu Button */
415*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_D1__GPIO2_IO01		0x1b0b0
416*4882a593Smuzhiyun				/* Home Button */
417*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_D4__GPIO2_IO04		0x1b0b0
418*4882a593Smuzhiyun				/* Back Button */
419*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_D2__GPIO2_IO02		0x1b0b0
420*4882a593Smuzhiyun				/* Volume Up Button */
421*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_18__GPIO7_IO13		0x1b0b0
422*4882a593Smuzhiyun				/* Volume Down Button */
423*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_19__GPIO4_IO05		0x1b0b0
424*4882a593Smuzhiyun			>;
425*4882a593Smuzhiyun		};
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun		pinctrl_i2c1: i2c1grp {
428*4882a593Smuzhiyun			fsl,pins = <
429*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1
430*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1
431*4882a593Smuzhiyun			>;
432*4882a593Smuzhiyun		};
433*4882a593Smuzhiyun
434*4882a593Smuzhiyun		pinctrl_i2c2: i2c2grp {
435*4882a593Smuzhiyun			fsl,pins = <
436*4882a593Smuzhiyun				MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
437*4882a593Smuzhiyun				MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
438*4882a593Smuzhiyun			>;
439*4882a593Smuzhiyun		};
440*4882a593Smuzhiyun
441*4882a593Smuzhiyun		pinctrl_i2c3: i2c3grp {
442*4882a593Smuzhiyun			fsl,pins = <
443*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_5__I2C3_SCL		0x4001b8b1
444*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_16__I2C3_SDA		0x4001b8b1
445*4882a593Smuzhiyun			>;
446*4882a593Smuzhiyun		};
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun		pinctrl_j15: j15grp {
449*4882a593Smuzhiyun			fsl,pins = <
450*4882a593Smuzhiyun				MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
451*4882a593Smuzhiyun				MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
452*4882a593Smuzhiyun				MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
453*4882a593Smuzhiyun				MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
454*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
455*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
456*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
457*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
458*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
459*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
460*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
461*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
462*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
463*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
464*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
465*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
466*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
467*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
468*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
469*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
470*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
471*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
472*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
473*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
474*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
475*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
476*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
477*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
478*4882a593Smuzhiyun			>;
479*4882a593Smuzhiyun		};
480*4882a593Smuzhiyun
481*4882a593Smuzhiyun		pinctrl_pwm1: pwm1grp {
482*4882a593Smuzhiyun			fsl,pins = <
483*4882a593Smuzhiyun				MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
484*4882a593Smuzhiyun			>;
485*4882a593Smuzhiyun		};
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun		pinctrl_pwm3: pwm3grp {
488*4882a593Smuzhiyun			fsl,pins = <
489*4882a593Smuzhiyun				MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
490*4882a593Smuzhiyun			>;
491*4882a593Smuzhiyun		};
492*4882a593Smuzhiyun
493*4882a593Smuzhiyun		pinctrl_pwm4: pwm4grp {
494*4882a593Smuzhiyun			fsl,pins = <
495*4882a593Smuzhiyun				MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
496*4882a593Smuzhiyun			>;
497*4882a593Smuzhiyun		};
498*4882a593Smuzhiyun
499*4882a593Smuzhiyun		pinctrl_uart1: uart1grp {
500*4882a593Smuzhiyun			fsl,pins = <
501*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA	0x1b0b1
502*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA	0x1b0b1
503*4882a593Smuzhiyun			>;
504*4882a593Smuzhiyun		};
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun		pinctrl_uart2: uart2grp {
507*4882a593Smuzhiyun			fsl,pins = <
508*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D26__UART2_TX_DATA	0x1b0b1
509*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D27__UART2_RX_DATA	0x1b0b1
510*4882a593Smuzhiyun			>;
511*4882a593Smuzhiyun		};
512*4882a593Smuzhiyun
513*4882a593Smuzhiyun		pinctrl_usbh1: usbh1grp {
514*4882a593Smuzhiyun			fsl,pins = <
515*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_17__GPIO7_IO12		0x030b0
516*4882a593Smuzhiyun			>;
517*4882a593Smuzhiyun		};
518*4882a593Smuzhiyun
519*4882a593Smuzhiyun		pinctrl_usbotg: usbotggrp {
520*4882a593Smuzhiyun			fsl,pins = <
521*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_1__USB_OTG_ID	0x17059
522*4882a593Smuzhiyun				MX6QDL_PAD_KEY_COL4__USB_OTG_OC	0x1b0b0
523*4882a593Smuzhiyun				/* power enable, high active */
524*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x000b0
525*4882a593Smuzhiyun			>;
526*4882a593Smuzhiyun		};
527*4882a593Smuzhiyun
528*4882a593Smuzhiyun		pinctrl_usdhc2: usdhc2grp {
529*4882a593Smuzhiyun			fsl,pins = <
530*4882a593Smuzhiyun				MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17071
531*4882a593Smuzhiyun				MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10071
532*4882a593Smuzhiyun				MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17071
533*4882a593Smuzhiyun				MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17071
534*4882a593Smuzhiyun				MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17071
535*4882a593Smuzhiyun				MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17071
536*4882a593Smuzhiyun			>;
537*4882a593Smuzhiyun		};
538*4882a593Smuzhiyun
539*4882a593Smuzhiyun		pinctrl_usdhc3: usdhc3grp {
540*4882a593Smuzhiyun			fsl,pins = <
541*4882a593Smuzhiyun				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
542*4882a593Smuzhiyun				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
543*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
544*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
545*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
546*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
547*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0	/* CD */
548*4882a593Smuzhiyun			>;
549*4882a593Smuzhiyun		};
550*4882a593Smuzhiyun
551*4882a593Smuzhiyun		pinctrl_usdhc4: usdhc4grp {
552*4882a593Smuzhiyun			fsl,pins = <
553*4882a593Smuzhiyun				MX6QDL_PAD_SD4_CMD__SD4_CMD		0x17059
554*4882a593Smuzhiyun				MX6QDL_PAD_SD4_CLK__SD4_CLK		0x10059
555*4882a593Smuzhiyun				MX6QDL_PAD_SD4_DAT0__SD4_DATA0		0x17059
556*4882a593Smuzhiyun				MX6QDL_PAD_SD4_DAT1__SD4_DATA1		0x17059
557*4882a593Smuzhiyun				MX6QDL_PAD_SD4_DAT2__SD4_DATA2		0x17059
558*4882a593Smuzhiyun				MX6QDL_PAD_SD4_DAT3__SD4_DATA3		0x17059
559*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0	/* CD */
560*4882a593Smuzhiyun			>;
561*4882a593Smuzhiyun		};
562*4882a593Smuzhiyun
563*4882a593Smuzhiyun		pinctrl_wlan_vmmc: wlan-vmmcgrp {
564*4882a593Smuzhiyun			fsl,pins = <
565*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_CS0__GPIO6_IO11	0x100b0
566*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_CS2__GPIO6_IO15	0x000b0
567*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_CS3__GPIO6_IO16	0x000b0
568*4882a593Smuzhiyun				MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT	0x000b0
569*4882a593Smuzhiyun			>;
570*4882a593Smuzhiyun		};
571*4882a593Smuzhiyun	};
572*4882a593Smuzhiyun};
573*4882a593Smuzhiyun
574*4882a593Smuzhiyun&ipu1_di0_disp0 {
575*4882a593Smuzhiyun	remote-endpoint = <&lcd_display_in>;
576*4882a593Smuzhiyun};
577*4882a593Smuzhiyun
578*4882a593Smuzhiyun&ldb {
579*4882a593Smuzhiyun	status = "okay";
580*4882a593Smuzhiyun
581*4882a593Smuzhiyun	lvds-channel@0 {
582*4882a593Smuzhiyun		status = "okay";
583*4882a593Smuzhiyun
584*4882a593Smuzhiyun		port@4 {
585*4882a593Smuzhiyun			reg = <4>;
586*4882a593Smuzhiyun
587*4882a593Smuzhiyun			lvds0_out: endpoint {
588*4882a593Smuzhiyun				remote-endpoint = <&panel_in>;
589*4882a593Smuzhiyun			};
590*4882a593Smuzhiyun		};
591*4882a593Smuzhiyun	};
592*4882a593Smuzhiyun};
593*4882a593Smuzhiyun
594*4882a593Smuzhiyun&pcie {
595*4882a593Smuzhiyun	status = "okay";
596*4882a593Smuzhiyun};
597*4882a593Smuzhiyun
598*4882a593Smuzhiyun&pwm1 {
599*4882a593Smuzhiyun	#pwm-cells = <2>;
600*4882a593Smuzhiyun	pinctrl-names = "default";
601*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pwm1>;
602*4882a593Smuzhiyun	status = "okay";
603*4882a593Smuzhiyun};
604*4882a593Smuzhiyun
605*4882a593Smuzhiyun&pwm3 {
606*4882a593Smuzhiyun	pinctrl-names = "default";
607*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pwm3>;
608*4882a593Smuzhiyun	status = "okay";
609*4882a593Smuzhiyun};
610*4882a593Smuzhiyun
611*4882a593Smuzhiyun&pwm4 {
612*4882a593Smuzhiyun	#pwm-cells = <2>;
613*4882a593Smuzhiyun	pinctrl-names = "default";
614*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pwm4>;
615*4882a593Smuzhiyun	status = "okay";
616*4882a593Smuzhiyun};
617*4882a593Smuzhiyun
618*4882a593Smuzhiyun&ssi1 {
619*4882a593Smuzhiyun	status = "okay";
620*4882a593Smuzhiyun};
621*4882a593Smuzhiyun
622*4882a593Smuzhiyun&uart1 {
623*4882a593Smuzhiyun	pinctrl-names = "default";
624*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart1>;
625*4882a593Smuzhiyun	status = "okay";
626*4882a593Smuzhiyun};
627*4882a593Smuzhiyun
628*4882a593Smuzhiyun&uart2 {
629*4882a593Smuzhiyun	pinctrl-names = "default";
630*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart2>;
631*4882a593Smuzhiyun	status = "okay";
632*4882a593Smuzhiyun};
633*4882a593Smuzhiyun
634*4882a593Smuzhiyun&usbh1 {
635*4882a593Smuzhiyun	vbus-supply = <&reg_usb_h1_vbus>;
636*4882a593Smuzhiyun	status = "okay";
637*4882a593Smuzhiyun};
638*4882a593Smuzhiyun
639*4882a593Smuzhiyun&usbotg {
640*4882a593Smuzhiyun	vbus-supply = <&reg_usb_otg_vbus>;
641*4882a593Smuzhiyun	pinctrl-names = "default";
642*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usbotg>;
643*4882a593Smuzhiyun	disable-over-current;
644*4882a593Smuzhiyun	status = "okay";
645*4882a593Smuzhiyun};
646*4882a593Smuzhiyun
647*4882a593Smuzhiyun&usdhc2 {
648*4882a593Smuzhiyun	pinctrl-names = "default";
649*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc2>;
650*4882a593Smuzhiyun	bus-width = <4>;
651*4882a593Smuzhiyun	non-removable;
652*4882a593Smuzhiyun	vmmc-supply = <&reg_wlan_vmmc>;
653*4882a593Smuzhiyun	cap-power-off-card;
654*4882a593Smuzhiyun	keep-power-in-suspend;
655*4882a593Smuzhiyun	status = "okay";
656*4882a593Smuzhiyun
657*4882a593Smuzhiyun	#address-cells = <1>;
658*4882a593Smuzhiyun	#size-cells = <0>;
659*4882a593Smuzhiyun	wlcore: wlcore@2 {
660*4882a593Smuzhiyun		compatible = "ti,wl1271";
661*4882a593Smuzhiyun		reg = <2>;
662*4882a593Smuzhiyun		interrupt-parent = <&gpio6>;
663*4882a593Smuzhiyun		interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
664*4882a593Smuzhiyun		ref-clock-frequency = <38400000>;
665*4882a593Smuzhiyun	};
666*4882a593Smuzhiyun};
667*4882a593Smuzhiyun
668*4882a593Smuzhiyun&usdhc3 {
669*4882a593Smuzhiyun	pinctrl-names = "default";
670*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc3>;
671*4882a593Smuzhiyun	cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
672*4882a593Smuzhiyun	vmmc-supply = <&reg_3p3v>;
673*4882a593Smuzhiyun	status = "okay";
674*4882a593Smuzhiyun};
675*4882a593Smuzhiyun
676*4882a593Smuzhiyun&usdhc4 {
677*4882a593Smuzhiyun	pinctrl-names = "default";
678*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc4>;
679*4882a593Smuzhiyun	cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
680*4882a593Smuzhiyun	vmmc-supply = <&reg_3p3v>;
681*4882a593Smuzhiyun	status = "okay";
682*4882a593Smuzhiyun};
683