1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 OR X11 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright 2016 Boundary Devices, Inc. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 6*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/ { 9*4882a593Smuzhiyun chosen { 10*4882a593Smuzhiyun stdout-path = &uart2; 11*4882a593Smuzhiyun }; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun memory@10000000 { 14*4882a593Smuzhiyun device_type = "memory"; 15*4882a593Smuzhiyun reg = <0x10000000 0x40000000>; 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun backlight_lcd: backlight-lcd { 19*4882a593Smuzhiyun compatible = "pwm-backlight"; 20*4882a593Smuzhiyun pwms = <&pwm1 0 5000000>; 21*4882a593Smuzhiyun brightness-levels = <0 4 8 16 32 64 128 255>; 22*4882a593Smuzhiyun default-brightness-level = <7>; 23*4882a593Smuzhiyun power-supply = <®_3p3v>; 24*4882a593Smuzhiyun status = "okay"; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun backlight_lvds0: backlight-lvds0 { 28*4882a593Smuzhiyun compatible = "pwm-backlight"; 29*4882a593Smuzhiyun pwms = <&pwm4 0 5000000>; 30*4882a593Smuzhiyun brightness-levels = <0 4 8 16 32 64 128 255>; 31*4882a593Smuzhiyun default-brightness-level = <7>; 32*4882a593Smuzhiyun power-supply = <®_3p3v>; 33*4882a593Smuzhiyun status = "okay"; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun backlight_lvds1: backlight-lvds1 { 37*4882a593Smuzhiyun compatible = "gpio-backlight"; 38*4882a593Smuzhiyun pinctrl-names = "default"; 39*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_backlight_lvds1>; 40*4882a593Smuzhiyun gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; 41*4882a593Smuzhiyun default-on; 42*4882a593Smuzhiyun status = "okay"; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun gpio-keys { 46*4882a593Smuzhiyun compatible = "gpio-keys"; 47*4882a593Smuzhiyun pinctrl-names = "default"; 48*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_gpio_keys>; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun power { 51*4882a593Smuzhiyun label = "Power Button"; 52*4882a593Smuzhiyun gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; 53*4882a593Smuzhiyun linux,code = <KEY_POWER>; 54*4882a593Smuzhiyun wakeup-source; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun menu { 58*4882a593Smuzhiyun label = "Menu"; 59*4882a593Smuzhiyun gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; 60*4882a593Smuzhiyun linux,code = <KEY_MENU>; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun home { 64*4882a593Smuzhiyun label = "Home"; 65*4882a593Smuzhiyun gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; 66*4882a593Smuzhiyun linux,code = <KEY_HOME>; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun back { 70*4882a593Smuzhiyun label = "Back"; 71*4882a593Smuzhiyun gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; 72*4882a593Smuzhiyun linux,code = <KEY_BACK>; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun volume-up { 76*4882a593Smuzhiyun label = "Volume Up"; 77*4882a593Smuzhiyun gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; 78*4882a593Smuzhiyun linux,code = <KEY_VOLUMEUP>; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun volume-down { 82*4882a593Smuzhiyun label = "Volume Down"; 83*4882a593Smuzhiyun gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; 84*4882a593Smuzhiyun linux,code = <KEY_VOLUMEDOWN>; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun lcd_display: disp0 { 89*4882a593Smuzhiyun compatible = "fsl,imx-parallel-display"; 90*4882a593Smuzhiyun #address-cells = <1>; 91*4882a593Smuzhiyun #size-cells = <0>; 92*4882a593Smuzhiyun interface-pix-fmt = "bgr666"; 93*4882a593Smuzhiyun pinctrl-names = "default"; 94*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_j15>; 95*4882a593Smuzhiyun status = "okay"; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun port@0 { 98*4882a593Smuzhiyun reg = <0>; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun lcd_display_in: endpoint { 101*4882a593Smuzhiyun remote-endpoint = <&ipu1_di0_disp0>; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun port@1 { 106*4882a593Smuzhiyun reg = <1>; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun lcd_display_out: endpoint { 109*4882a593Smuzhiyun remote-endpoint = <&lcd_panel_in>; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun panel-lcd { 115*4882a593Smuzhiyun compatible = "okaya,rs800480t-7x0gp"; 116*4882a593Smuzhiyun backlight = <&backlight_lcd>; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun port { 119*4882a593Smuzhiyun lcd_panel_in: endpoint { 120*4882a593Smuzhiyun remote-endpoint = <&lcd_display_out>; 121*4882a593Smuzhiyun }; 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun }; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun panel-lvds0 { 126*4882a593Smuzhiyun compatible = "hannstar,hsd100pxn1"; 127*4882a593Smuzhiyun backlight = <&backlight_lvds0>; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun port { 130*4882a593Smuzhiyun panel_in_lvds0: endpoint { 131*4882a593Smuzhiyun remote-endpoint = <&lvds0_out>; 132*4882a593Smuzhiyun }; 133*4882a593Smuzhiyun }; 134*4882a593Smuzhiyun }; 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun panel-lvds1 { 137*4882a593Smuzhiyun compatible = "hannstar,hsd100pxn1"; 138*4882a593Smuzhiyun backlight = <&backlight_lvds1>; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun port { 141*4882a593Smuzhiyun panel_in_lvds1: endpoint { 142*4882a593Smuzhiyun remote-endpoint = <&lvds1_out>; 143*4882a593Smuzhiyun }; 144*4882a593Smuzhiyun }; 145*4882a593Smuzhiyun }; 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun reg_1p8v: regulator-1v8 { 148*4882a593Smuzhiyun compatible = "regulator-fixed"; 149*4882a593Smuzhiyun regulator-name = "1P8V"; 150*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 151*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 152*4882a593Smuzhiyun regulator-always-on; 153*4882a593Smuzhiyun }; 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun reg_2p5v: regulator-2v5 { 156*4882a593Smuzhiyun compatible = "regulator-fixed"; 157*4882a593Smuzhiyun regulator-name = "2P5V"; 158*4882a593Smuzhiyun regulator-min-microvolt = <2500000>; 159*4882a593Smuzhiyun regulator-max-microvolt = <2500000>; 160*4882a593Smuzhiyun regulator-always-on; 161*4882a593Smuzhiyun }; 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun reg_3p3v: regulator-3v3 { 164*4882a593Smuzhiyun compatible = "regulator-fixed"; 165*4882a593Smuzhiyun regulator-name = "3P3V"; 166*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 167*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 168*4882a593Smuzhiyun regulator-always-on; 169*4882a593Smuzhiyun }; 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun reg_can_xcvr: regulator-can-xcvr { 172*4882a593Smuzhiyun compatible = "regulator-fixed"; 173*4882a593Smuzhiyun regulator-name = "CAN XCVR"; 174*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 175*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 176*4882a593Smuzhiyun pinctrl-names = "default"; 177*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_can_xcvr>; 178*4882a593Smuzhiyun gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; 179*4882a593Smuzhiyun }; 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun reg_usb_h1_vbus: regulator-usb-h1-vbus { 182*4882a593Smuzhiyun compatible = "regulator-fixed"; 183*4882a593Smuzhiyun pinctrl-names = "default"; 184*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usbh1>; 185*4882a593Smuzhiyun regulator-name = "usb_h1_vbus"; 186*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 187*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 188*4882a593Smuzhiyun gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; 189*4882a593Smuzhiyun enable-active-high; 190*4882a593Smuzhiyun regulator-always-on; 191*4882a593Smuzhiyun }; 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun reg_usb_otg_vbus: regulator-usb-otg-vbus { 194*4882a593Smuzhiyun compatible = "regulator-fixed"; 195*4882a593Smuzhiyun regulator-name = "usb_otg_vbus"; 196*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 197*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 198*4882a593Smuzhiyun gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 199*4882a593Smuzhiyun enable-active-high; 200*4882a593Smuzhiyun }; 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun reg_wlan_vmmc: regulator-wlan-vmmc { 203*4882a593Smuzhiyun compatible = "regulator-fixed"; 204*4882a593Smuzhiyun pinctrl-names = "default"; 205*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_wlan_vmmc>; 206*4882a593Smuzhiyun regulator-name = "reg_wlan_vmmc"; 207*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 208*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 209*4882a593Smuzhiyun gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>; 210*4882a593Smuzhiyun startup-delay-us = <70000>; 211*4882a593Smuzhiyun enable-active-high; 212*4882a593Smuzhiyun }; 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun sound { 215*4882a593Smuzhiyun compatible = "fsl,imx6q-nitrogen6_som2-sgtl5000", 216*4882a593Smuzhiyun "fsl,imx-audio-sgtl5000"; 217*4882a593Smuzhiyun model = "imx6q-nitrogen6_som2-sgtl5000"; 218*4882a593Smuzhiyun ssi-controller = <&ssi1>; 219*4882a593Smuzhiyun audio-codec = <&codec>; 220*4882a593Smuzhiyun audio-routing = 221*4882a593Smuzhiyun "MIC_IN", "Mic Jack", 222*4882a593Smuzhiyun "Mic Jack", "Mic Bias", 223*4882a593Smuzhiyun "Headphone Jack", "HP_OUT"; 224*4882a593Smuzhiyun mux-int-port = <1>; 225*4882a593Smuzhiyun mux-ext-port = <3>; 226*4882a593Smuzhiyun }; 227*4882a593Smuzhiyun}; 228*4882a593Smuzhiyun 229*4882a593Smuzhiyun&audmux { 230*4882a593Smuzhiyun pinctrl-names = "default"; 231*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_audmux>; 232*4882a593Smuzhiyun status = "okay"; 233*4882a593Smuzhiyun}; 234*4882a593Smuzhiyun 235*4882a593Smuzhiyun&can1 { 236*4882a593Smuzhiyun pinctrl-names = "default"; 237*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_can1>; 238*4882a593Smuzhiyun xceiver-supply = <®_can_xcvr>; 239*4882a593Smuzhiyun status = "okay"; 240*4882a593Smuzhiyun}; 241*4882a593Smuzhiyun 242*4882a593Smuzhiyun&clks { 243*4882a593Smuzhiyun assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 244*4882a593Smuzhiyun <&clks IMX6QDL_CLK_LDB_DI1_SEL>; 245*4882a593Smuzhiyun assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, 246*4882a593Smuzhiyun <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 247*4882a593Smuzhiyun}; 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun&ecspi1 { 250*4882a593Smuzhiyun cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; 251*4882a593Smuzhiyun pinctrl-names = "default"; 252*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_ecspi1>; 253*4882a593Smuzhiyun status = "okay"; 254*4882a593Smuzhiyun 255*4882a593Smuzhiyun flash: flash@0 { 256*4882a593Smuzhiyun compatible = "microchip,sst25vf016b"; 257*4882a593Smuzhiyun spi-max-frequency = <20000000>; 258*4882a593Smuzhiyun reg = <0>; 259*4882a593Smuzhiyun }; 260*4882a593Smuzhiyun}; 261*4882a593Smuzhiyun 262*4882a593Smuzhiyun&fec { 263*4882a593Smuzhiyun pinctrl-names = "default"; 264*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_enet>; 265*4882a593Smuzhiyun phy-mode = "rgmii"; 266*4882a593Smuzhiyun interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, 267*4882a593Smuzhiyun <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; 268*4882a593Smuzhiyun fsl,err006687-workaround-present; 269*4882a593Smuzhiyun status = "okay"; 270*4882a593Smuzhiyun}; 271*4882a593Smuzhiyun 272*4882a593Smuzhiyun&hdmi { 273*4882a593Smuzhiyun ddc-i2c-bus = <&i2c2>; 274*4882a593Smuzhiyun status = "okay"; 275*4882a593Smuzhiyun}; 276*4882a593Smuzhiyun 277*4882a593Smuzhiyun&i2c1 { 278*4882a593Smuzhiyun clock-frequency = <100000>; 279*4882a593Smuzhiyun pinctrl-names = "default"; 280*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c1>; 281*4882a593Smuzhiyun status = "okay"; 282*4882a593Smuzhiyun 283*4882a593Smuzhiyun codec: sgtl5000@a { 284*4882a593Smuzhiyun compatible = "fsl,sgtl5000"; 285*4882a593Smuzhiyun pinctrl-names = "default"; 286*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_sgtl5000>; 287*4882a593Smuzhiyun reg = <0x0a>; 288*4882a593Smuzhiyun clocks = <&clks IMX6QDL_CLK_CKO>; 289*4882a593Smuzhiyun VDDA-supply = <®_2p5v>; 290*4882a593Smuzhiyun VDDIO-supply = <®_3p3v>; 291*4882a593Smuzhiyun }; 292*4882a593Smuzhiyun 293*4882a593Smuzhiyun rtc@68 { 294*4882a593Smuzhiyun compatible = "microcrystal,rv4162"; 295*4882a593Smuzhiyun pinctrl-names = "default"; 296*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_rv4162>; 297*4882a593Smuzhiyun reg = <0x68>; 298*4882a593Smuzhiyun interrupts-extended = <&gpio6 7 IRQ_TYPE_LEVEL_LOW>; 299*4882a593Smuzhiyun }; 300*4882a593Smuzhiyun}; 301*4882a593Smuzhiyun 302*4882a593Smuzhiyun&i2c2 { 303*4882a593Smuzhiyun clock-frequency = <100000>; 304*4882a593Smuzhiyun pinctrl-names = "default"; 305*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c2>; 306*4882a593Smuzhiyun status = "okay"; 307*4882a593Smuzhiyun}; 308*4882a593Smuzhiyun 309*4882a593Smuzhiyun&i2c3 { 310*4882a593Smuzhiyun clock-frequency = <100000>; 311*4882a593Smuzhiyun pinctrl-names = "default"; 312*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c3>; 313*4882a593Smuzhiyun status = "okay"; 314*4882a593Smuzhiyun 315*4882a593Smuzhiyun touchscreen@4 { 316*4882a593Smuzhiyun compatible = "eeti,egalax_ts"; 317*4882a593Smuzhiyun reg = <0x04>; 318*4882a593Smuzhiyun interrupt-parent = <&gpio1>; 319*4882a593Smuzhiyun interrupts = <9 IRQ_TYPE_EDGE_FALLING>; 320*4882a593Smuzhiyun wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; 321*4882a593Smuzhiyun }; 322*4882a593Smuzhiyun 323*4882a593Smuzhiyun touchscreen@38 { 324*4882a593Smuzhiyun compatible = "edt,edt-ft5x06"; 325*4882a593Smuzhiyun reg = <0x38>; 326*4882a593Smuzhiyun interrupt-parent = <&gpio1>; 327*4882a593Smuzhiyun interrupts = <9 IRQ_TYPE_EDGE_FALLING>; 328*4882a593Smuzhiyun wakeup-source; 329*4882a593Smuzhiyun }; 330*4882a593Smuzhiyun}; 331*4882a593Smuzhiyun 332*4882a593Smuzhiyun&iomuxc { 333*4882a593Smuzhiyun pinctrl_audmux: audmuxgrp { 334*4882a593Smuzhiyun fsl,pins = < 335*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 336*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 337*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 338*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 339*4882a593Smuzhiyun >; 340*4882a593Smuzhiyun }; 341*4882a593Smuzhiyun 342*4882a593Smuzhiyun pinctrl_backlight_lvds1: backlight-lvds1grp { 343*4882a593Smuzhiyun fsl,pins = < 344*4882a593Smuzhiyun MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x0b0b0 345*4882a593Smuzhiyun >; 346*4882a593Smuzhiyun }; 347*4882a593Smuzhiyun 348*4882a593Smuzhiyun pinctrl_can1: can1grp { 349*4882a593Smuzhiyun fsl,pins = < 350*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 351*4882a593Smuzhiyun MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 352*4882a593Smuzhiyun >; 353*4882a593Smuzhiyun }; 354*4882a593Smuzhiyun 355*4882a593Smuzhiyun pinctrl_can_xcvr: can-xcvrgrp { 356*4882a593Smuzhiyun fsl,pins = < 357*4882a593Smuzhiyun /* Flexcan XCVR enable */ 358*4882a593Smuzhiyun MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0b0b0 359*4882a593Smuzhiyun >; 360*4882a593Smuzhiyun }; 361*4882a593Smuzhiyun 362*4882a593Smuzhiyun pinctrl_ecspi1: ecspi1grp { 363*4882a593Smuzhiyun fsl,pins = < 364*4882a593Smuzhiyun MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 365*4882a593Smuzhiyun MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 366*4882a593Smuzhiyun MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 367*4882a593Smuzhiyun MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 368*4882a593Smuzhiyun >; 369*4882a593Smuzhiyun }; 370*4882a593Smuzhiyun 371*4882a593Smuzhiyun pinctrl_enet: enetgrp { 372*4882a593Smuzhiyun fsl,pins = < 373*4882a593Smuzhiyun MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 374*4882a593Smuzhiyun MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 375*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 376*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 377*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 378*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 379*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 380*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 381*4882a593Smuzhiyun MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 382*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 383*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0 384*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 385*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x130b0 386*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 387*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 388*4882a593Smuzhiyun MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0 389*4882a593Smuzhiyun MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 390*4882a593Smuzhiyun MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 391*4882a593Smuzhiyun >; 392*4882a593Smuzhiyun }; 393*4882a593Smuzhiyun 394*4882a593Smuzhiyun pinctrl_gpio_keys: gpio-keysgrp { 395*4882a593Smuzhiyun fsl,pins = < 396*4882a593Smuzhiyun /* Power Button */ 397*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 398*4882a593Smuzhiyun /* Menu Button */ 399*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 400*4882a593Smuzhiyun /* Home Button */ 401*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 402*4882a593Smuzhiyun /* Back Button */ 403*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 404*4882a593Smuzhiyun /* Volume Up Button */ 405*4882a593Smuzhiyun MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 406*4882a593Smuzhiyun /* Volume Down Button */ 407*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 408*4882a593Smuzhiyun >; 409*4882a593Smuzhiyun }; 410*4882a593Smuzhiyun 411*4882a593Smuzhiyun pinctrl_i2c1: i2c1grp { 412*4882a593Smuzhiyun fsl,pins = < 413*4882a593Smuzhiyun MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 414*4882a593Smuzhiyun MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 415*4882a593Smuzhiyun >; 416*4882a593Smuzhiyun }; 417*4882a593Smuzhiyun 418*4882a593Smuzhiyun pinctrl_i2c2: i2c2grp { 419*4882a593Smuzhiyun fsl,pins = < 420*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 421*4882a593Smuzhiyun MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 422*4882a593Smuzhiyun >; 423*4882a593Smuzhiyun }; 424*4882a593Smuzhiyun 425*4882a593Smuzhiyun pinctrl_i2c3: i2c3grp { 426*4882a593Smuzhiyun fsl,pins = < 427*4882a593Smuzhiyun MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 428*4882a593Smuzhiyun MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 429*4882a593Smuzhiyun MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 430*4882a593Smuzhiyun >; 431*4882a593Smuzhiyun }; 432*4882a593Smuzhiyun 433*4882a593Smuzhiyun pinctrl_i2c3mux: i2c3muxgrp { 434*4882a593Smuzhiyun fsl,pins = < 435*4882a593Smuzhiyun /* PCIe I2C enable */ 436*4882a593Smuzhiyun MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x000b0 437*4882a593Smuzhiyun >; 438*4882a593Smuzhiyun }; 439*4882a593Smuzhiyun 440*4882a593Smuzhiyun pinctrl_j15: j15grp { 441*4882a593Smuzhiyun fsl,pins = < 442*4882a593Smuzhiyun MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 443*4882a593Smuzhiyun MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 444*4882a593Smuzhiyun MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 445*4882a593Smuzhiyun MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 446*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 447*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 448*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 449*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 450*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 451*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 452*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 453*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 454*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 455*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 456*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 457*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 458*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 459*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 460*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 461*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 462*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 463*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 464*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 465*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 466*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 467*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 468*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 469*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 470*4882a593Smuzhiyun >; 471*4882a593Smuzhiyun }; 472*4882a593Smuzhiyun 473*4882a593Smuzhiyun pinctrl_pcie: pciegrp { 474*4882a593Smuzhiyun fsl,pins = < 475*4882a593Smuzhiyun /* PCIe reset */ 476*4882a593Smuzhiyun MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x030b0 477*4882a593Smuzhiyun MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x030b0 478*4882a593Smuzhiyun >; 479*4882a593Smuzhiyun }; 480*4882a593Smuzhiyun 481*4882a593Smuzhiyun pinctrl_pwm1: pwm1grp { 482*4882a593Smuzhiyun fsl,pins = < 483*4882a593Smuzhiyun MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x030b1 484*4882a593Smuzhiyun >; 485*4882a593Smuzhiyun }; 486*4882a593Smuzhiyun 487*4882a593Smuzhiyun pinctrl_pwm3: pwm3grp { 488*4882a593Smuzhiyun fsl,pins = < 489*4882a593Smuzhiyun MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x030b1 490*4882a593Smuzhiyun >; 491*4882a593Smuzhiyun }; 492*4882a593Smuzhiyun 493*4882a593Smuzhiyun pinctrl_pwm4: pwm4grp { 494*4882a593Smuzhiyun fsl,pins = < 495*4882a593Smuzhiyun MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x030b1 496*4882a593Smuzhiyun >; 497*4882a593Smuzhiyun }; 498*4882a593Smuzhiyun 499*4882a593Smuzhiyun pinctrl_rv4162: rv4162grp { 500*4882a593Smuzhiyun fsl,pins = < 501*4882a593Smuzhiyun MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 502*4882a593Smuzhiyun >; 503*4882a593Smuzhiyun }; 504*4882a593Smuzhiyun 505*4882a593Smuzhiyun pinctrl_sgtl5000: sgtl5000grp { 506*4882a593Smuzhiyun fsl,pins = < 507*4882a593Smuzhiyun MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 508*4882a593Smuzhiyun MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x130b0 509*4882a593Smuzhiyun MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x130b0 510*4882a593Smuzhiyun MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x130b0 511*4882a593Smuzhiyun >; 512*4882a593Smuzhiyun }; 513*4882a593Smuzhiyun 514*4882a593Smuzhiyun pinctrl_uart1: uart1grp { 515*4882a593Smuzhiyun fsl,pins = < 516*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 517*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 518*4882a593Smuzhiyun >; 519*4882a593Smuzhiyun }; 520*4882a593Smuzhiyun 521*4882a593Smuzhiyun pinctrl_uart2: uart2grp { 522*4882a593Smuzhiyun fsl,pins = < 523*4882a593Smuzhiyun MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 524*4882a593Smuzhiyun MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 525*4882a593Smuzhiyun >; 526*4882a593Smuzhiyun }; 527*4882a593Smuzhiyun 528*4882a593Smuzhiyun pinctrl_uart3: uart3grp { 529*4882a593Smuzhiyun fsl,pins = < 530*4882a593Smuzhiyun MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 531*4882a593Smuzhiyun MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 532*4882a593Smuzhiyun MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 533*4882a593Smuzhiyun MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 534*4882a593Smuzhiyun >; 535*4882a593Smuzhiyun }; 536*4882a593Smuzhiyun 537*4882a593Smuzhiyun pinctrl_usbh1: usbh1grp { 538*4882a593Smuzhiyun fsl,pins = < 539*4882a593Smuzhiyun MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0 540*4882a593Smuzhiyun >; 541*4882a593Smuzhiyun }; 542*4882a593Smuzhiyun 543*4882a593Smuzhiyun pinctrl_usbotg: usbotggrp { 544*4882a593Smuzhiyun fsl,pins = < 545*4882a593Smuzhiyun MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 546*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 547*4882a593Smuzhiyun /* power enable, high active */ 548*4882a593Smuzhiyun MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0 549*4882a593Smuzhiyun >; 550*4882a593Smuzhiyun }; 551*4882a593Smuzhiyun 552*4882a593Smuzhiyun pinctrl_usdhc2: usdhc2grp { 553*4882a593Smuzhiyun fsl,pins = < 554*4882a593Smuzhiyun MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 555*4882a593Smuzhiyun MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 556*4882a593Smuzhiyun MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 557*4882a593Smuzhiyun MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 558*4882a593Smuzhiyun MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 559*4882a593Smuzhiyun MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 560*4882a593Smuzhiyun >; 561*4882a593Smuzhiyun }; 562*4882a593Smuzhiyun 563*4882a593Smuzhiyun pinctrl_usdhc3: usdhc3grp { 564*4882a593Smuzhiyun fsl,pins = < 565*4882a593Smuzhiyun MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071 566*4882a593Smuzhiyun MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17071 567*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17071 568*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17071 569*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17071 570*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17071 571*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 572*4882a593Smuzhiyun >; 573*4882a593Smuzhiyun }; 574*4882a593Smuzhiyun 575*4882a593Smuzhiyun pinctrl_usdhc4: usdhc4grp { 576*4882a593Smuzhiyun fsl,pins = < 577*4882a593Smuzhiyun MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 578*4882a593Smuzhiyun MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 579*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 580*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 581*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 582*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 583*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 584*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 585*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 586*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 587*4882a593Smuzhiyun >; 588*4882a593Smuzhiyun }; 589*4882a593Smuzhiyun 590*4882a593Smuzhiyun pinctrl_wlan_vmmc: wlan-vmmcgrp { 591*4882a593Smuzhiyun fsl,pins = < 592*4882a593Smuzhiyun MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x100b0 593*4882a593Smuzhiyun MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x030b0 594*4882a593Smuzhiyun MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x030b0 595*4882a593Smuzhiyun MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 596*4882a593Smuzhiyun >; 597*4882a593Smuzhiyun }; 598*4882a593Smuzhiyun}; 599*4882a593Smuzhiyun 600*4882a593Smuzhiyun&ipu1_di0_disp0 { 601*4882a593Smuzhiyun remote-endpoint = <&lcd_display_in>; 602*4882a593Smuzhiyun}; 603*4882a593Smuzhiyun 604*4882a593Smuzhiyun&ldb { 605*4882a593Smuzhiyun status = "okay"; 606*4882a593Smuzhiyun 607*4882a593Smuzhiyun lvds-channel@0 { 608*4882a593Smuzhiyun status = "okay"; 609*4882a593Smuzhiyun 610*4882a593Smuzhiyun port@4 { 611*4882a593Smuzhiyun reg = <4>; 612*4882a593Smuzhiyun 613*4882a593Smuzhiyun lvds0_out: endpoint { 614*4882a593Smuzhiyun remote-endpoint = <&panel_in_lvds0>; 615*4882a593Smuzhiyun }; 616*4882a593Smuzhiyun }; 617*4882a593Smuzhiyun }; 618*4882a593Smuzhiyun 619*4882a593Smuzhiyun lvds-channel@1 { 620*4882a593Smuzhiyun fsl,data-mapping = "spwg"; 621*4882a593Smuzhiyun fsl,data-width = <18>; 622*4882a593Smuzhiyun status = "okay"; 623*4882a593Smuzhiyun 624*4882a593Smuzhiyun port@4 { 625*4882a593Smuzhiyun reg = <4>; 626*4882a593Smuzhiyun 627*4882a593Smuzhiyun lvds1_out: endpoint { 628*4882a593Smuzhiyun remote-endpoint = <&panel_in_lvds1>; 629*4882a593Smuzhiyun }; 630*4882a593Smuzhiyun }; 631*4882a593Smuzhiyun }; 632*4882a593Smuzhiyun}; 633*4882a593Smuzhiyun 634*4882a593Smuzhiyun&pcie { 635*4882a593Smuzhiyun pinctrl-names = "default"; 636*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pcie>; 637*4882a593Smuzhiyun reset-gpio = <&gpio3 0 GPIO_ACTIVE_LOW>; 638*4882a593Smuzhiyun status = "okay"; 639*4882a593Smuzhiyun}; 640*4882a593Smuzhiyun 641*4882a593Smuzhiyun&pwm1 { 642*4882a593Smuzhiyun #pwm-cells = <2>; 643*4882a593Smuzhiyun pinctrl-names = "default"; 644*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pwm1>; 645*4882a593Smuzhiyun status = "okay"; 646*4882a593Smuzhiyun}; 647*4882a593Smuzhiyun 648*4882a593Smuzhiyun&pwm3 { 649*4882a593Smuzhiyun pinctrl-names = "default"; 650*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pwm3>; 651*4882a593Smuzhiyun status = "okay"; 652*4882a593Smuzhiyun}; 653*4882a593Smuzhiyun 654*4882a593Smuzhiyun&pwm4 { 655*4882a593Smuzhiyun #pwm-cells = <2>; 656*4882a593Smuzhiyun pinctrl-names = "default"; 657*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pwm4>; 658*4882a593Smuzhiyun status = "okay"; 659*4882a593Smuzhiyun}; 660*4882a593Smuzhiyun 661*4882a593Smuzhiyun&ssi1 { 662*4882a593Smuzhiyun status = "okay"; 663*4882a593Smuzhiyun}; 664*4882a593Smuzhiyun 665*4882a593Smuzhiyun&uart1 { 666*4882a593Smuzhiyun pinctrl-names = "default"; 667*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart1>; 668*4882a593Smuzhiyun status = "okay"; 669*4882a593Smuzhiyun}; 670*4882a593Smuzhiyun 671*4882a593Smuzhiyun&uart2 { 672*4882a593Smuzhiyun pinctrl-names = "default"; 673*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart2>; 674*4882a593Smuzhiyun status = "okay"; 675*4882a593Smuzhiyun}; 676*4882a593Smuzhiyun 677*4882a593Smuzhiyun&uart3 { 678*4882a593Smuzhiyun pinctrl-names = "default"; 679*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart3>; 680*4882a593Smuzhiyun uart-has-rtscts; 681*4882a593Smuzhiyun status = "okay"; 682*4882a593Smuzhiyun}; 683*4882a593Smuzhiyun 684*4882a593Smuzhiyun&usbh1 { 685*4882a593Smuzhiyun vbus-supply = <®_usb_h1_vbus>; 686*4882a593Smuzhiyun status = "okay"; 687*4882a593Smuzhiyun}; 688*4882a593Smuzhiyun 689*4882a593Smuzhiyun&usbotg { 690*4882a593Smuzhiyun vbus-supply = <®_usb_otg_vbus>; 691*4882a593Smuzhiyun pinctrl-names = "default"; 692*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usbotg>; 693*4882a593Smuzhiyun disable-over-current; 694*4882a593Smuzhiyun status = "okay"; 695*4882a593Smuzhiyun}; 696*4882a593Smuzhiyun 697*4882a593Smuzhiyun&usdhc2 { 698*4882a593Smuzhiyun pinctrl-names = "default"; 699*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc2>; 700*4882a593Smuzhiyun bus-width = <4>; 701*4882a593Smuzhiyun non-removable; 702*4882a593Smuzhiyun vmmc-supply = <®_wlan_vmmc>; 703*4882a593Smuzhiyun cap-power-off-card; 704*4882a593Smuzhiyun keep-power-in-suspend; 705*4882a593Smuzhiyun status = "okay"; 706*4882a593Smuzhiyun 707*4882a593Smuzhiyun #address-cells = <1>; 708*4882a593Smuzhiyun #size-cells = <0>; 709*4882a593Smuzhiyun wlcore: wlcore@2 { 710*4882a593Smuzhiyun compatible = "ti,wl1271"; 711*4882a593Smuzhiyun reg = <2>; 712*4882a593Smuzhiyun interrupt-parent = <&gpio6>; 713*4882a593Smuzhiyun interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; 714*4882a593Smuzhiyun ref-clock-frequency = <38400000>; 715*4882a593Smuzhiyun }; 716*4882a593Smuzhiyun}; 717*4882a593Smuzhiyun 718*4882a593Smuzhiyun&usdhc3 { 719*4882a593Smuzhiyun pinctrl-names = "default"; 720*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc3>; 721*4882a593Smuzhiyun cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; 722*4882a593Smuzhiyun bus-width = <4>; 723*4882a593Smuzhiyun vmmc-supply = <®_3p3v>; 724*4882a593Smuzhiyun status = "okay"; 725*4882a593Smuzhiyun}; 726*4882a593Smuzhiyun 727*4882a593Smuzhiyun&usdhc4 { 728*4882a593Smuzhiyun pinctrl-names = "default"; 729*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc4>; 730*4882a593Smuzhiyun bus-width = <8>; 731*4882a593Smuzhiyun non-removable; 732*4882a593Smuzhiyun vmmc-supply = <®_1p8v>; 733*4882a593Smuzhiyun keep-power-in-suspend; 734*4882a593Smuzhiyun status = "okay"; 735*4882a593Smuzhiyun}; 736