1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright 2017 Gateworks Corporation 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This file is dual-licensed: you can use it either under the terms 5*4882a593Smuzhiyun * of the GPL or the X11 license, at your option. Note that this dual 6*4882a593Smuzhiyun * licensing only applies to this file, and not this project as a 7*4882a593Smuzhiyun * whole. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * a) This file is free software; you can redistribute it and/or 10*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License as 11*4882a593Smuzhiyun * published by the Free Software Foundation; either version 2 of 12*4882a593Smuzhiyun * the License, or (at your option) any later version. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * This file is distributed in the hope that it will be useful, 15*4882a593Smuzhiyun * but WITHOUT ANY WARRANTY; without even the implied warranty of 16*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17*4882a593Smuzhiyun * GNU General Public License for more details. 18*4882a593Smuzhiyun * 19*4882a593Smuzhiyun * You should have received a copy of the GNU General Public 20*4882a593Smuzhiyun * License along with this file; if not, write to the Free 21*4882a593Smuzhiyun * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 22*4882a593Smuzhiyun * MA 02110-1301 USA 23*4882a593Smuzhiyun * 24*4882a593Smuzhiyun * Or, alternatively, 25*4882a593Smuzhiyun * 26*4882a593Smuzhiyun * b) Permission is hereby granted, free of charge, to any person 27*4882a593Smuzhiyun * obtaining a copy of this software and associated documentation 28*4882a593Smuzhiyun * files (the "Software"), to deal in the Software without 29*4882a593Smuzhiyun * restriction, including without limitation the rights to use, 30*4882a593Smuzhiyun * copy, modify, merge, publish, distribute, sublicense, and/or 31*4882a593Smuzhiyun * sell copies of the Software, and to permit persons to whom the 32*4882a593Smuzhiyun * Software is furnished to do so, subject to the following 33*4882a593Smuzhiyun * conditions: 34*4882a593Smuzhiyun * 35*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be 36*4882a593Smuzhiyun * included in all copies or substantial portions of the Software. 37*4882a593Smuzhiyun * 38*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 39*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 40*4882a593Smuzhiyun * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 41*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 42*4882a593Smuzhiyun * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 43*4882a593Smuzhiyun * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 44*4882a593Smuzhiyun * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 45*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 46*4882a593Smuzhiyun */ 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 49*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 50*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h> 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun/ { 53*4882a593Smuzhiyun /* these are used by bootloader for disabling nodes */ 54*4882a593Smuzhiyun aliases { 55*4882a593Smuzhiyun led0 = &led0; 56*4882a593Smuzhiyun led1 = &led1; 57*4882a593Smuzhiyun led2 = &led2; 58*4882a593Smuzhiyun ssi0 = &ssi1; 59*4882a593Smuzhiyun usb0 = &usbh1; 60*4882a593Smuzhiyun usb1 = &usbotg; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun chosen { 64*4882a593Smuzhiyun stdout-path = &uart2; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun backlight-display { 68*4882a593Smuzhiyun compatible = "pwm-backlight"; 69*4882a593Smuzhiyun pwms = <&pwm4 0 5000000>; 70*4882a593Smuzhiyun brightness-levels = < 71*4882a593Smuzhiyun 0 1 2 3 4 5 6 7 8 9 72*4882a593Smuzhiyun 10 11 12 13 14 15 16 17 18 19 73*4882a593Smuzhiyun 20 21 22 23 24 25 26 27 28 29 74*4882a593Smuzhiyun 30 31 32 33 34 35 36 37 38 39 75*4882a593Smuzhiyun 40 41 42 43 44 45 46 47 48 49 76*4882a593Smuzhiyun 50 51 52 53 54 55 56 57 58 59 77*4882a593Smuzhiyun 60 61 62 63 64 65 66 67 68 69 78*4882a593Smuzhiyun 70 71 72 73 74 75 76 77 78 79 79*4882a593Smuzhiyun 80 81 82 83 84 85 86 87 88 89 80*4882a593Smuzhiyun 90 91 92 93 94 95 96 97 98 99 81*4882a593Smuzhiyun 100 82*4882a593Smuzhiyun >; 83*4882a593Smuzhiyun default-brightness-level = <100>; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun backlight-keypad { 87*4882a593Smuzhiyun compatible = "gpio-backlight"; 88*4882a593Smuzhiyun gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; 89*4882a593Smuzhiyun default-on; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun gpio-keys { 93*4882a593Smuzhiyun compatible = "gpio-keys"; 94*4882a593Smuzhiyun #address-cells = <1>; 95*4882a593Smuzhiyun #size-cells = <0>; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun user-pb { 98*4882a593Smuzhiyun label = "user_pb"; 99*4882a593Smuzhiyun gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; 100*4882a593Smuzhiyun linux,code = <BTN_0>; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun user-pb1x { 104*4882a593Smuzhiyun label = "user_pb1x"; 105*4882a593Smuzhiyun linux,code = <BTN_1>; 106*4882a593Smuzhiyun interrupt-parent = <&gsc>; 107*4882a593Smuzhiyun interrupts = <0>; 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun key-erased { 111*4882a593Smuzhiyun label = "key-erased"; 112*4882a593Smuzhiyun linux,code = <BTN_2>; 113*4882a593Smuzhiyun interrupt-parent = <&gsc>; 114*4882a593Smuzhiyun interrupts = <1>; 115*4882a593Smuzhiyun }; 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun eeprom-wp { 118*4882a593Smuzhiyun label = "eeprom_wp"; 119*4882a593Smuzhiyun linux,code = <BTN_3>; 120*4882a593Smuzhiyun interrupt-parent = <&gsc>; 121*4882a593Smuzhiyun interrupts = <2>; 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun tamper { 125*4882a593Smuzhiyun label = "tamper"; 126*4882a593Smuzhiyun linux,code = <BTN_4>; 127*4882a593Smuzhiyun interrupt-parent = <&gsc>; 128*4882a593Smuzhiyun interrupts = <5>; 129*4882a593Smuzhiyun }; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun switch-hold { 132*4882a593Smuzhiyun label = "switch_hold"; 133*4882a593Smuzhiyun linux,code = <BTN_5>; 134*4882a593Smuzhiyun interrupt-parent = <&gsc>; 135*4882a593Smuzhiyun interrupts = <7>; 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun }; 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun leds { 140*4882a593Smuzhiyun compatible = "gpio-leds"; 141*4882a593Smuzhiyun pinctrl-names = "default"; 142*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_gpio_leds>; 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun led0: user1 { 145*4882a593Smuzhiyun label = "user1"; 146*4882a593Smuzhiyun gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ 147*4882a593Smuzhiyun default-state = "on"; 148*4882a593Smuzhiyun linux,default-trigger = "heartbeat"; 149*4882a593Smuzhiyun }; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun led1: user2 { 152*4882a593Smuzhiyun label = "user2"; 153*4882a593Smuzhiyun gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ 154*4882a593Smuzhiyun default-state = "off"; 155*4882a593Smuzhiyun }; 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun led2: user3 { 158*4882a593Smuzhiyun label = "user3"; 159*4882a593Smuzhiyun gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ 160*4882a593Smuzhiyun default-state = "off"; 161*4882a593Smuzhiyun }; 162*4882a593Smuzhiyun }; 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun memory@10000000 { 165*4882a593Smuzhiyun device_type = "memory"; 166*4882a593Smuzhiyun reg = <0x10000000 0x40000000>; 167*4882a593Smuzhiyun }; 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun pps { 170*4882a593Smuzhiyun compatible = "pps-gpio"; 171*4882a593Smuzhiyun pinctrl-names = "default"; 172*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pps>; 173*4882a593Smuzhiyun gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 174*4882a593Smuzhiyun }; 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun reg_2p5v: regulator-2p5v { 177*4882a593Smuzhiyun compatible = "regulator-fixed"; 178*4882a593Smuzhiyun regulator-name = "2P5V"; 179*4882a593Smuzhiyun regulator-min-microvolt = <2500000>; 180*4882a593Smuzhiyun regulator-max-microvolt = <2500000>; 181*4882a593Smuzhiyun regulator-always-on; 182*4882a593Smuzhiyun }; 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun reg_3p3v: regulator-3p3v { 185*4882a593Smuzhiyun compatible = "regulator-fixed"; 186*4882a593Smuzhiyun regulator-name = "3P3V"; 187*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 188*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 189*4882a593Smuzhiyun regulator-always-on; 190*4882a593Smuzhiyun }; 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun reg_5p0v: regulator-5p0v { 193*4882a593Smuzhiyun compatible = "regulator-fixed"; 194*4882a593Smuzhiyun regulator-name = "5P0V"; 195*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 196*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 197*4882a593Smuzhiyun regulator-always-on; 198*4882a593Smuzhiyun }; 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun reg_12p0v: regulator-12p0v { 201*4882a593Smuzhiyun compatible = "regulator-fixed"; 202*4882a593Smuzhiyun regulator-name = "12P0V"; 203*4882a593Smuzhiyun regulator-min-microvolt = <12000000>; 204*4882a593Smuzhiyun regulator-max-microvolt = <12000000>; 205*4882a593Smuzhiyun gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; 206*4882a593Smuzhiyun enable-active-high; 207*4882a593Smuzhiyun }; 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun reg_1p4v: regulator-vddsoc { 210*4882a593Smuzhiyun compatible = "regulator-fixed"; 211*4882a593Smuzhiyun regulator-name = "vdd_soc"; 212*4882a593Smuzhiyun regulator-min-microvolt = <1400000>; 213*4882a593Smuzhiyun regulator-max-microvolt = <1400000>; 214*4882a593Smuzhiyun regulator-always-on; 215*4882a593Smuzhiyun }; 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun reg_usb_h1_vbus: regulator-usb-h1-vbus { 218*4882a593Smuzhiyun compatible = "regulator-fixed"; 219*4882a593Smuzhiyun regulator-name = "usb_h1_vbus"; 220*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 221*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 222*4882a593Smuzhiyun regulator-always-on; 223*4882a593Smuzhiyun }; 224*4882a593Smuzhiyun 225*4882a593Smuzhiyun reg_usb_otg_vbus: regulator-usb-otg-vbus { 226*4882a593Smuzhiyun compatible = "regulator-fixed"; 227*4882a593Smuzhiyun regulator-name = "usb_otg_vbus"; 228*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 229*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 230*4882a593Smuzhiyun gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 231*4882a593Smuzhiyun enable-active-high; 232*4882a593Smuzhiyun }; 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun sound { 235*4882a593Smuzhiyun compatible = "fsl,imx6q-ventana-sgtl5000", 236*4882a593Smuzhiyun "fsl,imx-audio-sgtl5000"; 237*4882a593Smuzhiyun model = "sgtl5000-audio"; 238*4882a593Smuzhiyun ssi-controller = <&ssi1>; 239*4882a593Smuzhiyun audio-codec = <&sgtl5000>; 240*4882a593Smuzhiyun audio-routing = 241*4882a593Smuzhiyun "MIC_IN", "Mic Jack", 242*4882a593Smuzhiyun "Mic Jack", "Mic Bias", 243*4882a593Smuzhiyun "Headphone Jack", "HP_OUT"; 244*4882a593Smuzhiyun mux-int-port = <1>; 245*4882a593Smuzhiyun mux-ext-port = <4>; 246*4882a593Smuzhiyun }; 247*4882a593Smuzhiyun}; 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun&audmux { 250*4882a593Smuzhiyun pinctrl-names = "default"; 251*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_audmux>; 252*4882a593Smuzhiyun status = "okay"; 253*4882a593Smuzhiyun}; 254*4882a593Smuzhiyun 255*4882a593Smuzhiyun&ecspi3 { 256*4882a593Smuzhiyun cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; 257*4882a593Smuzhiyun pinctrl-names = "default"; 258*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_ecspi3>; 259*4882a593Smuzhiyun status = "okay"; 260*4882a593Smuzhiyun}; 261*4882a593Smuzhiyun 262*4882a593Smuzhiyun&can1 { 263*4882a593Smuzhiyun pinctrl-names = "default"; 264*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_flexcan>; 265*4882a593Smuzhiyun status = "okay"; 266*4882a593Smuzhiyun}; 267*4882a593Smuzhiyun 268*4882a593Smuzhiyun&clks { 269*4882a593Smuzhiyun assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 270*4882a593Smuzhiyun <&clks IMX6QDL_CLK_LDB_DI1_SEL>; 271*4882a593Smuzhiyun assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, 272*4882a593Smuzhiyun <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 273*4882a593Smuzhiyun}; 274*4882a593Smuzhiyun 275*4882a593Smuzhiyun&fec { 276*4882a593Smuzhiyun pinctrl-names = "default"; 277*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_enet>; 278*4882a593Smuzhiyun phy-mode = "rgmii-id"; 279*4882a593Smuzhiyun phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; 280*4882a593Smuzhiyun status = "okay"; 281*4882a593Smuzhiyun}; 282*4882a593Smuzhiyun 283*4882a593Smuzhiyun&hdmi { 284*4882a593Smuzhiyun ddc-i2c-bus = <&i2c3>; 285*4882a593Smuzhiyun status = "okay"; 286*4882a593Smuzhiyun}; 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun&i2c1 { 289*4882a593Smuzhiyun clock-frequency = <100000>; 290*4882a593Smuzhiyun pinctrl-names = "default"; 291*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c1>; 292*4882a593Smuzhiyun status = "okay"; 293*4882a593Smuzhiyun 294*4882a593Smuzhiyun gsc: gsc@20 { 295*4882a593Smuzhiyun compatible = "gw,gsc"; 296*4882a593Smuzhiyun reg = <0x20>; 297*4882a593Smuzhiyun interrupt-parent = <&gpio1>; 298*4882a593Smuzhiyun interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 299*4882a593Smuzhiyun interrupt-controller; 300*4882a593Smuzhiyun #interrupt-cells = <1>; 301*4882a593Smuzhiyun #size-cells = <0>; 302*4882a593Smuzhiyun 303*4882a593Smuzhiyun adc { 304*4882a593Smuzhiyun compatible = "gw,gsc-adc"; 305*4882a593Smuzhiyun #address-cells = <1>; 306*4882a593Smuzhiyun #size-cells = <0>; 307*4882a593Smuzhiyun 308*4882a593Smuzhiyun channel@0 { 309*4882a593Smuzhiyun gw,mode = <0>; 310*4882a593Smuzhiyun reg = <0x00>; 311*4882a593Smuzhiyun label = "temp"; 312*4882a593Smuzhiyun }; 313*4882a593Smuzhiyun 314*4882a593Smuzhiyun channel@2 { 315*4882a593Smuzhiyun gw,mode = <1>; 316*4882a593Smuzhiyun reg = <0x02>; 317*4882a593Smuzhiyun label = "vdd_vin"; 318*4882a593Smuzhiyun }; 319*4882a593Smuzhiyun 320*4882a593Smuzhiyun channel@5 { 321*4882a593Smuzhiyun gw,mode = <1>; 322*4882a593Smuzhiyun reg = <0x05>; 323*4882a593Smuzhiyun label = "vdd_3p3"; 324*4882a593Smuzhiyun }; 325*4882a593Smuzhiyun 326*4882a593Smuzhiyun channel@8 { 327*4882a593Smuzhiyun gw,mode = <1>; 328*4882a593Smuzhiyun reg = <0x08>; 329*4882a593Smuzhiyun label = "vdd_bat"; 330*4882a593Smuzhiyun }; 331*4882a593Smuzhiyun 332*4882a593Smuzhiyun channel@b { 333*4882a593Smuzhiyun gw,mode = <1>; 334*4882a593Smuzhiyun reg = <0x0b>; 335*4882a593Smuzhiyun label = "vdd_5p0"; 336*4882a593Smuzhiyun }; 337*4882a593Smuzhiyun 338*4882a593Smuzhiyun channel@e { 339*4882a593Smuzhiyun gw,mode = <1>; 340*4882a593Smuzhiyun reg = <0xe>; 341*4882a593Smuzhiyun label = "vdd_arm"; 342*4882a593Smuzhiyun }; 343*4882a593Smuzhiyun 344*4882a593Smuzhiyun channel@11 { 345*4882a593Smuzhiyun gw,mode = <1>; 346*4882a593Smuzhiyun reg = <0x11>; 347*4882a593Smuzhiyun label = "vdd_soc"; 348*4882a593Smuzhiyun }; 349*4882a593Smuzhiyun 350*4882a593Smuzhiyun channel@14 { 351*4882a593Smuzhiyun gw,mode = <1>; 352*4882a593Smuzhiyun reg = <0x14>; 353*4882a593Smuzhiyun label = "vdd_3p0"; 354*4882a593Smuzhiyun }; 355*4882a593Smuzhiyun 356*4882a593Smuzhiyun channel@17 { 357*4882a593Smuzhiyun gw,mode = <1>; 358*4882a593Smuzhiyun reg = <0x17>; 359*4882a593Smuzhiyun label = "vdd_1p5"; 360*4882a593Smuzhiyun }; 361*4882a593Smuzhiyun 362*4882a593Smuzhiyun channel@1d { 363*4882a593Smuzhiyun gw,mode = <1>; 364*4882a593Smuzhiyun reg = <0x1d>; 365*4882a593Smuzhiyun label = "vdd_1p8"; 366*4882a593Smuzhiyun }; 367*4882a593Smuzhiyun 368*4882a593Smuzhiyun channel@20 { 369*4882a593Smuzhiyun gw,mode = <1>; 370*4882a593Smuzhiyun reg = <0x20>; 371*4882a593Smuzhiyun label = "vdd_an1"; 372*4882a593Smuzhiyun }; 373*4882a593Smuzhiyun 374*4882a593Smuzhiyun channel@23 { 375*4882a593Smuzhiyun gw,mode = <1>; 376*4882a593Smuzhiyun reg = <0x23>; 377*4882a593Smuzhiyun label = "vdd_2p5"; 378*4882a593Smuzhiyun }; 379*4882a593Smuzhiyun 380*4882a593Smuzhiyun channel@26 { 381*4882a593Smuzhiyun gw,mode = <1>; 382*4882a593Smuzhiyun reg = <0x26>; 383*4882a593Smuzhiyun label = "vdd_gps"; 384*4882a593Smuzhiyun }; 385*4882a593Smuzhiyun 386*4882a593Smuzhiyun channel@29 { 387*4882a593Smuzhiyun gw,mode = <1>; 388*4882a593Smuzhiyun reg = <0x29>; 389*4882a593Smuzhiyun label = "vdd_an2"; 390*4882a593Smuzhiyun }; 391*4882a593Smuzhiyun }; 392*4882a593Smuzhiyun }; 393*4882a593Smuzhiyun 394*4882a593Smuzhiyun gsc_gpio: gpio@23 { 395*4882a593Smuzhiyun compatible = "nxp,pca9555"; 396*4882a593Smuzhiyun reg = <0x23>; 397*4882a593Smuzhiyun gpio-controller; 398*4882a593Smuzhiyun #gpio-cells = <2>; 399*4882a593Smuzhiyun interrupt-parent = <&gsc>; 400*4882a593Smuzhiyun interrupts = <4>; 401*4882a593Smuzhiyun }; 402*4882a593Smuzhiyun 403*4882a593Smuzhiyun eeprom1: eeprom@50 { 404*4882a593Smuzhiyun compatible = "atmel,24c02"; 405*4882a593Smuzhiyun reg = <0x50>; 406*4882a593Smuzhiyun pagesize = <16>; 407*4882a593Smuzhiyun }; 408*4882a593Smuzhiyun 409*4882a593Smuzhiyun eeprom2: eeprom@51 { 410*4882a593Smuzhiyun compatible = "atmel,24c02"; 411*4882a593Smuzhiyun reg = <0x51>; 412*4882a593Smuzhiyun pagesize = <16>; 413*4882a593Smuzhiyun }; 414*4882a593Smuzhiyun 415*4882a593Smuzhiyun eeprom3: eeprom@52 { 416*4882a593Smuzhiyun compatible = "atmel,24c02"; 417*4882a593Smuzhiyun reg = <0x52>; 418*4882a593Smuzhiyun pagesize = <16>; 419*4882a593Smuzhiyun }; 420*4882a593Smuzhiyun 421*4882a593Smuzhiyun eeprom4: eeprom@53 { 422*4882a593Smuzhiyun compatible = "atmel,24c02"; 423*4882a593Smuzhiyun reg = <0x53>; 424*4882a593Smuzhiyun pagesize = <16>; 425*4882a593Smuzhiyun }; 426*4882a593Smuzhiyun 427*4882a593Smuzhiyun ds1672: rtc@68 { 428*4882a593Smuzhiyun compatible = "dallas,ds1672"; 429*4882a593Smuzhiyun reg = <0x68>; 430*4882a593Smuzhiyun }; 431*4882a593Smuzhiyun}; 432*4882a593Smuzhiyun 433*4882a593Smuzhiyun&i2c2 { 434*4882a593Smuzhiyun clock-frequency = <100000>; 435*4882a593Smuzhiyun pinctrl-names = "default"; 436*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c2>; 437*4882a593Smuzhiyun status = "okay"; 438*4882a593Smuzhiyun 439*4882a593Smuzhiyun sgtl5000: codec@a { 440*4882a593Smuzhiyun compatible = "fsl,sgtl5000"; 441*4882a593Smuzhiyun reg = <0x0a>; 442*4882a593Smuzhiyun #sound-dai-cells = <0>; 443*4882a593Smuzhiyun clocks = <&clks IMX6QDL_CLK_CKO>; 444*4882a593Smuzhiyun VDDA-supply = <®_1p8v>; 445*4882a593Smuzhiyun VDDIO-supply = <®_3p3v>; 446*4882a593Smuzhiyun }; 447*4882a593Smuzhiyun 448*4882a593Smuzhiyun magn@1c { 449*4882a593Smuzhiyun compatible = "st,lsm9ds1-magn"; 450*4882a593Smuzhiyun reg = <0x1c>; 451*4882a593Smuzhiyun pinctrl-names = "default"; 452*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_mag>; 453*4882a593Smuzhiyun interrupt-parent = <&gpio5>; 454*4882a593Smuzhiyun interrupts = <9 IRQ_TYPE_EDGE_RISING>; 455*4882a593Smuzhiyun }; 456*4882a593Smuzhiyun 457*4882a593Smuzhiyun tca8418: keypad@34 { 458*4882a593Smuzhiyun compatible = "ti,tca8418"; 459*4882a593Smuzhiyun pinctrl-names = "default"; 460*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_keypad>; 461*4882a593Smuzhiyun reg = <0x34>; 462*4882a593Smuzhiyun interrupt-parent = <&gpio5>; 463*4882a593Smuzhiyun interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 464*4882a593Smuzhiyun linux,keymap = < MATRIX_KEY(0x00, 0x01, BTN_0) 465*4882a593Smuzhiyun MATRIX_KEY(0x00, 0x00, BTN_1) 466*4882a593Smuzhiyun MATRIX_KEY(0x01, 0x01, BTN_2) 467*4882a593Smuzhiyun MATRIX_KEY(0x01, 0x00, BTN_3) 468*4882a593Smuzhiyun MATRIX_KEY(0x02, 0x00, BTN_4) 469*4882a593Smuzhiyun MATRIX_KEY(0x00, 0x03, BTN_5) 470*4882a593Smuzhiyun MATRIX_KEY(0x00, 0x02, BTN_6) 471*4882a593Smuzhiyun MATRIX_KEY(0x01, 0x03, BTN_7) 472*4882a593Smuzhiyun MATRIX_KEY(0x01, 0x02, BTN_8) 473*4882a593Smuzhiyun MATRIX_KEY(0x02, 0x02, BTN_9) 474*4882a593Smuzhiyun >; 475*4882a593Smuzhiyun keypad,num-rows = <4>; 476*4882a593Smuzhiyun keypad,num-columns = <4>; 477*4882a593Smuzhiyun }; 478*4882a593Smuzhiyun 479*4882a593Smuzhiyun ltc3676: pmic@3c { 480*4882a593Smuzhiyun compatible = "lltc,ltc3676"; 481*4882a593Smuzhiyun pinctrl-names = "default"; 482*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pmic>; 483*4882a593Smuzhiyun reg = <0x3c>; 484*4882a593Smuzhiyun interrupt-parent = <&gpio1>; 485*4882a593Smuzhiyun interrupts = <8 IRQ_TYPE_EDGE_FALLING>; 486*4882a593Smuzhiyun 487*4882a593Smuzhiyun regulators { 488*4882a593Smuzhiyun /* VDD_DDR (1+R1/R2 = 2.105) */ 489*4882a593Smuzhiyun reg_vdd_ddr: sw2 { 490*4882a593Smuzhiyun regulator-name = "vddddr"; 491*4882a593Smuzhiyun regulator-min-microvolt = <868310>; 492*4882a593Smuzhiyun regulator-max-microvolt = <1684000>; 493*4882a593Smuzhiyun lltc,fb-voltage-divider = <221000 200000>; 494*4882a593Smuzhiyun regulator-ramp-delay = <7000>; 495*4882a593Smuzhiyun regulator-boot-on; 496*4882a593Smuzhiyun regulator-always-on; 497*4882a593Smuzhiyun }; 498*4882a593Smuzhiyun 499*4882a593Smuzhiyun /* VDD_ARM (1+R1/R2 = 1.931) */ 500*4882a593Smuzhiyun reg_vdd_arm: sw3 { 501*4882a593Smuzhiyun regulator-name = "vddarm"; 502*4882a593Smuzhiyun regulator-min-microvolt = <796551>; 503*4882a593Smuzhiyun regulator-max-microvolt = <1544827>; 504*4882a593Smuzhiyun lltc,fb-voltage-divider = <243000 261000>; 505*4882a593Smuzhiyun regulator-ramp-delay = <7000>; 506*4882a593Smuzhiyun regulator-boot-on; 507*4882a593Smuzhiyun regulator-always-on; 508*4882a593Smuzhiyun linux,phandle = <®_vdd_arm>; 509*4882a593Smuzhiyun }; 510*4882a593Smuzhiyun 511*4882a593Smuzhiyun /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */ 512*4882a593Smuzhiyun reg_1p8v: sw4 { 513*4882a593Smuzhiyun regulator-name = "vdd1p8"; 514*4882a593Smuzhiyun regulator-min-microvolt = <1033310>; 515*4882a593Smuzhiyun regulator-max-microvolt = <2004000>; 516*4882a593Smuzhiyun lltc,fb-voltage-divider = <301000 200000>; 517*4882a593Smuzhiyun regulator-ramp-delay = <7000>; 518*4882a593Smuzhiyun regulator-boot-on; 519*4882a593Smuzhiyun regulator-always-on; 520*4882a593Smuzhiyun }; 521*4882a593Smuzhiyun 522*4882a593Smuzhiyun /* VDD_1P0 (1+R1/R2 = 1.39): PCIe/ENET-PHY */ 523*4882a593Smuzhiyun reg_1p0v: ldo2 { 524*4882a593Smuzhiyun regulator-name = "vdd1p0"; 525*4882a593Smuzhiyun regulator-min-microvolt = <950000>; 526*4882a593Smuzhiyun regulator-max-microvolt = <1050000>; 527*4882a593Smuzhiyun lltc,fb-voltage-divider = <78700 200000>; 528*4882a593Smuzhiyun regulator-boot-on; 529*4882a593Smuzhiyun regulator-always-on; 530*4882a593Smuzhiyun }; 531*4882a593Smuzhiyun 532*4882a593Smuzhiyun /* VDD_AUD_1P8: Audio codec */ 533*4882a593Smuzhiyun reg_aud_1p8v: ldo3 { 534*4882a593Smuzhiyun regulator-name = "vdd1p8a"; 535*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 536*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 537*4882a593Smuzhiyun regulator-boot-on; 538*4882a593Smuzhiyun }; 539*4882a593Smuzhiyun 540*4882a593Smuzhiyun /* VDD_HIGH (1+R1/R2 = 4.17) */ 541*4882a593Smuzhiyun reg_3p0v: ldo4 { 542*4882a593Smuzhiyun regulator-name = "vdd3p0"; 543*4882a593Smuzhiyun regulator-min-microvolt = <3023250>; 544*4882a593Smuzhiyun regulator-max-microvolt = <3023250>; 545*4882a593Smuzhiyun lltc,fb-voltage-divider = <634000 200000>; 546*4882a593Smuzhiyun regulator-boot-on; 547*4882a593Smuzhiyun regulator-always-on; 548*4882a593Smuzhiyun }; 549*4882a593Smuzhiyun }; 550*4882a593Smuzhiyun }; 551*4882a593Smuzhiyun 552*4882a593Smuzhiyun imu@6a { 553*4882a593Smuzhiyun compatible = "st,lsm9ds1-imu"; 554*4882a593Smuzhiyun reg = <0x6a>; 555*4882a593Smuzhiyun st,drdy-int-pin = <1>; 556*4882a593Smuzhiyun pinctrl-names = "default"; 557*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_imu>; 558*4882a593Smuzhiyun interrupt-parent = <&gpio5>; 559*4882a593Smuzhiyun interrupts = <6 IRQ_TYPE_LEVEL_HIGH>; 560*4882a593Smuzhiyun }; 561*4882a593Smuzhiyun}; 562*4882a593Smuzhiyun 563*4882a593Smuzhiyun&i2c3 { 564*4882a593Smuzhiyun clock-frequency = <100000>; 565*4882a593Smuzhiyun pinctrl-names = "default"; 566*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c3>; 567*4882a593Smuzhiyun status = "okay"; 568*4882a593Smuzhiyun 569*4882a593Smuzhiyun egalax_ts: touchscreen@4 { 570*4882a593Smuzhiyun compatible = "eeti,egalax_ts"; 571*4882a593Smuzhiyun reg = <0x04>; 572*4882a593Smuzhiyun interrupt-parent = <&gpio5>; 573*4882a593Smuzhiyun interrupts = <12 IRQ_TYPE_EDGE_FALLING>; 574*4882a593Smuzhiyun wakeup-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 575*4882a593Smuzhiyun }; 576*4882a593Smuzhiyun}; 577*4882a593Smuzhiyun 578*4882a593Smuzhiyun&ldb { 579*4882a593Smuzhiyun fsl,dual-channel; 580*4882a593Smuzhiyun status = "okay"; 581*4882a593Smuzhiyun 582*4882a593Smuzhiyun lvds-channel@0 { 583*4882a593Smuzhiyun fsl,data-mapping = "spwg"; 584*4882a593Smuzhiyun fsl,data-width = <18>; 585*4882a593Smuzhiyun status = "okay"; 586*4882a593Smuzhiyun 587*4882a593Smuzhiyun display-timings { 588*4882a593Smuzhiyun native-mode = <&timing0>; 589*4882a593Smuzhiyun timing0: hsd100pxn1 { 590*4882a593Smuzhiyun clock-frequency = <65000000>; 591*4882a593Smuzhiyun hactive = <1024>; 592*4882a593Smuzhiyun vactive = <768>; 593*4882a593Smuzhiyun hback-porch = <220>; 594*4882a593Smuzhiyun hfront-porch = <40>; 595*4882a593Smuzhiyun vback-porch = <21>; 596*4882a593Smuzhiyun vfront-porch = <7>; 597*4882a593Smuzhiyun hsync-len = <60>; 598*4882a593Smuzhiyun vsync-len = <10>; 599*4882a593Smuzhiyun }; 600*4882a593Smuzhiyun }; 601*4882a593Smuzhiyun }; 602*4882a593Smuzhiyun}; 603*4882a593Smuzhiyun 604*4882a593Smuzhiyun&pcie { 605*4882a593Smuzhiyun pinctrl-names = "default"; 606*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pcie>; 607*4882a593Smuzhiyun reset-gpio = <&gpio4 31 GPIO_ACTIVE_LOW>; 608*4882a593Smuzhiyun status = "okay"; 609*4882a593Smuzhiyun}; 610*4882a593Smuzhiyun 611*4882a593Smuzhiyun&pwm2 { 612*4882a593Smuzhiyun pinctrl-names = "default"; 613*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ 614*4882a593Smuzhiyun status = "disabled"; 615*4882a593Smuzhiyun}; 616*4882a593Smuzhiyun 617*4882a593Smuzhiyun&pwm3 { 618*4882a593Smuzhiyun pinctrl-names = "default"; 619*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ 620*4882a593Smuzhiyun status = "disabled"; 621*4882a593Smuzhiyun}; 622*4882a593Smuzhiyun 623*4882a593Smuzhiyun&pwm4 { 624*4882a593Smuzhiyun #pwm-cells = <2>; 625*4882a593Smuzhiyun pinctrl-names = "default"; 626*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pwm4>; 627*4882a593Smuzhiyun status = "okay"; 628*4882a593Smuzhiyun}; 629*4882a593Smuzhiyun 630*4882a593Smuzhiyun&ssi1 { 631*4882a593Smuzhiyun status = "okay"; 632*4882a593Smuzhiyun}; 633*4882a593Smuzhiyun 634*4882a593Smuzhiyun&uart1 { 635*4882a593Smuzhiyun pinctrl-names = "default"; 636*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart1>; 637*4882a593Smuzhiyun uart-has-rtscts; 638*4882a593Smuzhiyun rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; 639*4882a593Smuzhiyun status = "okay"; 640*4882a593Smuzhiyun}; 641*4882a593Smuzhiyun 642*4882a593Smuzhiyun&uart2 { 643*4882a593Smuzhiyun pinctrl-names = "default"; 644*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart2>; 645*4882a593Smuzhiyun status = "okay"; 646*4882a593Smuzhiyun}; 647*4882a593Smuzhiyun 648*4882a593Smuzhiyun&uart5 { 649*4882a593Smuzhiyun pinctrl-names = "default"; 650*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart5>; 651*4882a593Smuzhiyun status = "okay"; 652*4882a593Smuzhiyun}; 653*4882a593Smuzhiyun 654*4882a593Smuzhiyun&usbotg { 655*4882a593Smuzhiyun vbus-supply = <®_usb_otg_vbus>; 656*4882a593Smuzhiyun pinctrl-names = "default"; 657*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usbotg>; 658*4882a593Smuzhiyun disable-over-current; 659*4882a593Smuzhiyun status = "okay"; 660*4882a593Smuzhiyun}; 661*4882a593Smuzhiyun 662*4882a593Smuzhiyun&usbh1 { 663*4882a593Smuzhiyun vbus-supply = <®_usb_h1_vbus>; 664*4882a593Smuzhiyun pinctrl-names = "default"; 665*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usbh1>; 666*4882a593Smuzhiyun status = "okay"; 667*4882a593Smuzhiyun}; 668*4882a593Smuzhiyun 669*4882a593Smuzhiyun&usdhc2 { 670*4882a593Smuzhiyun pinctrl-names = "default"; 671*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc2>; 672*4882a593Smuzhiyun bus-width = <8>; 673*4882a593Smuzhiyun vmmc-supply = <®_3p3v>; 674*4882a593Smuzhiyun non-removable; 675*4882a593Smuzhiyun status = "okay"; 676*4882a593Smuzhiyun}; 677*4882a593Smuzhiyun 678*4882a593Smuzhiyun&usdhc3 { 679*4882a593Smuzhiyun pinctrl-names = "default", "state_100mhz", "state_200mhz"; 680*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc3>; 681*4882a593Smuzhiyun pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 682*4882a593Smuzhiyun pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 683*4882a593Smuzhiyun cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; 684*4882a593Smuzhiyun vmmc-supply = <®_3p3v>; 685*4882a593Smuzhiyun status = "okay"; 686*4882a593Smuzhiyun}; 687*4882a593Smuzhiyun 688*4882a593Smuzhiyun&wdog1 { 689*4882a593Smuzhiyun pinctrl-names = "default"; 690*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_wdog>; 691*4882a593Smuzhiyun fsl,ext-reset-output; 692*4882a593Smuzhiyun}; 693*4882a593Smuzhiyun 694*4882a593Smuzhiyun&iomuxc { 695*4882a593Smuzhiyun pinctrl_audmux: audmuxgrp { 696*4882a593Smuzhiyun fsl,pins = < 697*4882a593Smuzhiyun /* AUD4 */ 698*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 699*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0 700*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 701*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 702*4882a593Smuzhiyun MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ 703*4882a593Smuzhiyun /* AUD6 */ 704*4882a593Smuzhiyun MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x130b0 705*4882a593Smuzhiyun MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x130b0 706*4882a593Smuzhiyun MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x130b0 707*4882a593Smuzhiyun MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x130b0 708*4882a593Smuzhiyun >; 709*4882a593Smuzhiyun }; 710*4882a593Smuzhiyun 711*4882a593Smuzhiyun pinctrl_ecspi3: escpi3grp { 712*4882a593Smuzhiyun fsl,pins = < 713*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 714*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 715*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 716*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1 717*4882a593Smuzhiyun >; 718*4882a593Smuzhiyun }; 719*4882a593Smuzhiyun 720*4882a593Smuzhiyun pinctrl_enet: enetgrp { 721*4882a593Smuzhiyun fsl,pins = < 722*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 723*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 724*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 725*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 726*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 727*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 728*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 729*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 730*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 731*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 732*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 733*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 734*4882a593Smuzhiyun MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 735*4882a593Smuzhiyun MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 736*4882a593Smuzhiyun MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 737*4882a593Smuzhiyun MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 738*4882a593Smuzhiyun MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */ 739*4882a593Smuzhiyun >; 740*4882a593Smuzhiyun }; 741*4882a593Smuzhiyun 742*4882a593Smuzhiyun pinctrl_flexcan: flexcangrp { 743*4882a593Smuzhiyun fsl,pins = < 744*4882a593Smuzhiyun MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 745*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 746*4882a593Smuzhiyun MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ 747*4882a593Smuzhiyun >; 748*4882a593Smuzhiyun }; 749*4882a593Smuzhiyun 750*4882a593Smuzhiyun pinctrl_gpio_leds: gpioledsgrp { 751*4882a593Smuzhiyun fsl,pins = < 752*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 753*4882a593Smuzhiyun MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 754*4882a593Smuzhiyun MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 755*4882a593Smuzhiyun >; 756*4882a593Smuzhiyun }; 757*4882a593Smuzhiyun 758*4882a593Smuzhiyun pinctrl_i2c1: i2c1grp { 759*4882a593Smuzhiyun fsl,pins = < 760*4882a593Smuzhiyun MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 761*4882a593Smuzhiyun MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 762*4882a593Smuzhiyun MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 763*4882a593Smuzhiyun >; 764*4882a593Smuzhiyun }; 765*4882a593Smuzhiyun 766*4882a593Smuzhiyun pinctrl_i2c2: i2c2grp { 767*4882a593Smuzhiyun fsl,pins = < 768*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 769*4882a593Smuzhiyun MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 770*4882a593Smuzhiyun >; 771*4882a593Smuzhiyun }; 772*4882a593Smuzhiyun 773*4882a593Smuzhiyun pinctrl_i2c3: i2c3grp { 774*4882a593Smuzhiyun fsl,pins = < 775*4882a593Smuzhiyun MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 776*4882a593Smuzhiyun MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 777*4882a593Smuzhiyun MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x4001b0b0 /* DIOI2C_DIS# */ 778*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x0001b0b0 /* LVDS_TOUCH_IRQ# */ 779*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x0001b0b0 /* LVDS_BACKEN */ 780*4882a593Smuzhiyun >; 781*4882a593Smuzhiyun }; 782*4882a593Smuzhiyun 783*4882a593Smuzhiyun pinctrl_imu: imugrp { 784*4882a593Smuzhiyun fsl,pins = < 785*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1b0b0 786*4882a593Smuzhiyun >; 787*4882a593Smuzhiyun }; 788*4882a593Smuzhiyun 789*4882a593Smuzhiyun pinctrl_keypad: keypadgrp { 790*4882a593Smuzhiyun fsl,pins = < 791*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x0001b0b0 /* KEYPAD_IRQ# */ 792*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x0001b0b0 /* KEYPAD_LED_EN */ 793*4882a593Smuzhiyun >; 794*4882a593Smuzhiyun }; 795*4882a593Smuzhiyun 796*4882a593Smuzhiyun pinctrl_mag: maggrp { 797*4882a593Smuzhiyun fsl,pins = < 798*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b0 799*4882a593Smuzhiyun >; 800*4882a593Smuzhiyun }; 801*4882a593Smuzhiyun 802*4882a593Smuzhiyun pinctrl_pcie: pciegrp { 803*4882a593Smuzhiyun fsl,pins = < 804*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b0 /* PCI_RST# */ 805*4882a593Smuzhiyun MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b0 /* PCIESKT_WDIS# */ 806*4882a593Smuzhiyun >; 807*4882a593Smuzhiyun }; 808*4882a593Smuzhiyun 809*4882a593Smuzhiyun pinctrl_pmic: pmicgrp { 810*4882a593Smuzhiyun fsl,pins = < 811*4882a593Smuzhiyun MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ 812*4882a593Smuzhiyun >; 813*4882a593Smuzhiyun }; 814*4882a593Smuzhiyun 815*4882a593Smuzhiyun pinctrl_pps: ppsgrp { 816*4882a593Smuzhiyun fsl,pins = < 817*4882a593Smuzhiyun MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 818*4882a593Smuzhiyun >; 819*4882a593Smuzhiyun }; 820*4882a593Smuzhiyun 821*4882a593Smuzhiyun pinctrl_pwm2: pwm2grp { 822*4882a593Smuzhiyun fsl,pins = < 823*4882a593Smuzhiyun MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 824*4882a593Smuzhiyun >; 825*4882a593Smuzhiyun }; 826*4882a593Smuzhiyun 827*4882a593Smuzhiyun pinctrl_pwm3: pwm3grp { 828*4882a593Smuzhiyun fsl,pins = < 829*4882a593Smuzhiyun MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 830*4882a593Smuzhiyun >; 831*4882a593Smuzhiyun }; 832*4882a593Smuzhiyun 833*4882a593Smuzhiyun pinctrl_pwm4: pwm4grp { 834*4882a593Smuzhiyun fsl,pins = < 835*4882a593Smuzhiyun MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 836*4882a593Smuzhiyun >; 837*4882a593Smuzhiyun }; 838*4882a593Smuzhiyun 839*4882a593Smuzhiyun pinctrl_uart1: uart1grp { 840*4882a593Smuzhiyun fsl,pins = < 841*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 842*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 843*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ 844*4882a593Smuzhiyun >; 845*4882a593Smuzhiyun }; 846*4882a593Smuzhiyun 847*4882a593Smuzhiyun pinctrl_uart2: uart2grp { 848*4882a593Smuzhiyun fsl,pins = < 849*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 850*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 851*4882a593Smuzhiyun >; 852*4882a593Smuzhiyun }; 853*4882a593Smuzhiyun 854*4882a593Smuzhiyun pinctrl_uart5: uart5grp { 855*4882a593Smuzhiyun fsl,pins = < 856*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 857*4882a593Smuzhiyun MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 858*4882a593Smuzhiyun >; 859*4882a593Smuzhiyun }; 860*4882a593Smuzhiyun 861*4882a593Smuzhiyun pinctrl_usbh1: usbh1grp { 862*4882a593Smuzhiyun fsl,pins = < 863*4882a593Smuzhiyun MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* USBHUB_RST# */ 864*4882a593Smuzhiyun >; 865*4882a593Smuzhiyun }; 866*4882a593Smuzhiyun 867*4882a593Smuzhiyun pinctrl_usbotg: usbotggrp { 868*4882a593Smuzhiyun fsl,pins = < 869*4882a593Smuzhiyun MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 870*4882a593Smuzhiyun MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ 871*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ 872*4882a593Smuzhiyun >; 873*4882a593Smuzhiyun }; 874*4882a593Smuzhiyun 875*4882a593Smuzhiyun pinctrl_usdhc2: usdhc2grp { 876*4882a593Smuzhiyun fsl,pins = < 877*4882a593Smuzhiyun MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 878*4882a593Smuzhiyun MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 879*4882a593Smuzhiyun MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 880*4882a593Smuzhiyun MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 881*4882a593Smuzhiyun MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 882*4882a593Smuzhiyun MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 883*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x170f9 884*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x170f9 885*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x170f9 886*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x170f9 887*4882a593Smuzhiyun >; 888*4882a593Smuzhiyun }; 889*4882a593Smuzhiyun 890*4882a593Smuzhiyun pinctrl_usdhc3: usdhc3grp { 891*4882a593Smuzhiyun fsl,pins = < 892*4882a593Smuzhiyun MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 893*4882a593Smuzhiyun MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 894*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 895*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 896*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 897*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 898*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ 899*4882a593Smuzhiyun MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 900*4882a593Smuzhiyun >; 901*4882a593Smuzhiyun }; 902*4882a593Smuzhiyun 903*4882a593Smuzhiyun pinctrl_usdhc3_100mhz: usdhc3grp100mhz { 904*4882a593Smuzhiyun fsl,pins = < 905*4882a593Smuzhiyun MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 906*4882a593Smuzhiyun MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 907*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 908*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 909*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 910*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 911*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ 912*4882a593Smuzhiyun MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 913*4882a593Smuzhiyun >; 914*4882a593Smuzhiyun }; 915*4882a593Smuzhiyun 916*4882a593Smuzhiyun pinctrl_usdhc3_200mhz: usdhc3grp200mhz { 917*4882a593Smuzhiyun fsl,pins = < 918*4882a593Smuzhiyun MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 919*4882a593Smuzhiyun MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 920*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 921*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 922*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 923*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 924*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ 925*4882a593Smuzhiyun MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 926*4882a593Smuzhiyun >; 927*4882a593Smuzhiyun }; 928*4882a593Smuzhiyun 929*4882a593Smuzhiyun pinctrl_wdog: wdoggrp { 930*4882a593Smuzhiyun fsl,pins = < 931*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 932*4882a593Smuzhiyun >; 933*4882a593Smuzhiyun }; 934*4882a593Smuzhiyun}; 935