1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright 2014 Gateworks Corporation 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 7*4882a593Smuzhiyun#include <dt-bindings/input/linux-event-codes.h> 8*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun /* these are used by bootloader for disabling nodes */ 12*4882a593Smuzhiyun aliases { 13*4882a593Smuzhiyun led0 = &led0; 14*4882a593Smuzhiyun led1 = &led1; 15*4882a593Smuzhiyun led2 = &led2; 16*4882a593Smuzhiyun nand = &gpmi; 17*4882a593Smuzhiyun usb0 = &usbh1; 18*4882a593Smuzhiyun usb1 = &usbotg; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun chosen { 22*4882a593Smuzhiyun bootargs = "console=ttymxc1,115200"; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun gpio-keys { 26*4882a593Smuzhiyun compatible = "gpio-keys"; 27*4882a593Smuzhiyun #address-cells = <1>; 28*4882a593Smuzhiyun #size-cells = <0>; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun user-pb { 31*4882a593Smuzhiyun label = "user_pb"; 32*4882a593Smuzhiyun gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; 33*4882a593Smuzhiyun linux,code = <BTN_0>; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun user-pb1x { 37*4882a593Smuzhiyun label = "user_pb1x"; 38*4882a593Smuzhiyun linux,code = <BTN_1>; 39*4882a593Smuzhiyun interrupt-parent = <&gsc>; 40*4882a593Smuzhiyun interrupts = <0>; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun key-erased { 44*4882a593Smuzhiyun label = "key-erased"; 45*4882a593Smuzhiyun linux,code = <BTN_2>; 46*4882a593Smuzhiyun interrupt-parent = <&gsc>; 47*4882a593Smuzhiyun interrupts = <1>; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun eeprom-wp { 51*4882a593Smuzhiyun label = "eeprom_wp"; 52*4882a593Smuzhiyun linux,code = <BTN_3>; 53*4882a593Smuzhiyun interrupt-parent = <&gsc>; 54*4882a593Smuzhiyun interrupts = <2>; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun tamper { 58*4882a593Smuzhiyun label = "tamper"; 59*4882a593Smuzhiyun linux,code = <BTN_4>; 60*4882a593Smuzhiyun interrupt-parent = <&gsc>; 61*4882a593Smuzhiyun interrupts = <5>; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun switch-hold { 65*4882a593Smuzhiyun label = "switch_hold"; 66*4882a593Smuzhiyun linux,code = <BTN_5>; 67*4882a593Smuzhiyun interrupt-parent = <&gsc>; 68*4882a593Smuzhiyun interrupts = <7>; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun leds { 73*4882a593Smuzhiyun compatible = "gpio-leds"; 74*4882a593Smuzhiyun pinctrl-names = "default"; 75*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_gpio_leds>; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun led0: user1 { 78*4882a593Smuzhiyun label = "user1"; 79*4882a593Smuzhiyun gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ 80*4882a593Smuzhiyun default-state = "on"; 81*4882a593Smuzhiyun linux,default-trigger = "heartbeat"; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun led1: user2 { 85*4882a593Smuzhiyun label = "user2"; 86*4882a593Smuzhiyun gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ 87*4882a593Smuzhiyun default-state = "off"; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun led2: user3 { 91*4882a593Smuzhiyun label = "user3"; 92*4882a593Smuzhiyun gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ 93*4882a593Smuzhiyun default-state = "off"; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun memory@10000000 { 98*4882a593Smuzhiyun device_type = "memory"; 99*4882a593Smuzhiyun reg = <0x10000000 0x20000000>; 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun reg_1p0v: regulator-1p0v { 103*4882a593Smuzhiyun compatible = "regulator-fixed"; 104*4882a593Smuzhiyun regulator-name = "1P0V"; 105*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 106*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 107*4882a593Smuzhiyun regulator-always-on; 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun reg_3p3v: regulator-3p3v { 111*4882a593Smuzhiyun compatible = "regulator-fixed"; 112*4882a593Smuzhiyun regulator-name = "3P3V"; 113*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 114*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 115*4882a593Smuzhiyun regulator-always-on; 116*4882a593Smuzhiyun }; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun reg_5p0v: regulator-5p0v { 119*4882a593Smuzhiyun compatible = "regulator-fixed"; 120*4882a593Smuzhiyun regulator-name = "5P0V"; 121*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 122*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 123*4882a593Smuzhiyun regulator-always-on; 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun}; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun&gpmi { 128*4882a593Smuzhiyun pinctrl-names = "default"; 129*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_gpmi_nand>; 130*4882a593Smuzhiyun status = "okay"; 131*4882a593Smuzhiyun}; 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun&hdmi { 134*4882a593Smuzhiyun ddc-i2c-bus = <&i2c3>; 135*4882a593Smuzhiyun status = "okay"; 136*4882a593Smuzhiyun}; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun&i2c1 { 139*4882a593Smuzhiyun clock-frequency = <100000>; 140*4882a593Smuzhiyun pinctrl-names = "default"; 141*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c1>; 142*4882a593Smuzhiyun status = "okay"; 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun gsc: gsc@20 { 145*4882a593Smuzhiyun compatible = "gw,gsc"; 146*4882a593Smuzhiyun reg = <0x20>; 147*4882a593Smuzhiyun interrupt-parent = <&gpio1>; 148*4882a593Smuzhiyun interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 149*4882a593Smuzhiyun interrupt-controller; 150*4882a593Smuzhiyun #interrupt-cells = <1>; 151*4882a593Smuzhiyun #size-cells = <0>; 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun adc { 154*4882a593Smuzhiyun compatible = "gw,gsc-adc"; 155*4882a593Smuzhiyun #address-cells = <1>; 156*4882a593Smuzhiyun #size-cells = <0>; 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun channel@0 { 159*4882a593Smuzhiyun gw,mode = <0>; 160*4882a593Smuzhiyun reg = <0x00>; 161*4882a593Smuzhiyun label = "temp"; 162*4882a593Smuzhiyun }; 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun channel@2 { 165*4882a593Smuzhiyun gw,mode = <1>; 166*4882a593Smuzhiyun reg = <0x02>; 167*4882a593Smuzhiyun label = "vdd_vin"; 168*4882a593Smuzhiyun }; 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun channel@5 { 171*4882a593Smuzhiyun gw,mode = <1>; 172*4882a593Smuzhiyun reg = <0x05>; 173*4882a593Smuzhiyun label = "vdd_3p3"; 174*4882a593Smuzhiyun }; 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun channel@8 { 177*4882a593Smuzhiyun gw,mode = <1>; 178*4882a593Smuzhiyun reg = <0x08>; 179*4882a593Smuzhiyun label = "vdd_bat"; 180*4882a593Smuzhiyun }; 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun channel@b { 183*4882a593Smuzhiyun gw,mode = <1>; 184*4882a593Smuzhiyun reg = <0x0b>; 185*4882a593Smuzhiyun label = "vdd_5p0"; 186*4882a593Smuzhiyun }; 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun channel@e { 189*4882a593Smuzhiyun gw,mode = <1>; 190*4882a593Smuzhiyun reg = <0xe>; 191*4882a593Smuzhiyun label = "vdd_arm"; 192*4882a593Smuzhiyun }; 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun channel@11 { 195*4882a593Smuzhiyun gw,mode = <1>; 196*4882a593Smuzhiyun reg = <0x11>; 197*4882a593Smuzhiyun label = "vdd_soc"; 198*4882a593Smuzhiyun }; 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun channel@14 { 201*4882a593Smuzhiyun gw,mode = <1>; 202*4882a593Smuzhiyun reg = <0x14>; 203*4882a593Smuzhiyun label = "vdd_3p0"; 204*4882a593Smuzhiyun }; 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun channel@17 { 207*4882a593Smuzhiyun gw,mode = <1>; 208*4882a593Smuzhiyun reg = <0x17>; 209*4882a593Smuzhiyun label = "vdd_1p5"; 210*4882a593Smuzhiyun }; 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun channel@1d { 213*4882a593Smuzhiyun gw,mode = <1>; 214*4882a593Smuzhiyun reg = <0x1d>; 215*4882a593Smuzhiyun label = "vdd_1p8"; 216*4882a593Smuzhiyun }; 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun channel@20 { 219*4882a593Smuzhiyun gw,mode = <1>; 220*4882a593Smuzhiyun reg = <0x20>; 221*4882a593Smuzhiyun label = "vdd_1p0"; 222*4882a593Smuzhiyun }; 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun channel@23 { 225*4882a593Smuzhiyun gw,mode = <1>; 226*4882a593Smuzhiyun reg = <0x23>; 227*4882a593Smuzhiyun label = "vdd_2p5"; 228*4882a593Smuzhiyun }; 229*4882a593Smuzhiyun }; 230*4882a593Smuzhiyun }; 231*4882a593Smuzhiyun 232*4882a593Smuzhiyun gsc_gpio: gpio@23 { 233*4882a593Smuzhiyun compatible = "nxp,pca9555"; 234*4882a593Smuzhiyun reg = <0x23>; 235*4882a593Smuzhiyun gpio-controller; 236*4882a593Smuzhiyun #gpio-cells = <2>; 237*4882a593Smuzhiyun interrupt-parent = <&gsc>; 238*4882a593Smuzhiyun interrupts = <4>; 239*4882a593Smuzhiyun }; 240*4882a593Smuzhiyun 241*4882a593Smuzhiyun eeprom1: eeprom@50 { 242*4882a593Smuzhiyun compatible = "atmel,24c02"; 243*4882a593Smuzhiyun reg = <0x50>; 244*4882a593Smuzhiyun pagesize = <16>; 245*4882a593Smuzhiyun }; 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun eeprom2: eeprom@51 { 248*4882a593Smuzhiyun compatible = "atmel,24c02"; 249*4882a593Smuzhiyun reg = <0x51>; 250*4882a593Smuzhiyun pagesize = <16>; 251*4882a593Smuzhiyun }; 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun eeprom3: eeprom@52 { 254*4882a593Smuzhiyun compatible = "atmel,24c02"; 255*4882a593Smuzhiyun reg = <0x52>; 256*4882a593Smuzhiyun pagesize = <16>; 257*4882a593Smuzhiyun }; 258*4882a593Smuzhiyun 259*4882a593Smuzhiyun eeprom4: eeprom@53 { 260*4882a593Smuzhiyun compatible = "atmel,24c02"; 261*4882a593Smuzhiyun reg = <0x53>; 262*4882a593Smuzhiyun pagesize = <16>; 263*4882a593Smuzhiyun }; 264*4882a593Smuzhiyun 265*4882a593Smuzhiyun rtc: ds1672@68 { 266*4882a593Smuzhiyun compatible = "dallas,ds1672"; 267*4882a593Smuzhiyun reg = <0x68>; 268*4882a593Smuzhiyun }; 269*4882a593Smuzhiyun}; 270*4882a593Smuzhiyun 271*4882a593Smuzhiyun&i2c2 { 272*4882a593Smuzhiyun clock-frequency = <100000>; 273*4882a593Smuzhiyun pinctrl-names = "default"; 274*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c2>; 275*4882a593Smuzhiyun status = "okay"; 276*4882a593Smuzhiyun 277*4882a593Smuzhiyun ltc3676: pmic@3c { 278*4882a593Smuzhiyun compatible = "lltc,ltc3676"; 279*4882a593Smuzhiyun reg = <0x3c>; 280*4882a593Smuzhiyun pinctrl-names = "default"; 281*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pmic>; 282*4882a593Smuzhiyun interrupt-parent = <&gpio1>; 283*4882a593Smuzhiyun interrupts = <8 IRQ_TYPE_EDGE_FALLING>; 284*4882a593Smuzhiyun 285*4882a593Smuzhiyun regulators { 286*4882a593Smuzhiyun /* VDD_SOC (1+R1/R2 = 1.635) */ 287*4882a593Smuzhiyun reg_vdd_soc: sw1 { 288*4882a593Smuzhiyun regulator-name = "vddsoc"; 289*4882a593Smuzhiyun regulator-min-microvolt = <674400>; 290*4882a593Smuzhiyun regulator-max-microvolt = <1308000>; 291*4882a593Smuzhiyun lltc,fb-voltage-divider = <127000 200000>; 292*4882a593Smuzhiyun regulator-ramp-delay = <7000>; 293*4882a593Smuzhiyun regulator-boot-on; 294*4882a593Smuzhiyun regulator-always-on; 295*4882a593Smuzhiyun }; 296*4882a593Smuzhiyun 297*4882a593Smuzhiyun /* VDD_1P8 (1+R1/R2 = 2.505): ENET-PHY */ 298*4882a593Smuzhiyun reg_1p8v: sw2 { 299*4882a593Smuzhiyun regulator-name = "vdd1p8"; 300*4882a593Smuzhiyun regulator-min-microvolt = <1033310>; 301*4882a593Smuzhiyun regulator-max-microvolt = <2004000>; 302*4882a593Smuzhiyun lltc,fb-voltage-divider = <301000 200000>; 303*4882a593Smuzhiyun regulator-ramp-delay = <7000>; 304*4882a593Smuzhiyun regulator-boot-on; 305*4882a593Smuzhiyun regulator-always-on; 306*4882a593Smuzhiyun }; 307*4882a593Smuzhiyun 308*4882a593Smuzhiyun /* VDD_ARM (1+R1/R2 = 1.635) */ 309*4882a593Smuzhiyun reg_vdd_arm: sw3 { 310*4882a593Smuzhiyun regulator-name = "vddarm"; 311*4882a593Smuzhiyun regulator-min-microvolt = <674400>; 312*4882a593Smuzhiyun regulator-max-microvolt = <1308000>; 313*4882a593Smuzhiyun lltc,fb-voltage-divider = <127000 200000>; 314*4882a593Smuzhiyun regulator-ramp-delay = <7000>; 315*4882a593Smuzhiyun regulator-boot-on; 316*4882a593Smuzhiyun regulator-always-on; 317*4882a593Smuzhiyun }; 318*4882a593Smuzhiyun 319*4882a593Smuzhiyun /* VDD_DDR (1+R1/R2 = 2.105) */ 320*4882a593Smuzhiyun reg_vdd_ddr: sw4 { 321*4882a593Smuzhiyun regulator-name = "vddddr"; 322*4882a593Smuzhiyun regulator-min-microvolt = <868310>; 323*4882a593Smuzhiyun regulator-max-microvolt = <1684000>; 324*4882a593Smuzhiyun lltc,fb-voltage-divider = <221000 200000>; 325*4882a593Smuzhiyun regulator-ramp-delay = <7000>; 326*4882a593Smuzhiyun regulator-boot-on; 327*4882a593Smuzhiyun regulator-always-on; 328*4882a593Smuzhiyun }; 329*4882a593Smuzhiyun 330*4882a593Smuzhiyun /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */ 331*4882a593Smuzhiyun reg_2p5v: ldo2 { 332*4882a593Smuzhiyun regulator-name = "vdd2p5"; 333*4882a593Smuzhiyun regulator-min-microvolt = <2490375>; 334*4882a593Smuzhiyun regulator-max-microvolt = <2490375>; 335*4882a593Smuzhiyun lltc,fb-voltage-divider = <487000 200000>; 336*4882a593Smuzhiyun regulator-boot-on; 337*4882a593Smuzhiyun regulator-always-on; 338*4882a593Smuzhiyun }; 339*4882a593Smuzhiyun 340*4882a593Smuzhiyun /* VDD_HIGH (1+R1/R2 = 4.17) */ 341*4882a593Smuzhiyun reg_3p0v: ldo4 { 342*4882a593Smuzhiyun regulator-name = "vdd3p0"; 343*4882a593Smuzhiyun regulator-min-microvolt = <3023250>; 344*4882a593Smuzhiyun regulator-max-microvolt = <3023250>; 345*4882a593Smuzhiyun lltc,fb-voltage-divider = <634000 200000>; 346*4882a593Smuzhiyun regulator-boot-on; 347*4882a593Smuzhiyun regulator-always-on; 348*4882a593Smuzhiyun }; 349*4882a593Smuzhiyun }; 350*4882a593Smuzhiyun }; 351*4882a593Smuzhiyun}; 352*4882a593Smuzhiyun 353*4882a593Smuzhiyun&i2c3 { 354*4882a593Smuzhiyun clock-frequency = <100000>; 355*4882a593Smuzhiyun pinctrl-names = "default"; 356*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c3>; 357*4882a593Smuzhiyun status = "okay"; 358*4882a593Smuzhiyun}; 359*4882a593Smuzhiyun 360*4882a593Smuzhiyun&pcie { 361*4882a593Smuzhiyun pinctrl-names = "default"; 362*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pcie>; 363*4882a593Smuzhiyun reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; 364*4882a593Smuzhiyun status = "okay"; 365*4882a593Smuzhiyun}; 366*4882a593Smuzhiyun 367*4882a593Smuzhiyun&pwm2 { 368*4882a593Smuzhiyun pinctrl-names = "default"; 369*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ 370*4882a593Smuzhiyun status = "disabled"; 371*4882a593Smuzhiyun}; 372*4882a593Smuzhiyun 373*4882a593Smuzhiyun&pwm3 { 374*4882a593Smuzhiyun pinctrl-names = "default"; 375*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ 376*4882a593Smuzhiyun status = "disabled"; 377*4882a593Smuzhiyun}; 378*4882a593Smuzhiyun 379*4882a593Smuzhiyun&uart2 { 380*4882a593Smuzhiyun pinctrl-names = "default"; 381*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart2>; 382*4882a593Smuzhiyun status = "okay"; 383*4882a593Smuzhiyun}; 384*4882a593Smuzhiyun 385*4882a593Smuzhiyun&uart3 { 386*4882a593Smuzhiyun pinctrl-names = "default"; 387*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart3>; 388*4882a593Smuzhiyun status = "okay"; 389*4882a593Smuzhiyun}; 390*4882a593Smuzhiyun 391*4882a593Smuzhiyun&uart5 { 392*4882a593Smuzhiyun pinctrl-names = "default"; 393*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart5>; 394*4882a593Smuzhiyun status = "okay"; }; 395*4882a593Smuzhiyun 396*4882a593Smuzhiyun&usbh1 { 397*4882a593Smuzhiyun status = "okay"; 398*4882a593Smuzhiyun}; 399*4882a593Smuzhiyun 400*4882a593Smuzhiyun&usbotg { 401*4882a593Smuzhiyun vbus-supply = <®_5p0v>; 402*4882a593Smuzhiyun pinctrl-names = "default"; 403*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usbotg>; 404*4882a593Smuzhiyun disable-over-current; 405*4882a593Smuzhiyun status = "okay"; 406*4882a593Smuzhiyun}; 407*4882a593Smuzhiyun 408*4882a593Smuzhiyun&wdog1 { 409*4882a593Smuzhiyun pinctrl-names = "default"; 410*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_wdog>; 411*4882a593Smuzhiyun fsl,ext-reset-output; 412*4882a593Smuzhiyun}; 413*4882a593Smuzhiyun 414*4882a593Smuzhiyun&iomuxc { 415*4882a593Smuzhiyun pinctrl_gpio_leds: gpioledsgrp { 416*4882a593Smuzhiyun fsl,pins = < 417*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 418*4882a593Smuzhiyun MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 419*4882a593Smuzhiyun MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 420*4882a593Smuzhiyun >; 421*4882a593Smuzhiyun }; 422*4882a593Smuzhiyun 423*4882a593Smuzhiyun pinctrl_gpmi_nand: gpminandgrp { 424*4882a593Smuzhiyun fsl,pins = < 425*4882a593Smuzhiyun MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 426*4882a593Smuzhiyun MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 427*4882a593Smuzhiyun MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 428*4882a593Smuzhiyun MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 429*4882a593Smuzhiyun MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 430*4882a593Smuzhiyun MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 431*4882a593Smuzhiyun MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 432*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 433*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 434*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 435*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 436*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 437*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 438*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 439*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 440*4882a593Smuzhiyun >; 441*4882a593Smuzhiyun }; 442*4882a593Smuzhiyun 443*4882a593Smuzhiyun pinctrl_i2c1: i2c1grp { 444*4882a593Smuzhiyun fsl,pins = < 445*4882a593Smuzhiyun MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 446*4882a593Smuzhiyun MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 447*4882a593Smuzhiyun MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 448*4882a593Smuzhiyun >; 449*4882a593Smuzhiyun }; 450*4882a593Smuzhiyun 451*4882a593Smuzhiyun pinctrl_i2c2: i2c2grp { 452*4882a593Smuzhiyun fsl,pins = < 453*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 454*4882a593Smuzhiyun MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 455*4882a593Smuzhiyun >; 456*4882a593Smuzhiyun }; 457*4882a593Smuzhiyun 458*4882a593Smuzhiyun pinctrl_i2c3: i2c3grp { 459*4882a593Smuzhiyun fsl,pins = < 460*4882a593Smuzhiyun MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 461*4882a593Smuzhiyun MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 462*4882a593Smuzhiyun >; 463*4882a593Smuzhiyun }; 464*4882a593Smuzhiyun 465*4882a593Smuzhiyun pinctrl_pcie: pciegrp { 466*4882a593Smuzhiyun fsl,pins = < 467*4882a593Smuzhiyun MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 468*4882a593Smuzhiyun >; 469*4882a593Smuzhiyun }; 470*4882a593Smuzhiyun 471*4882a593Smuzhiyun pinctrl_pmic: pmicgrp { 472*4882a593Smuzhiyun fsl,pins = < 473*4882a593Smuzhiyun MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ 474*4882a593Smuzhiyun >; 475*4882a593Smuzhiyun }; 476*4882a593Smuzhiyun 477*4882a593Smuzhiyun pinctrl_pwm2: pwm2grp { 478*4882a593Smuzhiyun fsl,pins = < 479*4882a593Smuzhiyun MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 480*4882a593Smuzhiyun >; 481*4882a593Smuzhiyun }; 482*4882a593Smuzhiyun 483*4882a593Smuzhiyun pinctrl_pwm3: pwm3grp { 484*4882a593Smuzhiyun fsl,pins = < 485*4882a593Smuzhiyun MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 486*4882a593Smuzhiyun >; 487*4882a593Smuzhiyun }; 488*4882a593Smuzhiyun 489*4882a593Smuzhiyun pinctrl_uart2: uart2grp { 490*4882a593Smuzhiyun fsl,pins = < 491*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 492*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 493*4882a593Smuzhiyun >; 494*4882a593Smuzhiyun }; 495*4882a593Smuzhiyun 496*4882a593Smuzhiyun pinctrl_uart3: uart3grp { 497*4882a593Smuzhiyun fsl,pins = < 498*4882a593Smuzhiyun MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 499*4882a593Smuzhiyun MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 500*4882a593Smuzhiyun >; 501*4882a593Smuzhiyun }; 502*4882a593Smuzhiyun 503*4882a593Smuzhiyun pinctrl_uart5: uart5grp { 504*4882a593Smuzhiyun fsl,pins = < 505*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 506*4882a593Smuzhiyun MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 507*4882a593Smuzhiyun >; 508*4882a593Smuzhiyun }; 509*4882a593Smuzhiyun 510*4882a593Smuzhiyun pinctrl_usbotg: usbotggrp { 511*4882a593Smuzhiyun fsl,pins = < 512*4882a593Smuzhiyun MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x13059 513*4882a593Smuzhiyun >; 514*4882a593Smuzhiyun }; 515*4882a593Smuzhiyun 516*4882a593Smuzhiyun pinctrl_wdog: wdoggrp { 517*4882a593Smuzhiyun fsl,pins = < 518*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 519*4882a593Smuzhiyun >; 520*4882a593Smuzhiyun }; 521*4882a593Smuzhiyun}; 522