1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun/ { 5*4882a593Smuzhiyun regulators { 6*4882a593Smuzhiyun compatible = "simple-bus"; 7*4882a593Smuzhiyun #address-cells = <1>; 8*4882a593Smuzhiyun #size-cells = <0>; 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun dummy_reg: regulator@0 { 11*4882a593Smuzhiyun compatible = "regulator-fixed"; 12*4882a593Smuzhiyun reg = <0>; 13*4882a593Smuzhiyun regulator-name = "dummy-supply"; 14*4882a593Smuzhiyun }; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun reg_usb_otg_vbus: regulator@1 { 17*4882a593Smuzhiyun compatible = "regulator-fixed"; 18*4882a593Smuzhiyun reg = <1>; 19*4882a593Smuzhiyun regulator-name = "usb_otg_vbus"; 20*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 21*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 22*4882a593Smuzhiyun gpio = <&gpio3 22 0>; 23*4882a593Smuzhiyun enable-active-high; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun chosen { 28*4882a593Smuzhiyun stdout-path = &uart1; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun}; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun&ecspi3 { 33*4882a593Smuzhiyun cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; 34*4882a593Smuzhiyun pinctrl-names = "default"; 35*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_ecspi3>; 36*4882a593Smuzhiyun status = "okay"; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun flash: flash@0 { 39*4882a593Smuzhiyun #address-cells = <1>; 40*4882a593Smuzhiyun #size-cells = <1>; 41*4882a593Smuzhiyun compatible = "sst,sst25vf040b", "jedec,spi-nor"; 42*4882a593Smuzhiyun spi-max-frequency = <20000000>; 43*4882a593Smuzhiyun reg = <0>; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun}; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun&fec { 48*4882a593Smuzhiyun pinctrl-names = "default"; 49*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_enet>; 50*4882a593Smuzhiyun status = "okay"; 51*4882a593Smuzhiyun phy-mode = "rgmii"; 52*4882a593Smuzhiyun}; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun&iomuxc { 55*4882a593Smuzhiyun pinctrl-names = "default"; 56*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_hog>; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun imx6qdl-dfi-fs700-m60 { 59*4882a593Smuzhiyun pinctrl_hog: hoggrp { 60*4882a593Smuzhiyun fsl,pins = < 61*4882a593Smuzhiyun MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 62*4882a593Smuzhiyun MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000 /* PMIC irq */ 63*4882a593Smuzhiyun MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000 /* MAX11801 irq */ 64*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000030b0 /* Backlight enable */ 65*4882a593Smuzhiyun >; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun pinctrl_enet: enetgrp { 69*4882a593Smuzhiyun fsl,pins = < 70*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 71*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 72*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 73*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 74*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 75*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 76*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 77*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 78*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 79*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 80*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 81*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 82*4882a593Smuzhiyun MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 83*4882a593Smuzhiyun MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 84*4882a593Smuzhiyun MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 85*4882a593Smuzhiyun MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 86*4882a593Smuzhiyun >; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun pinctrl_i2c2: i2c2grp { 90*4882a593Smuzhiyun fsl,pins = < 91*4882a593Smuzhiyun MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 92*4882a593Smuzhiyun MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 93*4882a593Smuzhiyun >; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun pinctrl_uart1: uart1grp { 97*4882a593Smuzhiyun fsl,pins = < 98*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 99*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 100*4882a593Smuzhiyun >; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun pinctrl_usbotg: usbotggrp { 104*4882a593Smuzhiyun fsl,pins = < 105*4882a593Smuzhiyun MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 106*4882a593Smuzhiyun >; 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun pinctrl_usdhc2: usdhc2grp { 110*4882a593Smuzhiyun fsl,pins = < 111*4882a593Smuzhiyun MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 112*4882a593Smuzhiyun MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 113*4882a593Smuzhiyun MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 114*4882a593Smuzhiyun MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 115*4882a593Smuzhiyun MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 116*4882a593Smuzhiyun MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 117*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 /* card detect */ 118*4882a593Smuzhiyun >; 119*4882a593Smuzhiyun }; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun pinctrl_usdhc3: usdhc3grp { 122*4882a593Smuzhiyun fsl,pins = < 123*4882a593Smuzhiyun MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 124*4882a593Smuzhiyun MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 125*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 126*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 127*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 128*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 129*4882a593Smuzhiyun >; 130*4882a593Smuzhiyun }; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun pinctrl_usdhc4: usdhc4grp { 133*4882a593Smuzhiyun fsl,pins = < 134*4882a593Smuzhiyun MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 135*4882a593Smuzhiyun MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 136*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 137*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 138*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 139*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 140*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 141*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 142*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 143*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 144*4882a593Smuzhiyun >; 145*4882a593Smuzhiyun }; 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun pinctrl_ecspi3: ecspi3grp { 148*4882a593Smuzhiyun fsl,pins = < 149*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 150*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 151*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 152*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */ 153*4882a593Smuzhiyun >; 154*4882a593Smuzhiyun }; 155*4882a593Smuzhiyun }; 156*4882a593Smuzhiyun}; 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun&i2c2 { 159*4882a593Smuzhiyun pinctrl-names = "default"; 160*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c2>; 161*4882a593Smuzhiyun status = "okay"; 162*4882a593Smuzhiyun}; 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun&uart1 { 165*4882a593Smuzhiyun pinctrl-names = "default"; 166*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart1>; 167*4882a593Smuzhiyun status = "okay"; 168*4882a593Smuzhiyun}; 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun&usbh1 { 171*4882a593Smuzhiyun status = "okay"; 172*4882a593Smuzhiyun}; 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun&usbotg { 175*4882a593Smuzhiyun vbus-supply = <®_usb_otg_vbus>; 176*4882a593Smuzhiyun pinctrl-names = "default"; 177*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usbotg>; 178*4882a593Smuzhiyun disable-over-current; 179*4882a593Smuzhiyun dr_mode = "host"; 180*4882a593Smuzhiyun status = "okay"; 181*4882a593Smuzhiyun}; 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun&usdhc2 { /* module slot */ 184*4882a593Smuzhiyun pinctrl-names = "default"; 185*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc2>; 186*4882a593Smuzhiyun cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; 187*4882a593Smuzhiyun status = "okay"; 188*4882a593Smuzhiyun}; 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun&usdhc3 { /* baseboard slot */ 191*4882a593Smuzhiyun pinctrl-names = "default"; 192*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc3>; 193*4882a593Smuzhiyun}; 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun&usdhc4 { /* eMMC */ 196*4882a593Smuzhiyun pinctrl-names = "default"; 197*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc4>; 198*4882a593Smuzhiyun bus-width = <8>; 199*4882a593Smuzhiyun non-removable; 200*4882a593Smuzhiyun status = "okay"; 201*4882a593Smuzhiyun}; 202