xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0+ OR MIT
2*4882a593Smuzhiyun//
3*4882a593Smuzhiyun// Copyright 2015 Armadeus Systems <support@armadeus.com>
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
6*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
7*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h>
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun/ {
10*4882a593Smuzhiyun	chosen {
11*4882a593Smuzhiyun		stdout-path = &uart4;
12*4882a593Smuzhiyun	};
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun	backlight: backlight {
15*4882a593Smuzhiyun		compatible = "pwm-backlight";
16*4882a593Smuzhiyun		pwms = <&pwm3 0 191000>;
17*4882a593Smuzhiyun		brightness-levels = <0 4 8 16 32 64 128 255>;
18*4882a593Smuzhiyun		default-brightness-level = <0>;
19*4882a593Smuzhiyun		power-supply = <&reg_5v>;
20*4882a593Smuzhiyun	};
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun	disp0 {
23*4882a593Smuzhiyun		compatible = "fsl,imx-parallel-display";
24*4882a593Smuzhiyun		pinctrl-names = "default";
25*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_ipu1_disp0>;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun		#address-cells = <1>;
28*4882a593Smuzhiyun		#size-cells = <0>;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun		port@0 {
31*4882a593Smuzhiyun			reg = <0>;
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun			display_in: endpoint {
34*4882a593Smuzhiyun				remote-endpoint = <&ipu1_di0_disp0>;
35*4882a593Smuzhiyun			};
36*4882a593Smuzhiyun		};
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun		port@1 {
39*4882a593Smuzhiyun			reg = <1>;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun			display_out: endpoint {
42*4882a593Smuzhiyun				remote-endpoint = <&panel_in>;
43*4882a593Smuzhiyun			};
44*4882a593Smuzhiyun		};
45*4882a593Smuzhiyun	};
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun	gpio-keys {
48*4882a593Smuzhiyun		compatible = "gpio-keys";
49*4882a593Smuzhiyun		pinctrl-names = "default";
50*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_gpio_keys>;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun		user-button {
53*4882a593Smuzhiyun			label = "User button";
54*4882a593Smuzhiyun			gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
55*4882a593Smuzhiyun			linux,code = <BTN_MISC>;
56*4882a593Smuzhiyun			wakeup-source;
57*4882a593Smuzhiyun		};
58*4882a593Smuzhiyun	};
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun	leds {
61*4882a593Smuzhiyun		compatible = "gpio-leds";
62*4882a593Smuzhiyun		pinctrl-names = "default";
63*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_gpio_leds>;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun		user-led {
66*4882a593Smuzhiyun			label = "User LED";
67*4882a593Smuzhiyun			gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>;
68*4882a593Smuzhiyun			linux,default-trigger = "heartbeat";
69*4882a593Smuzhiyun			default-state = "on";
70*4882a593Smuzhiyun		};
71*4882a593Smuzhiyun	};
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun	panel {
74*4882a593Smuzhiyun		compatible = "armadeus,st0700-adapt";
75*4882a593Smuzhiyun		power-supply = <&reg_3p3v>;
76*4882a593Smuzhiyun		backlight = <&backlight>;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun		port {
79*4882a593Smuzhiyun			panel_in: endpoint {
80*4882a593Smuzhiyun				remote-endpoint = <&display_out>;
81*4882a593Smuzhiyun			};
82*4882a593Smuzhiyun		};
83*4882a593Smuzhiyun	};
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun	reg_3p3v: regulator-3p3v {
86*4882a593Smuzhiyun		compatible = "regulator-fixed";
87*4882a593Smuzhiyun		regulator-name = "3P3V";
88*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
89*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
90*4882a593Smuzhiyun		regulator-always-on;
91*4882a593Smuzhiyun		vin-supply = <&reg_5v>;
92*4882a593Smuzhiyun	};
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun	reg_5v: regulator-5v {
95*4882a593Smuzhiyun		compatible = "regulator-fixed";
96*4882a593Smuzhiyun		regulator-name = "5V";
97*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
98*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
99*4882a593Smuzhiyun		regulator-always-on;
100*4882a593Smuzhiyun	};
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun	reg_usb_otg_vbus: regulator-usb-otg-vbus {
103*4882a593Smuzhiyun		compatible = "regulator-fixed";
104*4882a593Smuzhiyun		regulator-name = "usb_otg_vbus";
105*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
106*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
107*4882a593Smuzhiyun		regulator-always-on;
108*4882a593Smuzhiyun	};
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun	sound {
111*4882a593Smuzhiyun		compatible = "fsl,imx6-armadeus-sgtl5000",
112*4882a593Smuzhiyun			     "fsl,imx-audio-sgtl5000";
113*4882a593Smuzhiyun		model = "imx6-armadeus-sgtl5000";
114*4882a593Smuzhiyun		ssi-controller = <&ssi1>;
115*4882a593Smuzhiyun		audio-codec = <&codec>;
116*4882a593Smuzhiyun		audio-routing =
117*4882a593Smuzhiyun			"MIC_IN", "Mic Jack",
118*4882a593Smuzhiyun			"Mic Jack", "Mic Bias",
119*4882a593Smuzhiyun			"Headphone Jack", "HP_OUT";
120*4882a593Smuzhiyun		mux-int-port = <1>;
121*4882a593Smuzhiyun		mux-ext-port = <3>;
122*4882a593Smuzhiyun	};
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun	sound-spdif {
125*4882a593Smuzhiyun		compatible = "fsl,imx-audio-spdif";
126*4882a593Smuzhiyun		model = "imx-spdif";
127*4882a593Smuzhiyun		spdif-controller = <&spdif>;
128*4882a593Smuzhiyun		spdif-out;
129*4882a593Smuzhiyun	};
130*4882a593Smuzhiyun};
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun&audmux {
133*4882a593Smuzhiyun	pinctrl-names = "default";
134*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_audmux>;
135*4882a593Smuzhiyun	status = "okay";
136*4882a593Smuzhiyun};
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun&can2 {
139*4882a593Smuzhiyun	pinctrl-names = "default";
140*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_flexcan2>;
141*4882a593Smuzhiyun	xceiver-supply = <&reg_5v>;
142*4882a593Smuzhiyun	status = "okay";
143*4882a593Smuzhiyun};
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun&ecspi1 {
146*4882a593Smuzhiyun	pinctrl-names = "default";
147*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_ecspi1>;
148*4882a593Smuzhiyun	cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>,
149*4882a593Smuzhiyun		   <&gpio4 10 GPIO_ACTIVE_LOW>,
150*4882a593Smuzhiyun		   <&gpio4 11 GPIO_ACTIVE_LOW>;
151*4882a593Smuzhiyun	status = "okay";
152*4882a593Smuzhiyun};
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun&hdmi {
155*4882a593Smuzhiyun	ddc-i2c-bus = <&i2c3>;
156*4882a593Smuzhiyun	status = "okay";
157*4882a593Smuzhiyun};
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun&i2c1 {
160*4882a593Smuzhiyun	clock-frequency = <400000>;
161*4882a593Smuzhiyun	pinctrl-names = "default";
162*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c1>;
163*4882a593Smuzhiyun	status = "okay";
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun	touchscreen@48 {
166*4882a593Smuzhiyun		compatible = "semtech,sx8654";
167*4882a593Smuzhiyun		reg = <0x48>;
168*4882a593Smuzhiyun		pinctrl-names = "default";
169*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_touchscreen>;
170*4882a593Smuzhiyun		interrupt-parent = <&gpio6>;
171*4882a593Smuzhiyun		interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
172*4882a593Smuzhiyun	};
173*4882a593Smuzhiyun};
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun&i2c2 {
176*4882a593Smuzhiyun	clock-frequency = <400000>;
177*4882a593Smuzhiyun	pinctrl-names = "default";
178*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c2>;
179*4882a593Smuzhiyun	status = "okay";
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun	codec: sgtl5000@a {
182*4882a593Smuzhiyun		compatible = "fsl,sgtl5000";
183*4882a593Smuzhiyun		reg = <0x0a>;
184*4882a593Smuzhiyun		clocks = <&clks IMX6QDL_CLK_CKO>;
185*4882a593Smuzhiyun		VDDA-supply = <&reg_3p3v>;
186*4882a593Smuzhiyun		VDDIO-supply = <&reg_3p3v>;
187*4882a593Smuzhiyun	};
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun	rtc@6f {
190*4882a593Smuzhiyun		compatible = "microchip,mcp7940x";
191*4882a593Smuzhiyun		reg = <0x6f>;
192*4882a593Smuzhiyun	};
193*4882a593Smuzhiyun};
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun&i2c3 {
196*4882a593Smuzhiyun	clock-frequency = <400000>;
197*4882a593Smuzhiyun	pinctrl-names = "default";
198*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c3>;
199*4882a593Smuzhiyun	status = "okay";
200*4882a593Smuzhiyun};
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun&ipu1_di0_disp0 {
203*4882a593Smuzhiyun	remote-endpoint = <&display_in>;
204*4882a593Smuzhiyun};
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun&pcie {
207*4882a593Smuzhiyun	pinctrl-names = "default";
208*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pcie>;
209*4882a593Smuzhiyun	reset-gpio = <&gpio6 2 GPIO_ACTIVE_LOW>;
210*4882a593Smuzhiyun	status = "okay";
211*4882a593Smuzhiyun};
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun&pwm3 {
214*4882a593Smuzhiyun	#pwm-cells = <2>;
215*4882a593Smuzhiyun	pinctrl-names = "default";
216*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pwm3>;
217*4882a593Smuzhiyun	status = "okay";
218*4882a593Smuzhiyun};
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun/* GPS */
221*4882a593Smuzhiyun&uart1 {
222*4882a593Smuzhiyun	pinctrl-names = "default";
223*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart1>;
224*4882a593Smuzhiyun	status = "okay";
225*4882a593Smuzhiyun};
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun/* GSM */
228*4882a593Smuzhiyun&uart3 {
229*4882a593Smuzhiyun	pinctrl-names = "default";
230*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart3 &pinctrl_gsm>;
231*4882a593Smuzhiyun	uart-has-rtscts;
232*4882a593Smuzhiyun	status = "okay";
233*4882a593Smuzhiyun};
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun/* console */
236*4882a593Smuzhiyun&uart4 {
237*4882a593Smuzhiyun	pinctrl-names = "default";
238*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart4>;
239*4882a593Smuzhiyun	status = "okay";
240*4882a593Smuzhiyun};
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun&usbh1 {
243*4882a593Smuzhiyun	vbus-supply = <&reg_5v>;
244*4882a593Smuzhiyun	phy_type = "utmi";
245*4882a593Smuzhiyun	status = "okay";
246*4882a593Smuzhiyun};
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun&usbotg {
249*4882a593Smuzhiyun	pinctrl-names = "default";
250*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usbotg>;
251*4882a593Smuzhiyun	vbus-supply = <&reg_usb_otg_vbus>;
252*4882a593Smuzhiyun	dr_mode = "otg";
253*4882a593Smuzhiyun	status = "okay";
254*4882a593Smuzhiyun};
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun/* microSD */
257*4882a593Smuzhiyun&usdhc2 {
258*4882a593Smuzhiyun	pinctrl-names = "default";
259*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc2>;
260*4882a593Smuzhiyun	cd-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
261*4882a593Smuzhiyun	no-1-8-v;
262*4882a593Smuzhiyun	status = "okay";
263*4882a593Smuzhiyun};
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun&spdif {
266*4882a593Smuzhiyun	pinctrl-names = "default";
267*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_spdif>;
268*4882a593Smuzhiyun	status = "okay";
269*4882a593Smuzhiyun};
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun&ssi1 {
272*4882a593Smuzhiyun	status = "okay";
273*4882a593Smuzhiyun};
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun&iomuxc {
276*4882a593Smuzhiyun	pinctrl-names = "default";
277*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_gpios>;
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun	pinctrl_audmux: audmuxgrp {
280*4882a593Smuzhiyun		fsl,pins = <
281*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT4__AUD3_TXC  0x1b0b0
282*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT5__AUD3_TXD  0x1b0b0
283*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0
284*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT7__AUD3_RXD  0x1b0b0
285*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x130b0
286*4882a593Smuzhiyun		>;
287*4882a593Smuzhiyun	};
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun	pinctrl_ecspi1: ecspi1grp {
290*4882a593Smuzhiyun		fsl,pins = <
291*4882a593Smuzhiyun			MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
292*4882a593Smuzhiyun			MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
293*4882a593Smuzhiyun			MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
294*4882a593Smuzhiyun			MX6QDL_PAD_KEY_ROW1__GPIO4_IO09  0x1b0b0
295*4882a593Smuzhiyun			MX6QDL_PAD_KEY_ROW2__GPIO4_IO11  0x1b0b0
296*4882a593Smuzhiyun			MX6QDL_PAD_KEY_COL2__GPIO4_IO10  0x1b0b0
297*4882a593Smuzhiyun		>;
298*4882a593Smuzhiyun	};
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun	pinctrl_flexcan2: flexcan2grp {
301*4882a593Smuzhiyun		fsl,pins = <
302*4882a593Smuzhiyun			MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
303*4882a593Smuzhiyun			MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
304*4882a593Smuzhiyun		>;
305*4882a593Smuzhiyun	};
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun	pinctrl_gpio_keys: gpiokeysgrp {
308*4882a593Smuzhiyun		fsl,pins = <
309*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
310*4882a593Smuzhiyun		>;
311*4882a593Smuzhiyun	};
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun	pinctrl_gpio_leds: gpioledsgrp {
314*4882a593Smuzhiyun		fsl,pins = <
315*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x130b0
316*4882a593Smuzhiyun		>;
317*4882a593Smuzhiyun	};
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun	pinctrl_gpios: gpiosgrp {
320*4882a593Smuzhiyun		fsl,pins = <
321*4882a593Smuzhiyun			MX6QDL_PAD_DI0_PIN4__GPIO4_IO20		0x100b1
322*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12	0x100b1
323*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13	0x100b1
324*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14	0x100b1
325*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15	0x100b1
326*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16	0x100b1
327*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17	0x100b1
328*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18	0x100b1
329*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21	0x100b1
330*4882a593Smuzhiyun		>;
331*4882a593Smuzhiyun	};
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun	pinctrl_gsm: gsmgrp {
334*4882a593Smuzhiyun		fsl,pins = <
335*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_4__GPIO1_IO04  0x130b0 /* GSM_POKIN */
336*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x130b0 /* GSM_PWR_EN */
337*4882a593Smuzhiyun		>;
338*4882a593Smuzhiyun	};
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun	pinctrl_i2c1: i2c1grp {
341*4882a593Smuzhiyun		fsl,pins = <
342*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
343*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
344*4882a593Smuzhiyun		>;
345*4882a593Smuzhiyun	};
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun	pinctrl_i2c2: i2c2grp {
348*4882a593Smuzhiyun		fsl,pins = <
349*4882a593Smuzhiyun			MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
350*4882a593Smuzhiyun			MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
351*4882a593Smuzhiyun		>;
352*4882a593Smuzhiyun	};
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun	pinctrl_i2c3: i2c3grp {
355*4882a593Smuzhiyun		fsl,pins = <
356*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
357*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
358*4882a593Smuzhiyun		>;
359*4882a593Smuzhiyun	};
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun	pinctrl_ipu1_disp0: ipu1disp0grp {
362*4882a593Smuzhiyun		fsl,pins = <
363*4882a593Smuzhiyun			MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK	0x100b1
364*4882a593Smuzhiyun			MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15		0x100b1
365*4882a593Smuzhiyun			MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02		0x100b1
366*4882a593Smuzhiyun			MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03		0x100b1
367*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00	0x100b1
368*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01	0x100b1
369*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02	0x100b1
370*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03	0x100b1
371*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04	0x100b1
372*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05	0x100b1
373*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06	0x100b1
374*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07	0x100b1
375*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08	0x100b1
376*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09	0x100b1
377*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10	0x100b1
378*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11	0x100b1
379*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12	0x100b1
380*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13	0x100b1
381*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14	0x100b1
382*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15	0x100b1
383*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16	0x100b1
384*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17	0x100b1
385*4882a593Smuzhiyun		>;
386*4882a593Smuzhiyun	};
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun	pinctrl_pcie: pciegrp {
389*4882a593Smuzhiyun		fsl,pins = <
390*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x130b0
391*4882a593Smuzhiyun		>;
392*4882a593Smuzhiyun	};
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun	pinctrl_pwm3: pwm3grp {
395*4882a593Smuzhiyun		fsl,pins = <
396*4882a593Smuzhiyun			MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
397*4882a593Smuzhiyun		>;
398*4882a593Smuzhiyun	};
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun	pinctrl_uart1: uart1grp {
401*4882a593Smuzhiyun		fsl,pins = <
402*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b0
403*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b0
404*4882a593Smuzhiyun		>;
405*4882a593Smuzhiyun	};
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun	pinctrl_uart3: uart3grp {
408*4882a593Smuzhiyun		fsl,pins = <
409*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D23__UART3_CTS_B   0x1b0b0
410*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b0
411*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b0
412*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D31__UART3_RTS_B   0x1b0b0
413*4882a593Smuzhiyun		>;
414*4882a593Smuzhiyun	};
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun	pinctrl_uart4: uart4grp {
417*4882a593Smuzhiyun		fsl,pins = <
418*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b0
419*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b0
420*4882a593Smuzhiyun		>;
421*4882a593Smuzhiyun	};
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun	pinctrl_usbotg: usbotggrp {
424*4882a593Smuzhiyun		fsl,pins = <
425*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x1b0b0
426*4882a593Smuzhiyun		>;
427*4882a593Smuzhiyun	};
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun	pinctrl_usdhc2: usdhc2grp {
430*4882a593Smuzhiyun		fsl,pins = <
431*4882a593Smuzhiyun			MX6QDL_PAD_SD2_CMD__SD2_CMD    0x17059
432*4882a593Smuzhiyun			MX6QDL_PAD_SD2_CLK__SD2_CLK    0x10059
433*4882a593Smuzhiyun			MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
434*4882a593Smuzhiyun			MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
435*4882a593Smuzhiyun			MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
436*4882a593Smuzhiyun			MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
437*4882a593Smuzhiyun		>;
438*4882a593Smuzhiyun	};
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun	pinctrl_spdif: spdifgrp {
441*4882a593Smuzhiyun		fsl,pins = <
442*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0
443*4882a593Smuzhiyun		>;
444*4882a593Smuzhiyun	};
445*4882a593Smuzhiyun
446*4882a593Smuzhiyun	pinctrl_touchscreen: touchscreengrp {
447*4882a593Smuzhiyun		fsl,pins = <
448*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x1b0b0
449*4882a593Smuzhiyun		>;
450*4882a593Smuzhiyun	};
451*4882a593Smuzhiyun};
452