xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/imx6q-utilite-pro.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * Copyright 2013 CompuLab Ltd.
3*4882a593Smuzhiyun * Copyright 2016 Christopher Spinrath
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Based on the devicetree distributed with the vendor kernel for the
6*4882a593Smuzhiyun * Utilite Pro:
7*4882a593Smuzhiyun *	Copyright 2013 CompuLab Ltd.
8*4882a593Smuzhiyun *	Author: Valentin Raevsky <valentin@compulab.co.il>
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * This file is dual-licensed: you can use it either under the terms
11*4882a593Smuzhiyun * of the GPL or the X11 license, at your option. Note that this dual
12*4882a593Smuzhiyun * licensing only applies to this file, and not this project as a
13*4882a593Smuzhiyun * whole.
14*4882a593Smuzhiyun *
15*4882a593Smuzhiyun *  a) This file is free software; you can redistribute it and/or
16*4882a593Smuzhiyun *     modify it under the terms of the GNU General Public License as
17*4882a593Smuzhiyun *     published by the Free Software Foundation; either version 2 of the
18*4882a593Smuzhiyun *     License, or (at your option) any later version.
19*4882a593Smuzhiyun *
20*4882a593Smuzhiyun *     This file is distributed in the hope that it will be useful,
21*4882a593Smuzhiyun *     but WITHOUT ANY WARRANTY; without even the implied warranty of
22*4882a593Smuzhiyun *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
23*4882a593Smuzhiyun *     GNU General Public License for more details.
24*4882a593Smuzhiyun *
25*4882a593Smuzhiyun * Or, alternatively,
26*4882a593Smuzhiyun *
27*4882a593Smuzhiyun *  b) Permission is hereby granted, free of charge, to any person
28*4882a593Smuzhiyun *     obtaining a copy of this software and associated documentation
29*4882a593Smuzhiyun *     files (the "Software"), to deal in the Software without
30*4882a593Smuzhiyun *     restriction, including without limitation the rights to use,
31*4882a593Smuzhiyun *     copy, modify, merge, publish, distribute, sublicense, and/or
32*4882a593Smuzhiyun *     sell copies of the Software, and to permit persons to whom the
33*4882a593Smuzhiyun *     Software is furnished to do so, subject to the following
34*4882a593Smuzhiyun *     conditions:
35*4882a593Smuzhiyun *
36*4882a593Smuzhiyun *     The above copyright notice and this permission notice shall be
37*4882a593Smuzhiyun *     included in all copies or substantial portions of the Software.
38*4882a593Smuzhiyun *
39*4882a593Smuzhiyun *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
40*4882a593Smuzhiyun *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41*4882a593Smuzhiyun *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42*4882a593Smuzhiyun *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43*4882a593Smuzhiyun *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
44*4882a593Smuzhiyun *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45*4882a593Smuzhiyun *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46*4882a593Smuzhiyun *     OTHER DEALINGS IN THE SOFTWARE.
47*4882a593Smuzhiyun */
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
50*4882a593Smuzhiyun#include "imx6q-cm-fx6.dts"
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun/ {
53*4882a593Smuzhiyun	model = "CompuLab Utilite Pro";
54*4882a593Smuzhiyun	compatible = "compulab,utilite-pro", "compulab,cm-fx6", "fsl,imx6q";
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun	aliases {
57*4882a593Smuzhiyun		ethernet1 = &eth1;
58*4882a593Smuzhiyun		rtc0 = &em3027;
59*4882a593Smuzhiyun		rtc1 = &snvs_rtc;
60*4882a593Smuzhiyun	};
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun	encoder {
63*4882a593Smuzhiyun		compatible = "ti,tfp410";
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun		ports {
66*4882a593Smuzhiyun			#address-cells = <1>;
67*4882a593Smuzhiyun			#size-cells = <0>;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun			port@0 {
70*4882a593Smuzhiyun				reg = <0>;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun				tfp410_in: endpoint {
73*4882a593Smuzhiyun					remote-endpoint = <&parallel_display_out>;
74*4882a593Smuzhiyun				};
75*4882a593Smuzhiyun			};
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun			port@1 {
78*4882a593Smuzhiyun				reg = <1>;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun				tfp410_out: endpoint {
81*4882a593Smuzhiyun					remote-endpoint = <&hdmi_connector_in>;
82*4882a593Smuzhiyun				};
83*4882a593Smuzhiyun			};
84*4882a593Smuzhiyun		};
85*4882a593Smuzhiyun	};
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun	gpio-keys {
88*4882a593Smuzhiyun		compatible = "gpio-keys";
89*4882a593Smuzhiyun		pinctrl-names = "default";
90*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_gpio_keys>;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun		power {
93*4882a593Smuzhiyun			label = "Power Button";
94*4882a593Smuzhiyun			gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
95*4882a593Smuzhiyun			linux,code = <KEY_POWER>;
96*4882a593Smuzhiyun			wakeup-source;
97*4882a593Smuzhiyun		};
98*4882a593Smuzhiyun	};
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun	hdmi-connector {
101*4882a593Smuzhiyun		compatible = "hdmi-connector";
102*4882a593Smuzhiyun		pinctrl-names = "default";
103*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_hpd>;
104*4882a593Smuzhiyun		type = "a";
105*4882a593Smuzhiyun		ddc-i2c-bus = <&i2c_dvi_ddc>;
106*4882a593Smuzhiyun		hpd-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun		port {
109*4882a593Smuzhiyun			hdmi_connector_in: endpoint {
110*4882a593Smuzhiyun				remote-endpoint = <&tfp410_out>;
111*4882a593Smuzhiyun			};
112*4882a593Smuzhiyun		};
113*4882a593Smuzhiyun	};
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun	i2cmux {
116*4882a593Smuzhiyun		compatible = "i2c-mux-gpio";
117*4882a593Smuzhiyun		pinctrl-names = "default";
118*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_i2c1mux>;
119*4882a593Smuzhiyun		#address-cells = <1>;
120*4882a593Smuzhiyun		#size-cells = <0>;
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun		mux-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
123*4882a593Smuzhiyun		i2c-parent = <&i2c1>;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun		i2c@0 {
126*4882a593Smuzhiyun			reg = <0>;
127*4882a593Smuzhiyun			#address-cells = <1>;
128*4882a593Smuzhiyun			#size-cells = <0>;
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun			eeprom@50 {
131*4882a593Smuzhiyun				compatible = "atmel,24c02";
132*4882a593Smuzhiyun				reg = <0x50>;
133*4882a593Smuzhiyun				pagesize = <16>;
134*4882a593Smuzhiyun			};
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun			em3027: rtc@56 {
137*4882a593Smuzhiyun				compatible = "emmicro,em3027";
138*4882a593Smuzhiyun				reg = <0x56>;
139*4882a593Smuzhiyun			};
140*4882a593Smuzhiyun		};
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun		i2c_dvi_ddc: i2c@1 {
143*4882a593Smuzhiyun			reg = <1>;
144*4882a593Smuzhiyun			#address-cells = <1>;
145*4882a593Smuzhiyun			#size-cells = <0>;
146*4882a593Smuzhiyun		};
147*4882a593Smuzhiyun	};
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun	parallel-display {
150*4882a593Smuzhiyun		compatible = "fsl,imx-parallel-display";
151*4882a593Smuzhiyun		#address-cells = <1>;
152*4882a593Smuzhiyun		#size-cells = <0>;
153*4882a593Smuzhiyun		pinctrl-names = "default";
154*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_ipu1>;
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun		interface-pix-fmt = "rgb24";
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun		port@0 {
159*4882a593Smuzhiyun			reg = <0>;
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun			parallel_display_in: endpoint {
162*4882a593Smuzhiyun				remote-endpoint = <&ipu1_di0_disp0>;
163*4882a593Smuzhiyun			};
164*4882a593Smuzhiyun		};
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun		port@1 {
167*4882a593Smuzhiyun			reg = <1>;
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun			parallel_display_out: endpoint {
170*4882a593Smuzhiyun				remote-endpoint = <&tfp410_in>;
171*4882a593Smuzhiyun			};
172*4882a593Smuzhiyun		};
173*4882a593Smuzhiyun	};
174*4882a593Smuzhiyun};
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun/*
177*4882a593Smuzhiyun * A single IPU is not able to drive both display interfaces available on the
178*4882a593Smuzhiyun * Utilite Pro at high resolution due to its bandwidth limitation. Since the
179*4882a593Smuzhiyun * tfp410 encoder is wired up to IPU1, sever the link between IPU1 and the
180*4882a593Smuzhiyun * SoC-internal Designware HDMI encoder forcing the latter to be connected to
181*4882a593Smuzhiyun * IPU2 instead of IPU1.
182*4882a593Smuzhiyun */
183*4882a593Smuzhiyun/delete-node/&ipu1_di0_hdmi;
184*4882a593Smuzhiyun/delete-node/&hdmi_mux_0;
185*4882a593Smuzhiyun/delete-node/&ipu1_di1_hdmi;
186*4882a593Smuzhiyun/delete-node/&hdmi_mux_1;
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun&hdmi {
189*4882a593Smuzhiyun	pinctrl-names = "default";
190*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_hdmicec>;
191*4882a593Smuzhiyun	ddc-i2c-bus = <&i2c2>;
192*4882a593Smuzhiyun	status = "okay";
193*4882a593Smuzhiyun};
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun&i2c1 {
196*4882a593Smuzhiyun	pinctrl-names = "default";
197*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c1>;
198*4882a593Smuzhiyun	status = "okay";
199*4882a593Smuzhiyun};
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun&i2c2 {
202*4882a593Smuzhiyun	pinctrl-names = "default";
203*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c2>;
204*4882a593Smuzhiyun	status = "okay";
205*4882a593Smuzhiyun};
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun&iomuxc {
208*4882a593Smuzhiyun	pinctrl_gpio_keys: gpio_keysgrp {
209*4882a593Smuzhiyun		fsl,pins = <
210*4882a593Smuzhiyun			MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
211*4882a593Smuzhiyun		>;
212*4882a593Smuzhiyun	};
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun	pinctrl_hdmicec: hdmicecgrp {
215*4882a593Smuzhiyun		fsl,pins = <
216*4882a593Smuzhiyun			MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
217*4882a593Smuzhiyun		>;
218*4882a593Smuzhiyun	};
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun	pinctrl_hpd: hpdgrp {
221*4882a593Smuzhiyun		fsl,pins = <
222*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
223*4882a593Smuzhiyun		>;
224*4882a593Smuzhiyun	};
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun	pinctrl_i2c1: i2c1grp {
227*4882a593Smuzhiyun		fsl,pins = <
228*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
229*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
230*4882a593Smuzhiyun		>;
231*4882a593Smuzhiyun	};
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun	pinctrl_i2c1mux: i2c1muxgrp {
234*4882a593Smuzhiyun		fsl,pins = <
235*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
236*4882a593Smuzhiyun		>;
237*4882a593Smuzhiyun	};
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun	pinctrl_i2c2: i2c2grp {
240*4882a593Smuzhiyun		fsl,pins = <
241*4882a593Smuzhiyun			MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
242*4882a593Smuzhiyun			MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
243*4882a593Smuzhiyun		>;
244*4882a593Smuzhiyun	};
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun	pinctrl_ipu1: ipu1grp {
247*4882a593Smuzhiyun		fsl,pins = <
248*4882a593Smuzhiyun			MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x38
249*4882a593Smuzhiyun			MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x38
250*4882a593Smuzhiyun			MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x38
251*4882a593Smuzhiyun			MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x38
252*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x38
253*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x38
254*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x38
255*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x38
256*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x38
257*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x38
258*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x38
259*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x38
260*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x38
261*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x38
262*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x38
263*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x38
264*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x38
265*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x38
266*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x38
267*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x38
268*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x38
269*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x38
270*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x38
271*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x38
272*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x38
273*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x38
274*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x38
275*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x38
276*4882a593Smuzhiyun		>;
277*4882a593Smuzhiyun	};
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun	pinctrl_uart2: uart2grp {
280*4882a593Smuzhiyun		fsl,pins = <
281*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b0b1
282*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b0b1
283*4882a593Smuzhiyun			MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
284*4882a593Smuzhiyun			MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
285*4882a593Smuzhiyun		>;
286*4882a593Smuzhiyun	};
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun	pinctrl_usdhc3: usdhc3grp {
289*4882a593Smuzhiyun		fsl,pins = <
290*4882a593Smuzhiyun			MX6QDL_PAD_SD3_CMD__SD3_CMD	0x17059
291*4882a593Smuzhiyun			MX6QDL_PAD_SD3_CLK__SD3_CLK	0x10059
292*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT0__SD3_DATA0	0x17059
293*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT1__SD3_DATA1	0x17059
294*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT2__SD3_DATA2	0x17059
295*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT3__SD3_DATA3	0x17059
296*4882a593Smuzhiyun		>;
297*4882a593Smuzhiyun	};
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun	pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
300*4882a593Smuzhiyun		fsl,pins = <
301*4882a593Smuzhiyun			MX6QDL_PAD_SD3_CMD__SD3_CMD	0x170B9
302*4882a593Smuzhiyun			MX6QDL_PAD_SD3_CLK__SD3_CLK	0x100B9
303*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT0__SD3_DATA0	0x170B9
304*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT1__SD3_DATA1	0x170B9
305*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT2__SD3_DATA2	0x170B9
306*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT3__SD3_DATA3	0x170B9
307*4882a593Smuzhiyun		>;
308*4882a593Smuzhiyun	};
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun	pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
311*4882a593Smuzhiyun		fsl,pins = <
312*4882a593Smuzhiyun			MX6QDL_PAD_SD3_CMD__SD3_CMD	0x170F9
313*4882a593Smuzhiyun			MX6QDL_PAD_SD3_CLK__SD3_CLK	0x100F9
314*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT0__SD3_DATA0	0x170F9
315*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT1__SD3_DATA1	0x170F9
316*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT2__SD3_DATA2	0x170F9
317*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT3__SD3_DATA3	0x170F9
318*4882a593Smuzhiyun		>;
319*4882a593Smuzhiyun	};
320*4882a593Smuzhiyun};
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun&ipu1_di0_disp0 {
323*4882a593Smuzhiyun	remote-endpoint = <&parallel_display_in>;
324*4882a593Smuzhiyun};
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun&pcie {
327*4882a593Smuzhiyun	pcie@0,0 {
328*4882a593Smuzhiyun		reg = <0x000000 0 0 0 0>;
329*4882a593Smuzhiyun		#address-cells = <3>;
330*4882a593Smuzhiyun		#size-cells = <2>;
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun		/* non-removable i211 ethernet card */
333*4882a593Smuzhiyun		eth1: intel,i211@pcie0,0 {
334*4882a593Smuzhiyun			reg = <0x010000 0 0 0 0>;
335*4882a593Smuzhiyun		};
336*4882a593Smuzhiyun	};
337*4882a593Smuzhiyun};
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun&uart2 {
340*4882a593Smuzhiyun	pinctrl-names = "default";
341*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart2>;
342*4882a593Smuzhiyun	uart-has-rtscts;
343*4882a593Smuzhiyun	status = "okay";
344*4882a593Smuzhiyun};
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun&usdhc3 {
347*4882a593Smuzhiyun	pinctrl-names = "default", "state_100mhz", "state_200mhz";
348*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc3>;
349*4882a593Smuzhiyun	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
350*4882a593Smuzhiyun	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
351*4882a593Smuzhiyun	no-1-8-v;
352*4882a593Smuzhiyun	broken-cd;
353*4882a593Smuzhiyun	keep-power-in-suspend;
354*4882a593Smuzhiyun	status = "okay";
355*4882a593Smuzhiyun};
356