1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0+ OR MIT 2*4882a593Smuzhiyun// 3*4882a593Smuzhiyun// Copyright 2014 Soeren Moch <smoch@web.de> 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun/dts-v1/; 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#include "imx6q.dtsi" 8*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 9*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun model = "TBS2910 Matrix ARM mini PC"; 13*4882a593Smuzhiyun compatible = "tbs,imx6q-tbs2910", "fsl,imx6q"; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun chosen { 16*4882a593Smuzhiyun stdout-path = &uart1; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun aliases { 20*4882a593Smuzhiyun mmc0 = &usdhc2; 21*4882a593Smuzhiyun mmc1 = &usdhc3; 22*4882a593Smuzhiyun mmc2 = &usdhc4; 23*4882a593Smuzhiyun /delete-property/ mmc3; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun memory@10000000 { 27*4882a593Smuzhiyun device_type = "memory"; 28*4882a593Smuzhiyun reg = <0x10000000 0x80000000>; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun fan { 32*4882a593Smuzhiyun compatible = "gpio-fan"; 33*4882a593Smuzhiyun pinctrl-names = "default"; 34*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_gpio_fan>; 35*4882a593Smuzhiyun gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; 36*4882a593Smuzhiyun gpio-fan,speed-map = <0 0 37*4882a593Smuzhiyun 3000 1>; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun ir_recv { 41*4882a593Smuzhiyun compatible = "gpio-ir-receiver"; 42*4882a593Smuzhiyun gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; 43*4882a593Smuzhiyun pinctrl-names = "default"; 44*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_ir>; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun leds { 48*4882a593Smuzhiyun compatible = "gpio-leds"; 49*4882a593Smuzhiyun pinctrl-names = "default"; 50*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_gpio_leds>; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun blue { 53*4882a593Smuzhiyun label = "blue_status_led"; 54*4882a593Smuzhiyun gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; 55*4882a593Smuzhiyun default-state = "keep"; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun reg_2p5v: regulator-2p5v { 60*4882a593Smuzhiyun compatible = "regulator-fixed"; 61*4882a593Smuzhiyun regulator-name = "2P5V"; 62*4882a593Smuzhiyun regulator-min-microvolt = <2500000>; 63*4882a593Smuzhiyun regulator-max-microvolt = <2500000>; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun reg_3p3v: regulator-3p3v { 67*4882a593Smuzhiyun compatible = "regulator-fixed"; 68*4882a593Smuzhiyun regulator-name = "3P3V"; 69*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 70*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun reg_5p0v: regulator-5p0v { 74*4882a593Smuzhiyun compatible = "regulator-fixed"; 75*4882a593Smuzhiyun regulator-name = "5P0V"; 76*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 77*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun sound-sgtl5000 { 81*4882a593Smuzhiyun audio-codec = <&sgtl5000>; 82*4882a593Smuzhiyun audio-routing = 83*4882a593Smuzhiyun "MIC_IN", "Mic Jack", 84*4882a593Smuzhiyun "Mic Jack", "Mic Bias", 85*4882a593Smuzhiyun "Headphone Jack", "HP_OUT"; 86*4882a593Smuzhiyun compatible = "fsl,imx-audio-sgtl5000"; 87*4882a593Smuzhiyun model = "On-board Codec"; 88*4882a593Smuzhiyun mux-ext-port = <3>; 89*4882a593Smuzhiyun mux-int-port = <1>; 90*4882a593Smuzhiyun ssi-controller = <&ssi1>; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun sound-spdif { 94*4882a593Smuzhiyun compatible = "fsl,imx-audio-spdif"; 95*4882a593Smuzhiyun model = "On-board SPDIF"; 96*4882a593Smuzhiyun spdif-controller = <&spdif>; 97*4882a593Smuzhiyun spdif-out; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun}; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun&audmux { 102*4882a593Smuzhiyun status = "okay"; 103*4882a593Smuzhiyun}; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun&fec { 106*4882a593Smuzhiyun pinctrl-names = "default"; 107*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_enet>; 108*4882a593Smuzhiyun phy-mode = "rgmii-id"; 109*4882a593Smuzhiyun phy-handle = <&phy>; 110*4882a593Smuzhiyun status = "okay"; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun mdio { 113*4882a593Smuzhiyun #address-cells = <1>; 114*4882a593Smuzhiyun #size-cells = <0>; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun phy: ethernet-phy@4 { 117*4882a593Smuzhiyun reg = <4>; 118*4882a593Smuzhiyun qca,clk-out-frequency = <125000000>; 119*4882a593Smuzhiyun reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; 120*4882a593Smuzhiyun reset-assert-us = <10000>; 121*4882a593Smuzhiyun }; 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun}; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun&hdmi { 126*4882a593Smuzhiyun pinctrl-names = "default"; 127*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_hdmi>; 128*4882a593Smuzhiyun ddc-i2c-bus = <&i2c2>; 129*4882a593Smuzhiyun status = "okay"; 130*4882a593Smuzhiyun}; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun&i2c1 { 133*4882a593Smuzhiyun clock-frequency = <100000>; 134*4882a593Smuzhiyun pinctrl-names = "default"; 135*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c1>; 136*4882a593Smuzhiyun status = "okay"; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun sgtl5000: sgtl5000@a { 139*4882a593Smuzhiyun clocks = <&clks IMX6QDL_CLK_CKO>; 140*4882a593Smuzhiyun compatible = "fsl,sgtl5000"; 141*4882a593Smuzhiyun pinctrl-names = "default"; 142*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_sgtl5000>; 143*4882a593Smuzhiyun reg = <0x0a>; 144*4882a593Smuzhiyun VDDA-supply = <®_2p5v>; 145*4882a593Smuzhiyun VDDIO-supply = <®_3p3v>; 146*4882a593Smuzhiyun }; 147*4882a593Smuzhiyun}; 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun&i2c2 { 150*4882a593Smuzhiyun clock-frequency = <100000>; 151*4882a593Smuzhiyun pinctrl-names = "default"; 152*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c2>; 153*4882a593Smuzhiyun status = "okay"; 154*4882a593Smuzhiyun}; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun&i2c3 { 157*4882a593Smuzhiyun clock-frequency = <100000>; 158*4882a593Smuzhiyun pinctrl-names = "default"; 159*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c3>; 160*4882a593Smuzhiyun status = "okay"; 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun rtc: ds1307@68 { 163*4882a593Smuzhiyun compatible = "dallas,ds1307"; 164*4882a593Smuzhiyun reg = <0x68>; 165*4882a593Smuzhiyun }; 166*4882a593Smuzhiyun}; 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun&pcie { 169*4882a593Smuzhiyun pinctrl-names = "default"; 170*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pcie>; 171*4882a593Smuzhiyun reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; 172*4882a593Smuzhiyun status = "okay"; 173*4882a593Smuzhiyun}; 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun&sata { 176*4882a593Smuzhiyun fsl,transmit-level-mV = <1104>; 177*4882a593Smuzhiyun fsl,transmit-boost-mdB = <3330>; 178*4882a593Smuzhiyun fsl,transmit-atten-16ths = <16>; 179*4882a593Smuzhiyun fsl,receive-eq-mdB = <3000>; 180*4882a593Smuzhiyun status = "okay"; 181*4882a593Smuzhiyun}; 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun&snvs_poweroff { 184*4882a593Smuzhiyun status = "okay"; 185*4882a593Smuzhiyun}; 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun&spdif { 188*4882a593Smuzhiyun pinctrl-names = "default"; 189*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_spdif>; 190*4882a593Smuzhiyun status = "okay"; 191*4882a593Smuzhiyun}; 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun&ssi1 { 194*4882a593Smuzhiyun status = "okay"; 195*4882a593Smuzhiyun}; 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun&uart1 { 198*4882a593Smuzhiyun pinctrl-names = "default"; 199*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart1>; 200*4882a593Smuzhiyun status = "okay"; 201*4882a593Smuzhiyun}; 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun&uart2 { 204*4882a593Smuzhiyun pinctrl-names = "default"; 205*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart2>; 206*4882a593Smuzhiyun status = "okay"; 207*4882a593Smuzhiyun}; 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun&usbh1 { 210*4882a593Smuzhiyun vbus-supply = <®_5p0v>; 211*4882a593Smuzhiyun status = "okay"; 212*4882a593Smuzhiyun}; 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun&usbotg { 215*4882a593Smuzhiyun vbus-supply = <®_5p0v>; 216*4882a593Smuzhiyun pinctrl-names = "default"; 217*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usbotg>; 218*4882a593Smuzhiyun disable-over-current; 219*4882a593Smuzhiyun status = "okay"; 220*4882a593Smuzhiyun}; 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun&usdhc2 { 223*4882a593Smuzhiyun pinctrl-names = "default"; 224*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc2>; 225*4882a593Smuzhiyun bus-width = <4>; 226*4882a593Smuzhiyun cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; 227*4882a593Smuzhiyun vmmc-supply = <®_3p3v>; 228*4882a593Smuzhiyun vqmmc-supply = <®_3p3v>; 229*4882a593Smuzhiyun voltage-ranges = <3300 3300>; 230*4882a593Smuzhiyun no-1-8-v; 231*4882a593Smuzhiyun status = "okay"; 232*4882a593Smuzhiyun}; 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun&usdhc3 { 235*4882a593Smuzhiyun pinctrl-names = "default"; 236*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc3>; 237*4882a593Smuzhiyun bus-width = <4>; 238*4882a593Smuzhiyun cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; 239*4882a593Smuzhiyun wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; 240*4882a593Smuzhiyun vmmc-supply = <®_3p3v>; 241*4882a593Smuzhiyun vqmmc-supply = <®_3p3v>; 242*4882a593Smuzhiyun voltage-ranges = <3300 3300>; 243*4882a593Smuzhiyun no-1-8-v; 244*4882a593Smuzhiyun status = "okay"; 245*4882a593Smuzhiyun}; 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun&usdhc4 { 248*4882a593Smuzhiyun pinctrl-names = "default"; 249*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc4>; 250*4882a593Smuzhiyun bus-width = <8>; 251*4882a593Smuzhiyun vmmc-supply = <®_3p3v>; 252*4882a593Smuzhiyun vqmmc-supply = <®_3p3v>; 253*4882a593Smuzhiyun voltage-ranges = <3300 3300>; 254*4882a593Smuzhiyun non-removable; 255*4882a593Smuzhiyun no-1-8-v; 256*4882a593Smuzhiyun status = "okay"; 257*4882a593Smuzhiyun}; 258*4882a593Smuzhiyun 259*4882a593Smuzhiyun&iomuxc { 260*4882a593Smuzhiyun pinctrl_enet: enetgrp { 261*4882a593Smuzhiyun fsl,pins = < 262*4882a593Smuzhiyun MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 263*4882a593Smuzhiyun MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 264*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 265*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 266*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 267*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 268*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 269*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 270*4882a593Smuzhiyun MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 271*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 272*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 273*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 274*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 275*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 276*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 277*4882a593Smuzhiyun MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 278*4882a593Smuzhiyun MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b059 279*4882a593Smuzhiyun >; 280*4882a593Smuzhiyun }; 281*4882a593Smuzhiyun 282*4882a593Smuzhiyun pinctrl_gpio_fan: gpiofangrp { 283*4882a593Smuzhiyun fsl,pins = < 284*4882a593Smuzhiyun MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x130b1 285*4882a593Smuzhiyun >; 286*4882a593Smuzhiyun }; 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun pinctrl_gpio_leds: gpioledsgrp { 289*4882a593Smuzhiyun fsl,pins = < 290*4882a593Smuzhiyun MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b1 291*4882a593Smuzhiyun >; 292*4882a593Smuzhiyun }; 293*4882a593Smuzhiyun 294*4882a593Smuzhiyun pinctrl_hdmi: hdmigrp { 295*4882a593Smuzhiyun fsl,pins = < 296*4882a593Smuzhiyun MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 297*4882a593Smuzhiyun >; 298*4882a593Smuzhiyun }; 299*4882a593Smuzhiyun 300*4882a593Smuzhiyun pinctrl_i2c1: i2c1grp { 301*4882a593Smuzhiyun fsl,pins = < 302*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 303*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 304*4882a593Smuzhiyun >; 305*4882a593Smuzhiyun }; 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun pinctrl_i2c2: i2c2grp { 308*4882a593Smuzhiyun fsl,pins = < 309*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 310*4882a593Smuzhiyun MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 311*4882a593Smuzhiyun >; 312*4882a593Smuzhiyun }; 313*4882a593Smuzhiyun 314*4882a593Smuzhiyun pinctrl_i2c3: i2c3grp { 315*4882a593Smuzhiyun fsl,pins = < 316*4882a593Smuzhiyun MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 317*4882a593Smuzhiyun MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 318*4882a593Smuzhiyun >; 319*4882a593Smuzhiyun }; 320*4882a593Smuzhiyun 321*4882a593Smuzhiyun pinctrl_ir: irgrp { 322*4882a593Smuzhiyun fsl,pins = < 323*4882a593Smuzhiyun MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x17059 324*4882a593Smuzhiyun >; 325*4882a593Smuzhiyun }; 326*4882a593Smuzhiyun 327*4882a593Smuzhiyun pinctrl_pcie: pciegrp { 328*4882a593Smuzhiyun fsl,pins = < 329*4882a593Smuzhiyun MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x17059 330*4882a593Smuzhiyun >; 331*4882a593Smuzhiyun }; 332*4882a593Smuzhiyun 333*4882a593Smuzhiyun pinctrl_sgtl5000: sgtl5000grp { 334*4882a593Smuzhiyun fsl,pins = < 335*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 336*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 337*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 338*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 339*4882a593Smuzhiyun MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 340*4882a593Smuzhiyun >; 341*4882a593Smuzhiyun }; 342*4882a593Smuzhiyun 343*4882a593Smuzhiyun pinctrl_spdif: spdifgrp { 344*4882a593Smuzhiyun fsl,pins = <MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x13091 345*4882a593Smuzhiyun >; 346*4882a593Smuzhiyun }; 347*4882a593Smuzhiyun 348*4882a593Smuzhiyun pinctrl_uart1: uart1grp { 349*4882a593Smuzhiyun fsl,pins = < 350*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 351*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 352*4882a593Smuzhiyun >; 353*4882a593Smuzhiyun }; 354*4882a593Smuzhiyun 355*4882a593Smuzhiyun pinctrl_uart2: uart2grp { 356*4882a593Smuzhiyun fsl,pins = < 357*4882a593Smuzhiyun MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 358*4882a593Smuzhiyun MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 359*4882a593Smuzhiyun >; 360*4882a593Smuzhiyun }; 361*4882a593Smuzhiyun 362*4882a593Smuzhiyun pinctrl_usbotg: usbotggrp { 363*4882a593Smuzhiyun fsl,pins = < 364*4882a593Smuzhiyun MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 365*4882a593Smuzhiyun >; 366*4882a593Smuzhiyun }; 367*4882a593Smuzhiyun 368*4882a593Smuzhiyun pinctrl_usdhc2: usdhc2grp { 369*4882a593Smuzhiyun fsl,pins = < 370*4882a593Smuzhiyun MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 371*4882a593Smuzhiyun MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 372*4882a593Smuzhiyun MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 373*4882a593Smuzhiyun MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 374*4882a593Smuzhiyun MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 375*4882a593Smuzhiyun MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 376*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x17059 377*4882a593Smuzhiyun >; 378*4882a593Smuzhiyun }; 379*4882a593Smuzhiyun 380*4882a593Smuzhiyun pinctrl_usdhc3: usdhc3grp { 381*4882a593Smuzhiyun fsl,pins = < 382*4882a593Smuzhiyun MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 383*4882a593Smuzhiyun MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 384*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 385*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 386*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 387*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 388*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x17059 389*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x17059 390*4882a593Smuzhiyun >; 391*4882a593Smuzhiyun }; 392*4882a593Smuzhiyun 393*4882a593Smuzhiyun pinctrl_usdhc4: usdhc4grp { 394*4882a593Smuzhiyun fsl,pins = < 395*4882a593Smuzhiyun MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 396*4882a593Smuzhiyun MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 397*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 398*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 399*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 400*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 401*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 402*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 403*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 404*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 405*4882a593Smuzhiyun >; 406*4882a593Smuzhiyun }; 407*4882a593Smuzhiyun}; 408