1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright 2013 Pavel Machek <pavel@denx.de> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun#include "imx6q.dtsi" 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/ { 10*4882a593Smuzhiyun model = "MicroSys sbc6x board"; 11*4882a593Smuzhiyun compatible = "microsys,sbc6x", "fsl,imx6q"; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun memory@10000000 { 14*4882a593Smuzhiyun device_type = "memory"; 15*4882a593Smuzhiyun reg = <0x10000000 0x80000000>; 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun}; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun&fec { 21*4882a593Smuzhiyun pinctrl-names = "default"; 22*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_enet>; 23*4882a593Smuzhiyun phy-mode = "rgmii"; 24*4882a593Smuzhiyun status = "okay"; 25*4882a593Smuzhiyun}; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun&iomuxc { 28*4882a593Smuzhiyun imx6q-sbc6x { 29*4882a593Smuzhiyun pinctrl_enet: enetgrp { 30*4882a593Smuzhiyun fsl,pins = < 31*4882a593Smuzhiyun MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 32*4882a593Smuzhiyun MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 33*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 34*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 35*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 36*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 37*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 38*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 39*4882a593Smuzhiyun MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 40*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 41*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 42*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 43*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 44*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 45*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 46*4882a593Smuzhiyun MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 47*4882a593Smuzhiyun >; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun pinctrl_uart1: uart1grp { 51*4882a593Smuzhiyun fsl,pins = < 52*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 53*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 54*4882a593Smuzhiyun >; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun pinctrl_usbotg: usbotggrp { 58*4882a593Smuzhiyun fsl,pins = < 59*4882a593Smuzhiyun MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 60*4882a593Smuzhiyun >; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun pinctrl_usdhc3: usdhc3grp { 64*4882a593Smuzhiyun fsl,pins = < 65*4882a593Smuzhiyun MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 66*4882a593Smuzhiyun MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 67*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 68*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 69*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 70*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 71*4882a593Smuzhiyun >; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun}; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun&uart1 { 77*4882a593Smuzhiyun pinctrl-names = "default"; 78*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart1>; 79*4882a593Smuzhiyun status = "okay"; 80*4882a593Smuzhiyun}; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun&usbotg { 83*4882a593Smuzhiyun pinctrl-names = "default"; 84*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usbotg>; 85*4882a593Smuzhiyun disable-over-current; 86*4882a593Smuzhiyun status = "okay"; 87*4882a593Smuzhiyun}; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun&usdhc3 { 90*4882a593Smuzhiyun pinctrl-names = "default"; 91*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc3>; 92*4882a593Smuzhiyun status = "okay"; 93*4882a593Smuzhiyun}; 94