1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright 2015 Sutajio Ko-Usagi PTE LTD 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This file is dual-licensed: you can use it either under the terms 5*4882a593Smuzhiyun * of the GPL or the X11 license, at your option. Note that this dual 6*4882a593Smuzhiyun * licensing only applies to this file, and not this project as a 7*4882a593Smuzhiyun * whole. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * a) This file is free software; you can redistribute it and/or 10*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License as 11*4882a593Smuzhiyun * published by the Free Software Foundation; either version 2 of 12*4882a593Smuzhiyun * the License, or (at your option) any later version. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * This file is distributed in the hope that it will be useful, 15*4882a593Smuzhiyun * but WITHOUT ANY WARRANTY; without even the implied warranty of 16*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17*4882a593Smuzhiyun * GNU General Public License for more details. 18*4882a593Smuzhiyun * 19*4882a593Smuzhiyun * You should have received a copy of the GNU General Public 20*4882a593Smuzhiyun * License along with this file; if not, write to the Free 21*4882a593Smuzhiyun * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 22*4882a593Smuzhiyun * MA 02110-1301 USA 23*4882a593Smuzhiyun * 24*4882a593Smuzhiyun * Or, alternatively, 25*4882a593Smuzhiyun * 26*4882a593Smuzhiyun * b) Permission is hereby granted, free of charge, to any person 27*4882a593Smuzhiyun * obtaining a copy of this software and associated documentation 28*4882a593Smuzhiyun * files (the "Software"), to deal in the Software without 29*4882a593Smuzhiyun * restriction, including without limitation the rights to use, 30*4882a593Smuzhiyun * copy, modify, merge, publish, distribute, sublicense, and/or 31*4882a593Smuzhiyun * sell copies of the Software, and to permit persons to whom the 32*4882a593Smuzhiyun * Software is furnished to do so, subject to the following 33*4882a593Smuzhiyun * conditions: 34*4882a593Smuzhiyun * 35*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be 36*4882a593Smuzhiyun * included in all copies or substantial portions of the Software. 37*4882a593Smuzhiyun * 38*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 39*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 40*4882a593Smuzhiyun * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 41*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 42*4882a593Smuzhiyun * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 43*4882a593Smuzhiyun * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 44*4882a593Smuzhiyun * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 45*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 46*4882a593Smuzhiyun * 47*4882a593Smuzhiyun */ 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun/dts-v1/; 50*4882a593Smuzhiyun#include "imx6q.dtsi" 51*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 52*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun/ { 55*4882a593Smuzhiyun model = "Kosagi Novena Dual/Quad"; 56*4882a593Smuzhiyun compatible = "kosagi,imx6q-novena", "fsl,imx6q"; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* Will be filled by the bootloader */ 59*4882a593Smuzhiyun memory@10000000 { 60*4882a593Smuzhiyun device_type = "memory"; 61*4882a593Smuzhiyun reg = <0x10000000 0>; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun chosen { 65*4882a593Smuzhiyun stdout-path = &uart2; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun backlight: backlight { 69*4882a593Smuzhiyun compatible = "pwm-backlight"; 70*4882a593Smuzhiyun pwms = <&pwm1 0 10000000>; 71*4882a593Smuzhiyun pinctrl-names = "default"; 72*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_backlight_novena>; 73*4882a593Smuzhiyun power-supply = <®_lvds_lcd>; 74*4882a593Smuzhiyun brightness-levels = <0 3 6 12 16 24 32 48 64 96 128 192 255>; 75*4882a593Smuzhiyun default-brightness-level = <12>; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun gpio-keys { 79*4882a593Smuzhiyun compatible = "gpio-keys"; 80*4882a593Smuzhiyun pinctrl-names = "default"; 81*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_gpio_keys_novena>; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun user-button { 84*4882a593Smuzhiyun label = "User Button"; 85*4882a593Smuzhiyun gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; 86*4882a593Smuzhiyun linux,code = <KEY_POWER>; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun lid { 90*4882a593Smuzhiyun label = "Lid"; 91*4882a593Smuzhiyun gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; 92*4882a593Smuzhiyun linux,input-type = <5>; /* EV_SW */ 93*4882a593Smuzhiyun linux,code = <0>; /* SW_LID */ 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun leds { 98*4882a593Smuzhiyun compatible = "gpio-leds"; 99*4882a593Smuzhiyun pinctrl-names = "default"; 100*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_leds_novena>; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun heartbeat { 103*4882a593Smuzhiyun label = "novena:white:panel"; 104*4882a593Smuzhiyun gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; 105*4882a593Smuzhiyun linux,default-trigger = "default-on"; 106*4882a593Smuzhiyun }; 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun panel: panel { 110*4882a593Smuzhiyun compatible = "innolux,n133hse-ea1"; 111*4882a593Smuzhiyun backlight = <&backlight>; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun reg_2p5v: regulator-2p5v { 115*4882a593Smuzhiyun compatible = "regulator-fixed"; 116*4882a593Smuzhiyun regulator-name = "2P5V"; 117*4882a593Smuzhiyun regulator-min-microvolt = <2500000>; 118*4882a593Smuzhiyun regulator-max-microvolt = <2500000>; 119*4882a593Smuzhiyun regulator-always-on; 120*4882a593Smuzhiyun }; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun reg_3p3v: regulator-3p3v { 123*4882a593Smuzhiyun compatible = "regulator-fixed"; 124*4882a593Smuzhiyun regulator-name = "3P3V"; 125*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 126*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 127*4882a593Smuzhiyun regulator-always-on; 128*4882a593Smuzhiyun }; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun reg_audio_codec: regulator-audio-codec { 131*4882a593Smuzhiyun compatible = "regulator-fixed"; 132*4882a593Smuzhiyun regulator-name = "es8328-power"; 133*4882a593Smuzhiyun regulator-boot-on; 134*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 135*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 136*4882a593Smuzhiyun startup-delay-us = <400000>; 137*4882a593Smuzhiyun gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>; 138*4882a593Smuzhiyun enable-active-high; 139*4882a593Smuzhiyun }; 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun reg_display: regulator-display { 142*4882a593Smuzhiyun compatible = "regulator-fixed"; 143*4882a593Smuzhiyun regulator-name = "lcd-display-power"; 144*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 145*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 146*4882a593Smuzhiyun startup-delay-us = <200000>; 147*4882a593Smuzhiyun gpio = <&gpio5 28 GPIO_ACTIVE_HIGH>; 148*4882a593Smuzhiyun enable-active-high; 149*4882a593Smuzhiyun }; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun reg_lvds_lcd: regulator-lvds-lcd { 152*4882a593Smuzhiyun compatible = "regulator-fixed"; 153*4882a593Smuzhiyun regulator-name = "lcd-lvds-power"; 154*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 155*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 156*4882a593Smuzhiyun gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; 157*4882a593Smuzhiyun enable-active-high; 158*4882a593Smuzhiyun }; 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun reg_pcie: regulator-pcie { 161*4882a593Smuzhiyun compatible = "regulator-fixed"; 162*4882a593Smuzhiyun regulator-name = "pcie-bus-power"; 163*4882a593Smuzhiyun regulator-min-microvolt = <1500000>; 164*4882a593Smuzhiyun regulator-max-microvolt = <1500000>; 165*4882a593Smuzhiyun gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; 166*4882a593Smuzhiyun enable-active-high; 167*4882a593Smuzhiyun }; 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun reg_sata: regulator-sata { 170*4882a593Smuzhiyun compatible = "regulator-fixed"; 171*4882a593Smuzhiyun regulator-name = "sata-power"; 172*4882a593Smuzhiyun regulator-boot-on; 173*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 174*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 175*4882a593Smuzhiyun startup-delay-us = <10000>; 176*4882a593Smuzhiyun gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; 177*4882a593Smuzhiyun enable-active-high; 178*4882a593Smuzhiyun }; 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun reg_usb_otg_vbus: regulator-usb-otg-vbus { 181*4882a593Smuzhiyun compatible = "regulator-fixed"; 182*4882a593Smuzhiyun regulator-name = "usb_otg_vbus"; 183*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 184*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 185*4882a593Smuzhiyun enable-active-high; 186*4882a593Smuzhiyun }; 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun sound { 189*4882a593Smuzhiyun compatible = "fsl,imx-audio-es8328"; 190*4882a593Smuzhiyun model = "imx-audio-es8328"; 191*4882a593Smuzhiyun ssi-controller = <&ssi1>; 192*4882a593Smuzhiyun audio-codec = <&codec>; 193*4882a593Smuzhiyun audio-amp-supply = <®_audio_codec>; 194*4882a593Smuzhiyun jack-gpio = <&gpio5 15 GPIO_ACTIVE_HIGH>; 195*4882a593Smuzhiyun audio-routing = 196*4882a593Smuzhiyun "Speaker", "LOUT2", 197*4882a593Smuzhiyun "Speaker", "ROUT2", 198*4882a593Smuzhiyun "Speaker", "audio-amp", 199*4882a593Smuzhiyun "Headphone", "ROUT1", 200*4882a593Smuzhiyun "Headphone", "LOUT1", 201*4882a593Smuzhiyun "LINPUT1", "Mic Jack", 202*4882a593Smuzhiyun "RINPUT1", "Mic Jack", 203*4882a593Smuzhiyun "Mic Jack", "Mic Bias"; 204*4882a593Smuzhiyun mux-int-port = <0x1>; 205*4882a593Smuzhiyun mux-ext-port = <0x3>; 206*4882a593Smuzhiyun }; 207*4882a593Smuzhiyun}; 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun&audmux { 210*4882a593Smuzhiyun pinctrl-names = "default"; 211*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_audmux_novena>; 212*4882a593Smuzhiyun status = "okay"; 213*4882a593Smuzhiyun}; 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun&ecspi3 { 216*4882a593Smuzhiyun pinctrl-names = "default"; 217*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_ecspi3_novena>; 218*4882a593Smuzhiyun status = "okay"; 219*4882a593Smuzhiyun}; 220*4882a593Smuzhiyun 221*4882a593Smuzhiyun&fec { 222*4882a593Smuzhiyun pinctrl-names = "default"; 223*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_enet_novena>; 224*4882a593Smuzhiyun phy-mode = "rgmii"; 225*4882a593Smuzhiyun phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; 226*4882a593Smuzhiyun rxc-skew-ps = <3000>; 227*4882a593Smuzhiyun rxdv-skew-ps = <0>; 228*4882a593Smuzhiyun txc-skew-ps = <3000>; 229*4882a593Smuzhiyun txen-skew-ps = <0>; 230*4882a593Smuzhiyun rxd0-skew-ps = <0>; 231*4882a593Smuzhiyun rxd1-skew-ps = <0>; 232*4882a593Smuzhiyun rxd2-skew-ps = <0>; 233*4882a593Smuzhiyun rxd3-skew-ps = <0>; 234*4882a593Smuzhiyun txd0-skew-ps = <3000>; 235*4882a593Smuzhiyun txd1-skew-ps = <3000>; 236*4882a593Smuzhiyun txd2-skew-ps = <3000>; 237*4882a593Smuzhiyun txd3-skew-ps = <3000>; 238*4882a593Smuzhiyun status = "okay"; 239*4882a593Smuzhiyun}; 240*4882a593Smuzhiyun 241*4882a593Smuzhiyun&hdmi { 242*4882a593Smuzhiyun pinctrl-names = "default"; 243*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_hdmi_novena>; 244*4882a593Smuzhiyun ddc-i2c-bus = <&i2c2>; 245*4882a593Smuzhiyun status = "okay"; 246*4882a593Smuzhiyun}; 247*4882a593Smuzhiyun 248*4882a593Smuzhiyun&i2c1 { 249*4882a593Smuzhiyun pinctrl-names = "default"; 250*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c1_novena>; 251*4882a593Smuzhiyun status = "okay"; 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun accel: mma8452@1c { 254*4882a593Smuzhiyun compatible = "fsl,mma8452"; 255*4882a593Smuzhiyun reg = <0x1c>; 256*4882a593Smuzhiyun }; 257*4882a593Smuzhiyun 258*4882a593Smuzhiyun rtc: pcf8523@68 { 259*4882a593Smuzhiyun compatible = "nxp,pcf8523"; 260*4882a593Smuzhiyun reg = <0x68>; 261*4882a593Smuzhiyun }; 262*4882a593Smuzhiyun 263*4882a593Smuzhiyun sbs_battery: bq20z75@b { 264*4882a593Smuzhiyun compatible = "sbs,sbs-battery"; 265*4882a593Smuzhiyun reg = <0x0b>; 266*4882a593Smuzhiyun sbs,i2c-retry-count = <50>; 267*4882a593Smuzhiyun }; 268*4882a593Smuzhiyun 269*4882a593Smuzhiyun touch: stmpe811@44 { 270*4882a593Smuzhiyun compatible = "st,stmpe811"; 271*4882a593Smuzhiyun reg = <0x44>; 272*4882a593Smuzhiyun irq-gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>; 273*4882a593Smuzhiyun id = <0>; 274*4882a593Smuzhiyun blocks = <0x5>; 275*4882a593Smuzhiyun irq-trigger = <0x1>; 276*4882a593Smuzhiyun pinctrl-names = "default"; 277*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_stmpe_novena>; 278*4882a593Smuzhiyun vio-supply = <®_3p3v>; 279*4882a593Smuzhiyun vcc-supply = <®_3p3v>; 280*4882a593Smuzhiyun 281*4882a593Smuzhiyun stmpe_touchscreen { 282*4882a593Smuzhiyun compatible = "st,stmpe-ts"; 283*4882a593Smuzhiyun st,sample-time = <4>; 284*4882a593Smuzhiyun st,mod-12b = <1>; 285*4882a593Smuzhiyun st,ref-sel = <0>; 286*4882a593Smuzhiyun st,adc-freq = <1>; 287*4882a593Smuzhiyun st,ave-ctrl = <1>; 288*4882a593Smuzhiyun st,touch-det-delay = <2>; 289*4882a593Smuzhiyun st,settling = <2>; 290*4882a593Smuzhiyun st,fraction-z = <7>; 291*4882a593Smuzhiyun st,i-drive = <1>; 292*4882a593Smuzhiyun }; 293*4882a593Smuzhiyun }; 294*4882a593Smuzhiyun}; 295*4882a593Smuzhiyun 296*4882a593Smuzhiyun&i2c2 { 297*4882a593Smuzhiyun pinctrl-names = "default"; 298*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c2_novena>; 299*4882a593Smuzhiyun status = "okay"; 300*4882a593Smuzhiyun 301*4882a593Smuzhiyun pmic: pfuze100@8 { 302*4882a593Smuzhiyun compatible = "fsl,pfuze100"; 303*4882a593Smuzhiyun reg = <0x08>; 304*4882a593Smuzhiyun 305*4882a593Smuzhiyun regulators { 306*4882a593Smuzhiyun reg_sw1a: sw1a { 307*4882a593Smuzhiyun regulator-min-microvolt = <300000>; 308*4882a593Smuzhiyun regulator-max-microvolt = <1875000>; 309*4882a593Smuzhiyun regulator-boot-on; 310*4882a593Smuzhiyun regulator-always-on; 311*4882a593Smuzhiyun regulator-ramp-delay = <6250>; 312*4882a593Smuzhiyun }; 313*4882a593Smuzhiyun 314*4882a593Smuzhiyun reg_sw1c: sw1c { 315*4882a593Smuzhiyun regulator-min-microvolt = <300000>; 316*4882a593Smuzhiyun regulator-max-microvolt = <1875000>; 317*4882a593Smuzhiyun regulator-boot-on; 318*4882a593Smuzhiyun regulator-always-on; 319*4882a593Smuzhiyun }; 320*4882a593Smuzhiyun 321*4882a593Smuzhiyun reg_sw2: sw2 { 322*4882a593Smuzhiyun regulator-min-microvolt = <800000>; 323*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 324*4882a593Smuzhiyun regulator-boot-on; 325*4882a593Smuzhiyun regulator-always-on; 326*4882a593Smuzhiyun }; 327*4882a593Smuzhiyun 328*4882a593Smuzhiyun reg_sw3a: sw3a { 329*4882a593Smuzhiyun regulator-min-microvolt = <400000>; 330*4882a593Smuzhiyun regulator-max-microvolt = <1975000>; 331*4882a593Smuzhiyun regulator-boot-on; 332*4882a593Smuzhiyun regulator-always-on; 333*4882a593Smuzhiyun }; 334*4882a593Smuzhiyun 335*4882a593Smuzhiyun reg_sw3b: sw3b { 336*4882a593Smuzhiyun regulator-min-microvolt = <400000>; 337*4882a593Smuzhiyun regulator-max-microvolt = <1975000>; 338*4882a593Smuzhiyun regulator-boot-on; 339*4882a593Smuzhiyun regulator-always-on; 340*4882a593Smuzhiyun }; 341*4882a593Smuzhiyun 342*4882a593Smuzhiyun reg_sw4: sw4 { 343*4882a593Smuzhiyun regulator-min-microvolt = <800000>; 344*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 345*4882a593Smuzhiyun }; 346*4882a593Smuzhiyun 347*4882a593Smuzhiyun reg_swbst: swbst { 348*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 349*4882a593Smuzhiyun regulator-max-microvolt = <5150000>; 350*4882a593Smuzhiyun regulator-boot-on; 351*4882a593Smuzhiyun }; 352*4882a593Smuzhiyun 353*4882a593Smuzhiyun reg_snvs: vsnvs { 354*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 355*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 356*4882a593Smuzhiyun regulator-boot-on; 357*4882a593Smuzhiyun regulator-always-on; 358*4882a593Smuzhiyun }; 359*4882a593Smuzhiyun 360*4882a593Smuzhiyun reg_vref: vrefddr { 361*4882a593Smuzhiyun regulator-boot-on; 362*4882a593Smuzhiyun regulator-always-on; 363*4882a593Smuzhiyun }; 364*4882a593Smuzhiyun 365*4882a593Smuzhiyun reg_vgen1: vgen1 { 366*4882a593Smuzhiyun regulator-min-microvolt = <800000>; 367*4882a593Smuzhiyun regulator-max-microvolt = <1550000>; 368*4882a593Smuzhiyun }; 369*4882a593Smuzhiyun 370*4882a593Smuzhiyun reg_vgen2: vgen2 { 371*4882a593Smuzhiyun regulator-min-microvolt = <800000>; 372*4882a593Smuzhiyun regulator-max-microvolt = <1550000>; 373*4882a593Smuzhiyun }; 374*4882a593Smuzhiyun 375*4882a593Smuzhiyun reg_vgen3: vgen3 { 376*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 377*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 378*4882a593Smuzhiyun }; 379*4882a593Smuzhiyun 380*4882a593Smuzhiyun reg_vgen4: vgen4 { 381*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 382*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 383*4882a593Smuzhiyun regulator-always-on; 384*4882a593Smuzhiyun }; 385*4882a593Smuzhiyun 386*4882a593Smuzhiyun reg_vgen5: vgen5 { 387*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 388*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 389*4882a593Smuzhiyun regulator-always-on; 390*4882a593Smuzhiyun }; 391*4882a593Smuzhiyun 392*4882a593Smuzhiyun reg_vgen6: vgen6 { 393*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 394*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 395*4882a593Smuzhiyun regulator-always-on; 396*4882a593Smuzhiyun }; 397*4882a593Smuzhiyun }; 398*4882a593Smuzhiyun }; 399*4882a593Smuzhiyun}; 400*4882a593Smuzhiyun 401*4882a593Smuzhiyun&i2c3 { 402*4882a593Smuzhiyun pinctrl-names = "default"; 403*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c3_novena>; 404*4882a593Smuzhiyun status = "okay"; 405*4882a593Smuzhiyun 406*4882a593Smuzhiyun codec: es8328@11 { 407*4882a593Smuzhiyun compatible = "everest,es8328"; 408*4882a593Smuzhiyun reg = <0x11>; 409*4882a593Smuzhiyun DVDD-supply = <®_audio_codec>; 410*4882a593Smuzhiyun AVDD-supply = <®_audio_codec>; 411*4882a593Smuzhiyun PVDD-supply = <®_audio_codec>; 412*4882a593Smuzhiyun HPVDD-supply = <®_audio_codec>; 413*4882a593Smuzhiyun pinctrl-names = "default"; 414*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_sound_novena>; 415*4882a593Smuzhiyun clocks = <&clks IMX6QDL_CLK_CKO1>; 416*4882a593Smuzhiyun assigned-clocks = <&clks IMX6QDL_CLK_CKO>, 417*4882a593Smuzhiyun <&clks IMX6QDL_CLK_CKO1_SEL>, 418*4882a593Smuzhiyun <&clks IMX6QDL_CLK_PLL4_AUDIO>, 419*4882a593Smuzhiyun <&clks IMX6QDL_CLK_CKO1>; 420*4882a593Smuzhiyun assigned-clock-parents = <&clks IMX6QDL_CLK_CKO1>, 421*4882a593Smuzhiyun <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>, 422*4882a593Smuzhiyun <&clks IMX6QDL_CLK_OSC>, 423*4882a593Smuzhiyun <&clks IMX6QDL_CLK_CKO1_PODF>; 424*4882a593Smuzhiyun assigned-clock-rates = <0 0 722534400 22579200>; 425*4882a593Smuzhiyun }; 426*4882a593Smuzhiyun}; 427*4882a593Smuzhiyun 428*4882a593Smuzhiyun&kpp { 429*4882a593Smuzhiyun pinctrl-names = "default"; 430*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_kpp_novena>; 431*4882a593Smuzhiyun linux,keymap = < 432*4882a593Smuzhiyun MATRIX_KEY(1, 1, KEY_CONFIG) 433*4882a593Smuzhiyun >; 434*4882a593Smuzhiyun status = "okay"; 435*4882a593Smuzhiyun}; 436*4882a593Smuzhiyun 437*4882a593Smuzhiyun&ldb { 438*4882a593Smuzhiyun fsl,dual-channel; 439*4882a593Smuzhiyun status = "okay"; 440*4882a593Smuzhiyun 441*4882a593Smuzhiyun lvds-channel@0 { 442*4882a593Smuzhiyun fsl,data-mapping = "jeida"; 443*4882a593Smuzhiyun fsl,data-width = <24>; 444*4882a593Smuzhiyun fsl,panel = <&panel>; 445*4882a593Smuzhiyun status = "okay"; 446*4882a593Smuzhiyun }; 447*4882a593Smuzhiyun}; 448*4882a593Smuzhiyun 449*4882a593Smuzhiyun&pcie { 450*4882a593Smuzhiyun pinctrl-names = "default"; 451*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pcie_novena>; 452*4882a593Smuzhiyun reset-gpio = <&gpio3 29 GPIO_ACTIVE_LOW>; 453*4882a593Smuzhiyun vpcie-supply = <®_pcie>; 454*4882a593Smuzhiyun status = "okay"; 455*4882a593Smuzhiyun}; 456*4882a593Smuzhiyun 457*4882a593Smuzhiyun&pwm1 { 458*4882a593Smuzhiyun #pwm-cells = <2>; 459*4882a593Smuzhiyun status = "okay"; 460*4882a593Smuzhiyun}; 461*4882a593Smuzhiyun 462*4882a593Smuzhiyun&sata { 463*4882a593Smuzhiyun target-supply = <®_sata>; 464*4882a593Smuzhiyun fsl,transmit-level-mV = <1025>; 465*4882a593Smuzhiyun fsl,transmit-boost-mdB = <0>; 466*4882a593Smuzhiyun fsl,transmit-atten-16ths = <8>; 467*4882a593Smuzhiyun status = "okay"; 468*4882a593Smuzhiyun}; 469*4882a593Smuzhiyun 470*4882a593Smuzhiyun&ssi1 { 471*4882a593Smuzhiyun status = "okay"; 472*4882a593Smuzhiyun}; 473*4882a593Smuzhiyun 474*4882a593Smuzhiyun&uart2 { 475*4882a593Smuzhiyun pinctrl-names = "default"; 476*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart2_novena>; 477*4882a593Smuzhiyun status = "okay"; 478*4882a593Smuzhiyun}; 479*4882a593Smuzhiyun 480*4882a593Smuzhiyun&uart3 { 481*4882a593Smuzhiyun pinctrl-names = "default"; 482*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart3_novena>; 483*4882a593Smuzhiyun status = "okay"; 484*4882a593Smuzhiyun}; 485*4882a593Smuzhiyun 486*4882a593Smuzhiyun&uart4 { 487*4882a593Smuzhiyun pinctrl-names = "default"; 488*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart4_novena>; 489*4882a593Smuzhiyun status = "okay"; 490*4882a593Smuzhiyun}; 491*4882a593Smuzhiyun 492*4882a593Smuzhiyun&usbotg { 493*4882a593Smuzhiyun vbus-supply = <®_usb_otg_vbus>; 494*4882a593Smuzhiyun dr_mode = "otg"; 495*4882a593Smuzhiyun pinctrl-names = "default"; 496*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usbotg_novena>; 497*4882a593Smuzhiyun disable-over-current; 498*4882a593Smuzhiyun status = "okay"; 499*4882a593Smuzhiyun}; 500*4882a593Smuzhiyun 501*4882a593Smuzhiyun&usbh1 { 502*4882a593Smuzhiyun vbus-supply = <®_swbst>; 503*4882a593Smuzhiyun status = "okay"; 504*4882a593Smuzhiyun}; 505*4882a593Smuzhiyun 506*4882a593Smuzhiyun&usdhc2 { 507*4882a593Smuzhiyun pinctrl-names = "default"; 508*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc2_novena>; 509*4882a593Smuzhiyun cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; 510*4882a593Smuzhiyun wp-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; 511*4882a593Smuzhiyun bus-width = <4>; 512*4882a593Smuzhiyun status = "okay"; 513*4882a593Smuzhiyun}; 514*4882a593Smuzhiyun 515*4882a593Smuzhiyun&usdhc3 { 516*4882a593Smuzhiyun pinctrl-names = "default"; 517*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc3_novena>; 518*4882a593Smuzhiyun bus-width = <4>; 519*4882a593Smuzhiyun non-removable; 520*4882a593Smuzhiyun status = "okay"; 521*4882a593Smuzhiyun}; 522*4882a593Smuzhiyun 523*4882a593Smuzhiyun&iomuxc { 524*4882a593Smuzhiyun pinctrl_audmux_novena: audmuxgrp-novena { 525*4882a593Smuzhiyun fsl,pins = < 526*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 527*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 528*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 529*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 530*4882a593Smuzhiyun >; 531*4882a593Smuzhiyun }; 532*4882a593Smuzhiyun 533*4882a593Smuzhiyun pinctrl_backlight_novena: backlightgrp-novena { 534*4882a593Smuzhiyun fsl,pins = < 535*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0 536*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x1b0b1 537*4882a593Smuzhiyun MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b1 538*4882a593Smuzhiyun >; 539*4882a593Smuzhiyun }; 540*4882a593Smuzhiyun 541*4882a593Smuzhiyun pinctrl_ecspi3_novena: ecspi3grp-novena { 542*4882a593Smuzhiyun fsl,pins = < 543*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 544*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 545*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 546*4882a593Smuzhiyun >; 547*4882a593Smuzhiyun }; 548*4882a593Smuzhiyun 549*4882a593Smuzhiyun pinctrl_enet_novena: enetgrp-novena { 550*4882a593Smuzhiyun fsl,pins = < 551*4882a593Smuzhiyun MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 552*4882a593Smuzhiyun MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 553*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b020 554*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b028 555*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b028 556*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b028 557*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b028 558*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b028 559*4882a593Smuzhiyun MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 560*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 561*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 562*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 563*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 564*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 565*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 566*4882a593Smuzhiyun MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 567*4882a593Smuzhiyun /* Ethernet reset */ 568*4882a593Smuzhiyun MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b1 569*4882a593Smuzhiyun >; 570*4882a593Smuzhiyun }; 571*4882a593Smuzhiyun 572*4882a593Smuzhiyun pinctrl_fpga_gpio: fpgagpiogrp-novena { 573*4882a593Smuzhiyun fsl,pins = < 574*4882a593Smuzhiyun /* FPGA power */ 575*4882a593Smuzhiyun MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b1 576*4882a593Smuzhiyun /* Reset */ 577*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b1 578*4882a593Smuzhiyun /* FPGA GPIOs */ 579*4882a593Smuzhiyun MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b1 580*4882a593Smuzhiyun MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b0b1 581*4882a593Smuzhiyun MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b1 582*4882a593Smuzhiyun MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b0b1 583*4882a593Smuzhiyun MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b1 584*4882a593Smuzhiyun MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b1 585*4882a593Smuzhiyun MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b0b1 586*4882a593Smuzhiyun MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b1 587*4882a593Smuzhiyun MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b0b1 588*4882a593Smuzhiyun MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b0b1 589*4882a593Smuzhiyun MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b0b1 590*4882a593Smuzhiyun MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x1b0b1 591*4882a593Smuzhiyun MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x1b0b1 592*4882a593Smuzhiyun MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b1 593*4882a593Smuzhiyun MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x1b0b1 594*4882a593Smuzhiyun MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1b0b1 595*4882a593Smuzhiyun MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b1 596*4882a593Smuzhiyun MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b1 597*4882a593Smuzhiyun MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 598*4882a593Smuzhiyun MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b1 599*4882a593Smuzhiyun MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b1 600*4882a593Smuzhiyun MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b1 601*4882a593Smuzhiyun MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x1b0b1 602*4882a593Smuzhiyun MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b1 603*4882a593Smuzhiyun MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b1 604*4882a593Smuzhiyun MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b1 605*4882a593Smuzhiyun >; 606*4882a593Smuzhiyun }; 607*4882a593Smuzhiyun 608*4882a593Smuzhiyun pinctrl_fpga_eim: fpgaeimgrp-novena { 609*4882a593Smuzhiyun fsl,pins = < 610*4882a593Smuzhiyun /* FPGA power */ 611*4882a593Smuzhiyun MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b1 612*4882a593Smuzhiyun /* Reset */ 613*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b1 614*4882a593Smuzhiyun /* FPGA GPIOs */ 615*4882a593Smuzhiyun MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0f1 616*4882a593Smuzhiyun MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0f1 617*4882a593Smuzhiyun MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0f1 618*4882a593Smuzhiyun MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0f1 619*4882a593Smuzhiyun MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0f1 620*4882a593Smuzhiyun MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0f1 621*4882a593Smuzhiyun MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0f1 622*4882a593Smuzhiyun MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0f1 623*4882a593Smuzhiyun MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0f1 624*4882a593Smuzhiyun MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0f1 625*4882a593Smuzhiyun MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0f1 626*4882a593Smuzhiyun MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0f1 627*4882a593Smuzhiyun MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0f1 628*4882a593Smuzhiyun MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0f1 629*4882a593Smuzhiyun MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0f1 630*4882a593Smuzhiyun MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0f1 631*4882a593Smuzhiyun MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0f1 632*4882a593Smuzhiyun MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0f1 633*4882a593Smuzhiyun MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0f1 634*4882a593Smuzhiyun MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0f1 635*4882a593Smuzhiyun MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0f1 636*4882a593Smuzhiyun MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0xb0f1 637*4882a593Smuzhiyun MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0f1 638*4882a593Smuzhiyun MX6QDL_PAD_EIM_RW__EIM_RW 0xb0f1 639*4882a593Smuzhiyun MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb0f1 640*4882a593Smuzhiyun MX6QDL_PAD_EIM_BCLK__EIM_BCLK 0xb0f1 641*4882a593Smuzhiyun >; 642*4882a593Smuzhiyun }; 643*4882a593Smuzhiyun 644*4882a593Smuzhiyun pinctrl_gpio_keys_novena: gpiokeysgrp-novena { 645*4882a593Smuzhiyun fsl,pins = < 646*4882a593Smuzhiyun /* User button */ 647*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 648*4882a593Smuzhiyun /* PCIe Wakeup */ 649*4882a593Smuzhiyun MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1f0e0 650*4882a593Smuzhiyun /* Lid switch */ 651*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0 652*4882a593Smuzhiyun >; 653*4882a593Smuzhiyun }; 654*4882a593Smuzhiyun 655*4882a593Smuzhiyun pinctrl_hdmi_novena: hdmigrp-novena { 656*4882a593Smuzhiyun fsl,pins = < 657*4882a593Smuzhiyun MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 658*4882a593Smuzhiyun MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b1 659*4882a593Smuzhiyun >; 660*4882a593Smuzhiyun }; 661*4882a593Smuzhiyun 662*4882a593Smuzhiyun pinctrl_i2c1_novena: i2c1grp-novena { 663*4882a593Smuzhiyun fsl,pins = < 664*4882a593Smuzhiyun MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 665*4882a593Smuzhiyun MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 666*4882a593Smuzhiyun >; 667*4882a593Smuzhiyun }; 668*4882a593Smuzhiyun 669*4882a593Smuzhiyun pinctrl_i2c2_novena: i2c2grp-novena { 670*4882a593Smuzhiyun fsl,pins = < 671*4882a593Smuzhiyun MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 672*4882a593Smuzhiyun MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 673*4882a593Smuzhiyun >; 674*4882a593Smuzhiyun }; 675*4882a593Smuzhiyun 676*4882a593Smuzhiyun pinctrl_i2c3_novena: i2c3grp-novena { 677*4882a593Smuzhiyun fsl,pins = < 678*4882a593Smuzhiyun MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 679*4882a593Smuzhiyun MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 680*4882a593Smuzhiyun >; 681*4882a593Smuzhiyun }; 682*4882a593Smuzhiyun 683*4882a593Smuzhiyun pinctrl_kpp_novena: kppgrp-novena { 684*4882a593Smuzhiyun fsl,pins = < 685*4882a593Smuzhiyun /* Front panel button */ 686*4882a593Smuzhiyun MX6QDL_PAD_KEY_ROW1__KEY_ROW1 0x1b0b1 687*4882a593Smuzhiyun /* Fake column driver, not connected */ 688*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL1__KEY_COL1 0x1b0b1 689*4882a593Smuzhiyun >; 690*4882a593Smuzhiyun }; 691*4882a593Smuzhiyun 692*4882a593Smuzhiyun pinctrl_leds_novena: ledsgrp-novena { 693*4882a593Smuzhiyun fsl,pins = < 694*4882a593Smuzhiyun MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x1b0b1 695*4882a593Smuzhiyun >; 696*4882a593Smuzhiyun }; 697*4882a593Smuzhiyun 698*4882a593Smuzhiyun pinctrl_pcie_novena: pciegrp-novena { 699*4882a593Smuzhiyun fsl,pins = < 700*4882a593Smuzhiyun /* Reset */ 701*4882a593Smuzhiyun MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b1 702*4882a593Smuzhiyun /* Power On */ 703*4882a593Smuzhiyun MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1 704*4882a593Smuzhiyun /* Wifi kill */ 705*4882a593Smuzhiyun MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b0b1 706*4882a593Smuzhiyun >; 707*4882a593Smuzhiyun }; 708*4882a593Smuzhiyun 709*4882a593Smuzhiyun pinctrl_sata_novena: satagrp-novena { 710*4882a593Smuzhiyun fsl,pins = < 711*4882a593Smuzhiyun MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b1 712*4882a593Smuzhiyun >; 713*4882a593Smuzhiyun }; 714*4882a593Smuzhiyun 715*4882a593Smuzhiyun pinctrl_senoko_novena: senokogrp-novena { 716*4882a593Smuzhiyun fsl,pins = < 717*4882a593Smuzhiyun /* Senoko IRQ line */ 718*4882a593Smuzhiyun MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x13048 719*4882a593Smuzhiyun /* Senoko reset line */ 720*4882a593Smuzhiyun MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b1 721*4882a593Smuzhiyun >; 722*4882a593Smuzhiyun }; 723*4882a593Smuzhiyun 724*4882a593Smuzhiyun pinctrl_sound_novena: soundgrp-novena { 725*4882a593Smuzhiyun fsl,pins = < 726*4882a593Smuzhiyun /* Audio power regulator */ 727*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b1 728*4882a593Smuzhiyun /* Headphone plug */ 729*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b1 730*4882a593Smuzhiyun MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 731*4882a593Smuzhiyun >; 732*4882a593Smuzhiyun }; 733*4882a593Smuzhiyun 734*4882a593Smuzhiyun pinctrl_stmpe_novena: stmpegrp-novena { 735*4882a593Smuzhiyun fsl,pins = < 736*4882a593Smuzhiyun /* Touchscreen interrupt */ 737*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b1 738*4882a593Smuzhiyun >; 739*4882a593Smuzhiyun }; 740*4882a593Smuzhiyun 741*4882a593Smuzhiyun pinctrl_uart2_novena: uart2grp-novena { 742*4882a593Smuzhiyun fsl,pins = < 743*4882a593Smuzhiyun MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 744*4882a593Smuzhiyun MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 745*4882a593Smuzhiyun >; 746*4882a593Smuzhiyun }; 747*4882a593Smuzhiyun 748*4882a593Smuzhiyun pinctrl_uart3_novena: uart3grp-novena { 749*4882a593Smuzhiyun fsl,pins = < 750*4882a593Smuzhiyun MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 751*4882a593Smuzhiyun MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 752*4882a593Smuzhiyun >; 753*4882a593Smuzhiyun }; 754*4882a593Smuzhiyun 755*4882a593Smuzhiyun pinctrl_uart4_novena: uart4grp-novena { 756*4882a593Smuzhiyun fsl,pins = < 757*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 758*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 759*4882a593Smuzhiyun >; 760*4882a593Smuzhiyun }; 761*4882a593Smuzhiyun 762*4882a593Smuzhiyun pinctrl_usbotg_novena: usbotggrp-novena { 763*4882a593Smuzhiyun fsl,pins = < 764*4882a593Smuzhiyun MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 765*4882a593Smuzhiyun >; 766*4882a593Smuzhiyun }; 767*4882a593Smuzhiyun 768*4882a593Smuzhiyun pinctrl_usdhc2_novena: usdhc2grp-novena { 769*4882a593Smuzhiyun fsl,pins = < 770*4882a593Smuzhiyun MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 771*4882a593Smuzhiyun MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 772*4882a593Smuzhiyun MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 773*4882a593Smuzhiyun MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 774*4882a593Smuzhiyun MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 775*4882a593Smuzhiyun MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 776*4882a593Smuzhiyun /* Write protect */ 777*4882a593Smuzhiyun MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1 778*4882a593Smuzhiyun /* Card detect */ 779*4882a593Smuzhiyun MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b1 780*4882a593Smuzhiyun >; 781*4882a593Smuzhiyun }; 782*4882a593Smuzhiyun 783*4882a593Smuzhiyun pinctrl_usdhc3_novena: usdhc3grp-novena { 784*4882a593Smuzhiyun fsl,pins = < 785*4882a593Smuzhiyun MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 786*4882a593Smuzhiyun MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 787*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 788*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 789*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 790*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 791*4882a593Smuzhiyun >; 792*4882a593Smuzhiyun }; 793*4882a593Smuzhiyun}; 794