1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright 2013 Gateworks Corporation 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun#include "imx6q.dtsi" 8*4882a593Smuzhiyun#include "imx6qdl-gw53xx.dtsi" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun model = "Gateworks Ventana i.MX6 Dual/Quad GW53XX"; 12*4882a593Smuzhiyun compatible = "gw,imx6q-gw53xx", "gw,ventana", "fsl,imx6q"; 13*4882a593Smuzhiyun}; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun&i2c3 { 16*4882a593Smuzhiyun adv7180: camera@20 { 17*4882a593Smuzhiyun compatible = "adi,adv7180"; 18*4882a593Smuzhiyun pinctrl-names = "default"; 19*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_adv7180>; 20*4882a593Smuzhiyun reg = <0x20>; 21*4882a593Smuzhiyun powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; 22*4882a593Smuzhiyun interrupt-parent = <&gpio3>; 23*4882a593Smuzhiyun interrupts = <30 IRQ_TYPE_LEVEL_LOW>; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun port { 26*4882a593Smuzhiyun adv7180_to_ipu2_csi1_mux: endpoint { 27*4882a593Smuzhiyun remote-endpoint = <&ipu2_csi1_mux_from_parallel_sensor>; 28*4882a593Smuzhiyun bus-width = <8>; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun}; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun&ipu2_csi1_from_ipu2_csi1_mux { 35*4882a593Smuzhiyun bus-width = <8>; 36*4882a593Smuzhiyun}; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun&ipu2_csi1_mux_from_parallel_sensor { 39*4882a593Smuzhiyun remote-endpoint = <&adv7180_to_ipu2_csi1_mux>; 40*4882a593Smuzhiyun bus-width = <8>; 41*4882a593Smuzhiyun}; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun&ipu2_csi1 { 44*4882a593Smuzhiyun pinctrl-names = "default"; 45*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_ipu2_csi1>; 46*4882a593Smuzhiyun}; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun&sata { 49*4882a593Smuzhiyun status = "okay"; 50*4882a593Smuzhiyun}; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun&iomuxc { 53*4882a593Smuzhiyun pinctrl_adv7180: adv7180grp { 54*4882a593Smuzhiyun fsl,pins = < 55*4882a593Smuzhiyun MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0 56*4882a593Smuzhiyun MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0 57*4882a593Smuzhiyun >; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun pinctrl_ipu2_csi1: ipu2_csi1grp { 61*4882a593Smuzhiyun fsl,pins = < 62*4882a593Smuzhiyun MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b0 63*4882a593Smuzhiyun MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x1b0b0 64*4882a593Smuzhiyun MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x1b0b0 65*4882a593Smuzhiyun MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x1b0b0 66*4882a593Smuzhiyun MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x1b0b0 67*4882a593Smuzhiyun MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x1b0b0 68*4882a593Smuzhiyun MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x1b0b0 69*4882a593Smuzhiyun MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x1b0b0 70*4882a593Smuzhiyun MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x1b0b0 71*4882a593Smuzhiyun MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x1b0b0 72*4882a593Smuzhiyun MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x1b0b0 73*4882a593Smuzhiyun >; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun}; 76