1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright 2017 3*4882a593Smuzhiyun * Lukasz Majewski, DENX Software Engineering, lukma@denx.de 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This file is dual-licensed: you can use it either under the terms 6*4882a593Smuzhiyun * of the GPL or the X11 license, at your option. Note that this dual 7*4882a593Smuzhiyun * licensing only applies to this file, and not this project as a 8*4882a593Smuzhiyun * whole. 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * a) This file is licensed under the terms of the GNU General Public 11*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without 12*4882a593Smuzhiyun * any warranty of any kind, whether express or implied. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * Or, alternatively, 15*4882a593Smuzhiyun * 16*4882a593Smuzhiyun * b) Permission is hereby granted, free of charge, to any person 17*4882a593Smuzhiyun * obtaining a copy of this software and associated documentation 18*4882a593Smuzhiyun * files (the "Software"), to deal in the Software without 19*4882a593Smuzhiyun * restriction, including without limitation the rights to use, 20*4882a593Smuzhiyun * copy, modify, merge, publish, distribute, sublicense, and/or 21*4882a593Smuzhiyun * sell copies of the Software, and to permit persons to whom the 22*4882a593Smuzhiyun * Software is furnished to do so, subject to the following 23*4882a593Smuzhiyun * conditions: 24*4882a593Smuzhiyun * 25*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be 26*4882a593Smuzhiyun * included in all copies or substantial portions of the Software. 27*4882a593Smuzhiyun * 28*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 29*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 30*4882a593Smuzhiyun * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 31*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 32*4882a593Smuzhiyun * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 33*4882a593Smuzhiyun * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 34*4882a593Smuzhiyun * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 35*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 36*4882a593Smuzhiyun */ 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun/dts-v1/; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun#include "imx6q.dtsi" 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 43*4882a593Smuzhiyun#include <dt-bindings/pwm/pwm.h> 44*4882a593Smuzhiyun#include <dt-bindings/sound/fsl-imx-audmux.h> 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun/ { 47*4882a593Smuzhiyun model = "Liebherr (LWN) display5 i.MX6 Quad Board"; 48*4882a593Smuzhiyun compatible = "lwn,display5", "fsl,imx6q"; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun memory@10000000 { 51*4882a593Smuzhiyun device_type = "memory"; 52*4882a593Smuzhiyun reg = <0x10000000 0x40000000>; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun backlight_lvds: backlight { 56*4882a593Smuzhiyun compatible = "pwm-backlight"; 57*4882a593Smuzhiyun pinctrl-names = "default"; 58*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_backlight>; 59*4882a593Smuzhiyun pwms = <&pwm2 0 5000000 0>; 60*4882a593Smuzhiyun brightness-levels = < 0 1 2 3 4 5 6 7 8 9 61*4882a593Smuzhiyun 10 11 12 13 14 15 16 17 18 19 62*4882a593Smuzhiyun 20 21 22 23 24 25 26 27 28 29 63*4882a593Smuzhiyun 30 31 32 33 34 35 36 37 38 39 64*4882a593Smuzhiyun 40 41 42 43 44 45 46 47 48 49 65*4882a593Smuzhiyun 50 51 52 53 54 55 56 57 58 59 66*4882a593Smuzhiyun 60 61 62 63 64 65 66 67 68 69 67*4882a593Smuzhiyun 70 71 72 73 74 75 76 77 78 79 68*4882a593Smuzhiyun 80 81 82 83 84 85 86 87 88 89 69*4882a593Smuzhiyun 90 91 92 93 94 95 96 97 98 99 70*4882a593Smuzhiyun 100 101 102 103 104 105 106 107 108 109 71*4882a593Smuzhiyun 110 111 112 113 114 115 116 117 118 119 72*4882a593Smuzhiyun 120 121 122 123 124 125 126 127 128 129 73*4882a593Smuzhiyun 130 131 132 133 134 135 136 137 138 139 74*4882a593Smuzhiyun 140 141 142 143 144 145 146 147 148 149 75*4882a593Smuzhiyun 150 151 152 153 154 155 156 157 158 159 76*4882a593Smuzhiyun 160 161 162 163 164 165 166 167 168 169 77*4882a593Smuzhiyun 170 171 172 173 174 175 176 177 178 179 78*4882a593Smuzhiyun 180 181 182 183 184 185 186 187 188 189 79*4882a593Smuzhiyun 190 191 192 193 194 195 196 197 198 199 80*4882a593Smuzhiyun 200 201 202 203 204 205 206 207 208 209 81*4882a593Smuzhiyun 210 211 212 213 214 215 216 217 218 219 82*4882a593Smuzhiyun 220 221 222 223 224 225 226 227 228 229 83*4882a593Smuzhiyun 230 231 232 233 234 235 236 237 238 239 84*4882a593Smuzhiyun 240 241 242 243 244 245 246 247 248 249 85*4882a593Smuzhiyun 250 251 252 253 254 255>; 86*4882a593Smuzhiyun default-brightness-level = <250>; 87*4882a593Smuzhiyun enable-gpios = <&gpio5 7 GPIO_ACTIVE_HIGH>; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun reg_lvds: regulator-lvds { 91*4882a593Smuzhiyun compatible = "regulator-fixed"; 92*4882a593Smuzhiyun regulator-name = "lvds_ppen"; 93*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 94*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 95*4882a593Smuzhiyun regulator-boot-on; 96*4882a593Smuzhiyun regulator-always-on; 97*4882a593Smuzhiyun pinctrl-names = "default"; 98*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_reg_lvds>; 99*4882a593Smuzhiyun gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>; 100*4882a593Smuzhiyun enable-active-high; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun reg_usbh1_vbus: usb-h1-vbus { 104*4882a593Smuzhiyun compatible = "regulator-fixed"; 105*4882a593Smuzhiyun gpio = <&gpio3 31 GPIO_ACTIVE_LOW>; 106*4882a593Smuzhiyun pinctrl-names = "default"; 107*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usbh1_vbus>; 108*4882a593Smuzhiyun regulator-name = "usb_h1_vbus"; 109*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 110*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 111*4882a593Smuzhiyun regulator-enable-ramp-delay = <300000>; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun sound { 115*4882a593Smuzhiyun compatible = "simple-audio-card"; 116*4882a593Smuzhiyun label = "tfa9879-mono"; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun simple-audio-card,dai-link { 119*4882a593Smuzhiyun /* DAC */ 120*4882a593Smuzhiyun format = "i2s"; 121*4882a593Smuzhiyun bitclock-master = <&dailink_master>; 122*4882a593Smuzhiyun frame-master = <&dailink_master>; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun dailink_master: cpu { 125*4882a593Smuzhiyun sound-dai = <&ssi2>; 126*4882a593Smuzhiyun }; 127*4882a593Smuzhiyun codec { 128*4882a593Smuzhiyun sound-dai = <&codec>; 129*4882a593Smuzhiyun }; 130*4882a593Smuzhiyun }; 131*4882a593Smuzhiyun }; 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun panel: panel-lvds0 { 134*4882a593Smuzhiyun backlight = <&backlight_lvds>; 135*4882a593Smuzhiyun power-supply = <®_lvds>; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun port { 138*4882a593Smuzhiyun panel_in_lvds0: endpoint { 139*4882a593Smuzhiyun remote-endpoint = <&lvds0_out>; 140*4882a593Smuzhiyun }; 141*4882a593Smuzhiyun }; 142*4882a593Smuzhiyun }; 143*4882a593Smuzhiyun}; 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun&audmux { 146*4882a593Smuzhiyun pinctrl-names = "default"; 147*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_audmux>; 148*4882a593Smuzhiyun status = "okay"; 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun ssi2 { 151*4882a593Smuzhiyun fsl,audmux-port = <1>; 152*4882a593Smuzhiyun fsl,port-config = < 153*4882a593Smuzhiyun (IMX_AUDMUX_V2_PTCR_SYN | 154*4882a593Smuzhiyun IMX_AUDMUX_V2_PTCR_TFSEL(5) | 155*4882a593Smuzhiyun IMX_AUDMUX_V2_PTCR_TCSEL(5) | 156*4882a593Smuzhiyun IMX_AUDMUX_V2_PTCR_TFSDIR | 157*4882a593Smuzhiyun IMX_AUDMUX_V2_PTCR_TCLKDIR) 158*4882a593Smuzhiyun IMX_AUDMUX_V2_PDCR_RXDSEL(5) 159*4882a593Smuzhiyun >; 160*4882a593Smuzhiyun }; 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun aud6 { 163*4882a593Smuzhiyun fsl,audmux-port = <5>; 164*4882a593Smuzhiyun fsl,port-config = < 165*4882a593Smuzhiyun (IMX_AUDMUX_V2_PTCR_RFSEL(8) | 166*4882a593Smuzhiyun IMX_AUDMUX_V2_PTCR_RCSEL(8) | 167*4882a593Smuzhiyun IMX_AUDMUX_V2_PTCR_TFSEL(1) | 168*4882a593Smuzhiyun IMX_AUDMUX_V2_PTCR_TCSEL(1) | 169*4882a593Smuzhiyun IMX_AUDMUX_V2_PTCR_RFSDIR | 170*4882a593Smuzhiyun IMX_AUDMUX_V2_PTCR_RCLKDIR | 171*4882a593Smuzhiyun IMX_AUDMUX_V2_PTCR_TFSDIR | 172*4882a593Smuzhiyun IMX_AUDMUX_V2_PTCR_TCLKDIR) 173*4882a593Smuzhiyun IMX_AUDMUX_V2_PDCR_RXDSEL(1) 174*4882a593Smuzhiyun >; 175*4882a593Smuzhiyun }; 176*4882a593Smuzhiyun}; 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun&ecspi2 { 179*4882a593Smuzhiyun cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; 180*4882a593Smuzhiyun pinctrl-names = "default"; 181*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs &pinctrl_ecspi2_flwp>; 182*4882a593Smuzhiyun status = "okay"; 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun s25fl256s: flash@0 { 185*4882a593Smuzhiyun #address-cells = <1>; 186*4882a593Smuzhiyun #size-cells = <1>; 187*4882a593Smuzhiyun compatible = "jedec,spi-nor"; 188*4882a593Smuzhiyun spi-max-frequency = <40000000>; 189*4882a593Smuzhiyun reg = <0>; 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun partition@0 { 192*4882a593Smuzhiyun label = "SPL (spi)"; 193*4882a593Smuzhiyun reg = <0x0 0x20000>; 194*4882a593Smuzhiyun read-only; 195*4882a593Smuzhiyun }; 196*4882a593Smuzhiyun partition@1 { 197*4882a593Smuzhiyun label = "u-boot (spi)"; 198*4882a593Smuzhiyun reg = <0x20000 0x100000>; 199*4882a593Smuzhiyun read-only; 200*4882a593Smuzhiyun }; 201*4882a593Smuzhiyun partition@2 { 202*4882a593Smuzhiyun label = "uboot-env (spi)"; 203*4882a593Smuzhiyun reg = <0x120000 0x10000>; 204*4882a593Smuzhiyun }; 205*4882a593Smuzhiyun partition@3 { 206*4882a593Smuzhiyun label = "uboot-envr (spi)"; 207*4882a593Smuzhiyun reg = <0x130000 0x10000>; 208*4882a593Smuzhiyun }; 209*4882a593Smuzhiyun partition@4 { 210*4882a593Smuzhiyun label = "linux-recovery (spi)"; 211*4882a593Smuzhiyun reg = <0x140000 0x800000>; 212*4882a593Smuzhiyun }; 213*4882a593Smuzhiyun partition@5 { 214*4882a593Smuzhiyun label = "swupdate-fitImg (spi)"; 215*4882a593Smuzhiyun reg = <0x940000 0x400000>; 216*4882a593Smuzhiyun }; 217*4882a593Smuzhiyun partition@6 { 218*4882a593Smuzhiyun label = "swupdate-initramfs (spi)"; 219*4882a593Smuzhiyun reg = <0xD40000 0x800000>; 220*4882a593Smuzhiyun }; 221*4882a593Smuzhiyun }; 222*4882a593Smuzhiyun}; 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun&ecspi3 { 225*4882a593Smuzhiyun cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; 226*4882a593Smuzhiyun pinctrl-names = "default"; 227*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs &pinctrl_ecspi3_flwp>; 228*4882a593Smuzhiyun status = "okay"; 229*4882a593Smuzhiyun}; 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun&fec { 232*4882a593Smuzhiyun pinctrl-names = "default"; 233*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_enet>; 234*4882a593Smuzhiyun phy-handle = <ðernet_phy0>; 235*4882a593Smuzhiyun phy-mode = "rgmii-id"; 236*4882a593Smuzhiyun status = "okay"; 237*4882a593Smuzhiyun 238*4882a593Smuzhiyun mdio { 239*4882a593Smuzhiyun #address-cells = <1>; 240*4882a593Smuzhiyun #size-cells = <0>; 241*4882a593Smuzhiyun ethernet_phy0: ethernet-phy@0 { 242*4882a593Smuzhiyun compatible = "marvell,88E1510"; 243*4882a593Smuzhiyun device_type = "ethernet-phy"; 244*4882a593Smuzhiyun /* Set LED0 control: */ 245*4882a593Smuzhiyun /* On - Link, Blink - Activity, Off - No Link */ 246*4882a593Smuzhiyun marvell,reg-init = <3 0x10 0 0x1011>; 247*4882a593Smuzhiyun max-speed = <100>; 248*4882a593Smuzhiyun reg = <0>; 249*4882a593Smuzhiyun }; 250*4882a593Smuzhiyun }; 251*4882a593Smuzhiyun}; 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun&i2c1 { 254*4882a593Smuzhiyun clock-frequency = <400000>; 255*4882a593Smuzhiyun pinctrl-names = "default"; 256*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c1>; 257*4882a593Smuzhiyun status = "okay"; 258*4882a593Smuzhiyun 259*4882a593Smuzhiyun codec: tfa9879@6c { 260*4882a593Smuzhiyun #sound-dai-cells = <0>; 261*4882a593Smuzhiyun compatible = "nxp,tfa9879"; 262*4882a593Smuzhiyun reg = <0x6C>; 263*4882a593Smuzhiyun }; 264*4882a593Smuzhiyun}; 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun&i2c2 { 267*4882a593Smuzhiyun clock-frequency = <400000>; 268*4882a593Smuzhiyun pinctrl-names = "default"; 269*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c2>; 270*4882a593Smuzhiyun status = "okay"; 271*4882a593Smuzhiyun}; 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun&i2c3 { 274*4882a593Smuzhiyun clock-frequency = <400000>; 275*4882a593Smuzhiyun pinctrl-names = "default"; 276*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c3>; 277*4882a593Smuzhiyun status = "okay"; 278*4882a593Smuzhiyun 279*4882a593Smuzhiyun at24@50 { 280*4882a593Smuzhiyun compatible = "atmel,24c256"; 281*4882a593Smuzhiyun pagesize = <64>; 282*4882a593Smuzhiyun reg = <0x50>; 283*4882a593Smuzhiyun }; 284*4882a593Smuzhiyun 285*4882a593Smuzhiyun pfuze100: pmic@8 { 286*4882a593Smuzhiyun compatible = "fsl,pfuze100"; 287*4882a593Smuzhiyun reg = <0x08>; 288*4882a593Smuzhiyun 289*4882a593Smuzhiyun regulators { 290*4882a593Smuzhiyun sw1a_reg: sw1ab { 291*4882a593Smuzhiyun regulator-min-microvolt = <300000>; 292*4882a593Smuzhiyun regulator-max-microvolt = <1875000>; 293*4882a593Smuzhiyun regulator-boot-on; 294*4882a593Smuzhiyun regulator-always-on; 295*4882a593Smuzhiyun regulator-ramp-delay = <6250>; 296*4882a593Smuzhiyun }; 297*4882a593Smuzhiyun 298*4882a593Smuzhiyun sw1c_reg: sw1c { 299*4882a593Smuzhiyun regulator-min-microvolt = <300000>; 300*4882a593Smuzhiyun regulator-max-microvolt = <1875000>; 301*4882a593Smuzhiyun regulator-boot-on; 302*4882a593Smuzhiyun regulator-always-on; 303*4882a593Smuzhiyun regulator-ramp-delay = <6250>; 304*4882a593Smuzhiyun }; 305*4882a593Smuzhiyun 306*4882a593Smuzhiyun sw2_reg: sw2 { 307*4882a593Smuzhiyun regulator-min-microvolt = <800000>; 308*4882a593Smuzhiyun regulator-max-microvolt = <3950000>; 309*4882a593Smuzhiyun regulator-boot-on; 310*4882a593Smuzhiyun regulator-always-on; 311*4882a593Smuzhiyun }; 312*4882a593Smuzhiyun 313*4882a593Smuzhiyun sw3a_reg: sw3a { 314*4882a593Smuzhiyun regulator-min-microvolt = <400000>; 315*4882a593Smuzhiyun regulator-max-microvolt = <1975000>; 316*4882a593Smuzhiyun regulator-boot-on; 317*4882a593Smuzhiyun regulator-always-on; 318*4882a593Smuzhiyun }; 319*4882a593Smuzhiyun 320*4882a593Smuzhiyun sw3b_reg: sw3b { 321*4882a593Smuzhiyun regulator-min-microvolt = <400000>; 322*4882a593Smuzhiyun regulator-max-microvolt = <1975000>; 323*4882a593Smuzhiyun regulator-boot-on; 324*4882a593Smuzhiyun regulator-always-on; 325*4882a593Smuzhiyun }; 326*4882a593Smuzhiyun 327*4882a593Smuzhiyun sw4_reg: sw4 { 328*4882a593Smuzhiyun regulator-min-microvolt = <800000>; 329*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 330*4882a593Smuzhiyun }; 331*4882a593Smuzhiyun 332*4882a593Smuzhiyun swbst_reg: swbst { 333*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 334*4882a593Smuzhiyun regulator-max-microvolt = <5150000>; 335*4882a593Smuzhiyun }; 336*4882a593Smuzhiyun 337*4882a593Smuzhiyun snvs_reg: vsnvs { 338*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 339*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 340*4882a593Smuzhiyun regulator-boot-on; 341*4882a593Smuzhiyun regulator-always-on; 342*4882a593Smuzhiyun }; 343*4882a593Smuzhiyun 344*4882a593Smuzhiyun vref_reg: vrefddr { 345*4882a593Smuzhiyun regulator-boot-on; 346*4882a593Smuzhiyun regulator-always-on; 347*4882a593Smuzhiyun }; 348*4882a593Smuzhiyun 349*4882a593Smuzhiyun vgen1_reg: vgen1 { 350*4882a593Smuzhiyun regulator-min-microvolt = <800000>; 351*4882a593Smuzhiyun regulator-max-microvolt = <1550000>; 352*4882a593Smuzhiyun }; 353*4882a593Smuzhiyun 354*4882a593Smuzhiyun vgen2_reg: vgen2 { 355*4882a593Smuzhiyun regulator-min-microvolt = <800000>; 356*4882a593Smuzhiyun regulator-max-microvolt = <1550000>; 357*4882a593Smuzhiyun }; 358*4882a593Smuzhiyun 359*4882a593Smuzhiyun vgen3_reg: vgen3 { 360*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 361*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 362*4882a593Smuzhiyun }; 363*4882a593Smuzhiyun 364*4882a593Smuzhiyun vgen4_reg: vgen4 { 365*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 366*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 367*4882a593Smuzhiyun regulator-always-on; 368*4882a593Smuzhiyun }; 369*4882a593Smuzhiyun 370*4882a593Smuzhiyun vgen5_reg: vgen5 { 371*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 372*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 373*4882a593Smuzhiyun regulator-always-on; 374*4882a593Smuzhiyun }; 375*4882a593Smuzhiyun 376*4882a593Smuzhiyun vgen6_reg: vgen6 { 377*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 378*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 379*4882a593Smuzhiyun regulator-always-on; 380*4882a593Smuzhiyun }; 381*4882a593Smuzhiyun }; 382*4882a593Smuzhiyun }; 383*4882a593Smuzhiyun}; 384*4882a593Smuzhiyun 385*4882a593Smuzhiyun&ldb { 386*4882a593Smuzhiyun status = "okay"; 387*4882a593Smuzhiyun 388*4882a593Smuzhiyun lvds0: lvds-channel@0 { 389*4882a593Smuzhiyun status = "okay"; 390*4882a593Smuzhiyun 391*4882a593Smuzhiyun port@4 { 392*4882a593Smuzhiyun reg = <4>; 393*4882a593Smuzhiyun 394*4882a593Smuzhiyun lvds0_out: endpoint { 395*4882a593Smuzhiyun remote-endpoint = <&panel_in_lvds0>; 396*4882a593Smuzhiyun }; 397*4882a593Smuzhiyun }; 398*4882a593Smuzhiyun }; 399*4882a593Smuzhiyun}; 400*4882a593Smuzhiyun 401*4882a593Smuzhiyun&pwm2 { 402*4882a593Smuzhiyun pinctrl-names = "default"; 403*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pwm2>; 404*4882a593Smuzhiyun status = "okay"; 405*4882a593Smuzhiyun}; 406*4882a593Smuzhiyun 407*4882a593Smuzhiyun&ssi2 { 408*4882a593Smuzhiyun status = "okay"; 409*4882a593Smuzhiyun}; 410*4882a593Smuzhiyun 411*4882a593Smuzhiyun&uart4 { 412*4882a593Smuzhiyun pinctrl-names = "default"; 413*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart4>; 414*4882a593Smuzhiyun uart-has-rtscts; 415*4882a593Smuzhiyun status = "okay"; 416*4882a593Smuzhiyun}; 417*4882a593Smuzhiyun 418*4882a593Smuzhiyun&uart5 { 419*4882a593Smuzhiyun pinctrl-names = "default"; 420*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart5>; 421*4882a593Smuzhiyun status = "okay"; 422*4882a593Smuzhiyun}; 423*4882a593Smuzhiyun 424*4882a593Smuzhiyun&usbh1 { 425*4882a593Smuzhiyun vbus-supply = <®_usbh1_vbus>; 426*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usbh1>; 427*4882a593Smuzhiyun status = "okay"; 428*4882a593Smuzhiyun}; 429*4882a593Smuzhiyun 430*4882a593Smuzhiyun&usdhc4 { 431*4882a593Smuzhiyun pinctrl-names = "default"; 432*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc4>; 433*4882a593Smuzhiyun bus-width = <8>; 434*4882a593Smuzhiyun non-removable; 435*4882a593Smuzhiyun status = "okay"; 436*4882a593Smuzhiyun}; 437*4882a593Smuzhiyun 438*4882a593Smuzhiyun&iomuxc { 439*4882a593Smuzhiyun pinctrl_audmux: audmuxgrp { 440*4882a593Smuzhiyun fsl,pins = < 441*4882a593Smuzhiyun /* I2S OUTPUT AUD6*/ 442*4882a593Smuzhiyun MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x130b0 443*4882a593Smuzhiyun MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x130b0 444*4882a593Smuzhiyun MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x130b0 445*4882a593Smuzhiyun MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x130b0 446*4882a593Smuzhiyun >; 447*4882a593Smuzhiyun }; 448*4882a593Smuzhiyun 449*4882a593Smuzhiyun pinctrl_backlight: dispgrp { 450*4882a593Smuzhiyun fsl,pins = < 451*4882a593Smuzhiyun /* BLEN_OUT */ 452*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b0 453*4882a593Smuzhiyun >; 454*4882a593Smuzhiyun }; 455*4882a593Smuzhiyun 456*4882a593Smuzhiyun pinctrl_ecspi2: ecspi2grp { 457*4882a593Smuzhiyun fsl,pins = < 458*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 459*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 460*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 461*4882a593Smuzhiyun >; 462*4882a593Smuzhiyun }; 463*4882a593Smuzhiyun 464*4882a593Smuzhiyun pinctrl_ecspi2_cs: ecspi2csgrp { 465*4882a593Smuzhiyun fsl,pins = < 466*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x100b1 467*4882a593Smuzhiyun >; 468*4882a593Smuzhiyun }; 469*4882a593Smuzhiyun 470*4882a593Smuzhiyun pinctrl_ecspi2_flwp: ecspi2flwpgrp { 471*4882a593Smuzhiyun fsl,pins = < 472*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 473*4882a593Smuzhiyun >; 474*4882a593Smuzhiyun }; 475*4882a593Smuzhiyun 476*4882a593Smuzhiyun pinctrl_ecspi3: ecspi3grp { 477*4882a593Smuzhiyun fsl,pins = < 478*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 479*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 480*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 481*4882a593Smuzhiyun >; 482*4882a593Smuzhiyun }; 483*4882a593Smuzhiyun 484*4882a593Smuzhiyun pinctrl_ecspi3_cs: ecspi3csgrp { 485*4882a593Smuzhiyun fsl,pins = < 486*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x1b0b0 487*4882a593Smuzhiyun >; 488*4882a593Smuzhiyun }; 489*4882a593Smuzhiyun 490*4882a593Smuzhiyun pinctrl_ecspi3_flwp: ecspi3flwpgrp { 491*4882a593Smuzhiyun fsl,pins = < 492*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b0 493*4882a593Smuzhiyun >; 494*4882a593Smuzhiyun }; 495*4882a593Smuzhiyun 496*4882a593Smuzhiyun pinctrl_enet: enetgrp { 497*4882a593Smuzhiyun fsl,pins = < 498*4882a593Smuzhiyun MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 499*4882a593Smuzhiyun MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 500*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 501*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 502*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 503*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 504*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 505*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 506*4882a593Smuzhiyun MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 507*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 508*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 509*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 510*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 511*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 512*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 513*4882a593Smuzhiyun MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 514*4882a593Smuzhiyun MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 515*4882a593Smuzhiyun MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 516*4882a593Smuzhiyun >; 517*4882a593Smuzhiyun }; 518*4882a593Smuzhiyun 519*4882a593Smuzhiyun pinctrl_i2c1: i2c1grp { 520*4882a593Smuzhiyun fsl,pins = < 521*4882a593Smuzhiyun MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 522*4882a593Smuzhiyun MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 523*4882a593Smuzhiyun >; 524*4882a593Smuzhiyun }; 525*4882a593Smuzhiyun 526*4882a593Smuzhiyun pinctrl_i2c2: i2c2grp { 527*4882a593Smuzhiyun fsl,pins = < 528*4882a593Smuzhiyun MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 529*4882a593Smuzhiyun MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 530*4882a593Smuzhiyun >; 531*4882a593Smuzhiyun }; 532*4882a593Smuzhiyun 533*4882a593Smuzhiyun pinctrl_i2c3: i2c3grp { 534*4882a593Smuzhiyun fsl,pins = < 535*4882a593Smuzhiyun MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 536*4882a593Smuzhiyun MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 537*4882a593Smuzhiyun >; 538*4882a593Smuzhiyun }; 539*4882a593Smuzhiyun 540*4882a593Smuzhiyun pinctrl_pwm2: pwm2grp { 541*4882a593Smuzhiyun fsl,pins = < 542*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1 543*4882a593Smuzhiyun >; 544*4882a593Smuzhiyun }; 545*4882a593Smuzhiyun 546*4882a593Smuzhiyun pinctrl_reg_lvds: reqlvdsgrp { 547*4882a593Smuzhiyun fsl,pins = < 548*4882a593Smuzhiyun /* LVDS_PPEN_OUT */ 549*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 550*4882a593Smuzhiyun >; 551*4882a593Smuzhiyun }; 552*4882a593Smuzhiyun 553*4882a593Smuzhiyun pinctrl_uart4: uart4grp { 554*4882a593Smuzhiyun fsl,pins = < 555*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 556*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 557*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 558*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 559*4882a593Smuzhiyun >; 560*4882a593Smuzhiyun }; 561*4882a593Smuzhiyun 562*4882a593Smuzhiyun pinctrl_uart5: uart5grp { 563*4882a593Smuzhiyun fsl,pins = < 564*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 565*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 566*4882a593Smuzhiyun >; 567*4882a593Smuzhiyun }; 568*4882a593Smuzhiyun 569*4882a593Smuzhiyun pinctrl_usbh1: usbh1grp { 570*4882a593Smuzhiyun fsl,pins = < 571*4882a593Smuzhiyun MX6QDL_PAD_EIM_D30__USB_H1_OC 0x030b0 572*4882a593Smuzhiyun >; 573*4882a593Smuzhiyun }; 574*4882a593Smuzhiyun 575*4882a593Smuzhiyun pinctrl_usbh1_vbus: usbh1_vbus_grp { 576*4882a593Smuzhiyun fsl,pins = < 577*4882a593Smuzhiyun MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 578*4882a593Smuzhiyun >; 579*4882a593Smuzhiyun }; 580*4882a593Smuzhiyun 581*4882a593Smuzhiyun pinctrl_usdhc4: usdhc4grp { 582*4882a593Smuzhiyun fsl,pins = < 583*4882a593Smuzhiyun MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 584*4882a593Smuzhiyun MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 585*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 586*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 587*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 588*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 589*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 590*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 591*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 592*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 593*4882a593Smuzhiyun MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x17059 594*4882a593Smuzhiyun >; 595*4882a593Smuzhiyun }; 596*4882a593Smuzhiyun}; 597