1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Support for imx6 based Advantech DMS-BA16 Qseven module 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright 2015 Timesys Corporation. 5*4882a593Smuzhiyun * Copyright 2015 General Electric Company 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * This file is dual-licensed: you can use it either under the terms 8*4882a593Smuzhiyun * of the GPL or the X11 license, at your option. Note that this dual 9*4882a593Smuzhiyun * licensing only applies to this file, and not this project as a 10*4882a593Smuzhiyun * whole. 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * a) This file is free software; you can redistribute it and/or 13*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License 14*4882a593Smuzhiyun * version 2 as published by the Free Software Foundation. 15*4882a593Smuzhiyun * 16*4882a593Smuzhiyun * This file is distributed in the hope that it will be useful, 17*4882a593Smuzhiyun * but WITHOUT ANY WARRANTY; without even the implied warranty of 18*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19*4882a593Smuzhiyun * GNU General Public License for more details. 20*4882a593Smuzhiyun * 21*4882a593Smuzhiyun * Or, alternatively, 22*4882a593Smuzhiyun * 23*4882a593Smuzhiyun * b) Permission is hereby granted, free of charge, to any person 24*4882a593Smuzhiyun * obtaining a copy of this software and associated documentation 25*4882a593Smuzhiyun * files (the "Software"), to deal in the Software without 26*4882a593Smuzhiyun * restriction, including without limitation the rights to use, 27*4882a593Smuzhiyun * copy, modify, merge, publish, distribute, sublicense, and/or 28*4882a593Smuzhiyun * sell copies of the Software, and to permit persons to whom the 29*4882a593Smuzhiyun * Software is furnished to do so, subject to the following 30*4882a593Smuzhiyun * conditions: 31*4882a593Smuzhiyun * 32*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be 33*4882a593Smuzhiyun * included in all copies or substantial portions of the Software. 34*4882a593Smuzhiyun * 35*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37*4882a593Smuzhiyun * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39*4882a593Smuzhiyun * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40*4882a593Smuzhiyun * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41*4882a593Smuzhiyun * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 43*4882a593Smuzhiyun */ 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun#include "imx6q.dtsi" 46*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun/ { 49*4882a593Smuzhiyun memory@10000000 { 50*4882a593Smuzhiyun device_type = "memory"; 51*4882a593Smuzhiyun reg = <0x10000000 0x40000000>; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun backlight_lvds: backlight { 55*4882a593Smuzhiyun compatible = "pwm-backlight"; 56*4882a593Smuzhiyun pinctrl-names = "default"; 57*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_display>; 58*4882a593Smuzhiyun pwms = <&pwm1 0 5000000>; 59*4882a593Smuzhiyun brightness-levels = < 0 1 2 3 4 5 6 7 8 9 60*4882a593Smuzhiyun 10 11 12 13 14 15 16 17 18 19 61*4882a593Smuzhiyun 20 21 22 23 24 25 26 27 28 29 62*4882a593Smuzhiyun 30 31 32 33 34 35 36 37 38 39 63*4882a593Smuzhiyun 40 41 42 43 44 45 46 47 48 49 64*4882a593Smuzhiyun 50 51 52 53 54 55 56 57 58 59 65*4882a593Smuzhiyun 60 61 62 63 64 65 66 67 68 69 66*4882a593Smuzhiyun 70 71 72 73 74 75 76 77 78 79 67*4882a593Smuzhiyun 80 81 82 83 84 85 86 87 88 89 68*4882a593Smuzhiyun 90 91 92 93 94 95 96 97 98 99 69*4882a593Smuzhiyun 100 101 102 103 104 105 106 107 108 109 70*4882a593Smuzhiyun 110 111 112 113 114 115 116 117 118 119 71*4882a593Smuzhiyun 120 121 122 123 124 125 126 127 128 129 72*4882a593Smuzhiyun 130 131 132 133 134 135 136 137 138 139 73*4882a593Smuzhiyun 140 141 142 143 144 145 146 147 148 149 74*4882a593Smuzhiyun 150 151 152 153 154 155 156 157 158 159 75*4882a593Smuzhiyun 160 161 162 163 164 165 166 167 168 169 76*4882a593Smuzhiyun 170 171 172 173 174 175 176 177 178 179 77*4882a593Smuzhiyun 180 181 182 183 184 185 186 187 188 189 78*4882a593Smuzhiyun 190 191 192 193 194 195 196 197 198 199 79*4882a593Smuzhiyun 200 201 202 203 204 205 206 207 208 209 80*4882a593Smuzhiyun 210 211 212 213 214 215 216 217 218 219 81*4882a593Smuzhiyun 220 221 222 223 224 225 226 227 228 229 82*4882a593Smuzhiyun 230 231 232 233 234 235 236 237 238 239 83*4882a593Smuzhiyun 240 241 242 243 244 245 246 247 248 249 84*4882a593Smuzhiyun 250 251 252 253 254 255>; 85*4882a593Smuzhiyun default-brightness-level = <255>; 86*4882a593Smuzhiyun enable-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun reg_1p8v: regulator-1p8v { 90*4882a593Smuzhiyun compatible = "regulator-fixed"; 91*4882a593Smuzhiyun regulator-name = "1P8V"; 92*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 93*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 94*4882a593Smuzhiyun regulator-always-on; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun reg_3p3v: regulator-3p3v { 98*4882a593Smuzhiyun compatible = "regulator-fixed"; 99*4882a593Smuzhiyun regulator-name = "3P3V"; 100*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 101*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 102*4882a593Smuzhiyun regulator-always-on; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun reg_lvds: regulator-lvds { 106*4882a593Smuzhiyun compatible = "regulator-fixed"; 107*4882a593Smuzhiyun regulator-name = "lvds_ppen"; 108*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 109*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 110*4882a593Smuzhiyun regulator-boot-on; 111*4882a593Smuzhiyun gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 112*4882a593Smuzhiyun enable-active-high; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun reg_usb_h1_vbus: regulator-usbh1vbus { 116*4882a593Smuzhiyun compatible = "regulator-fixed"; 117*4882a593Smuzhiyun regulator-name = "usb_h1_vbus"; 118*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 119*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 120*4882a593Smuzhiyun }; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun reg_usb_otg_vbus: regulator-usbotgvbus { 123*4882a593Smuzhiyun compatible = "regulator-fixed"; 124*4882a593Smuzhiyun regulator-name = "usb_otg_vbus"; 125*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 126*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 127*4882a593Smuzhiyun }; 128*4882a593Smuzhiyun}; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun&audmux { 131*4882a593Smuzhiyun pinctrl-names = "default"; 132*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_audmux>; 133*4882a593Smuzhiyun status = "okay"; 134*4882a593Smuzhiyun}; 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun&ecspi1 { 137*4882a593Smuzhiyun cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; 138*4882a593Smuzhiyun pinctrl-names = "default"; 139*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_ecspi1>; 140*4882a593Smuzhiyun status = "okay"; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun flash: flash@0 { 143*4882a593Smuzhiyun compatible = "jedec,spi-nor"; 144*4882a593Smuzhiyun #address-cells = <1>; 145*4882a593Smuzhiyun #size-cells = <1>; 146*4882a593Smuzhiyun spi-max-frequency = <20000000>; 147*4882a593Smuzhiyun reg = <0>; 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun partition@0 { 150*4882a593Smuzhiyun label = "U-Boot"; 151*4882a593Smuzhiyun reg = <0x0 0xc0000>; 152*4882a593Smuzhiyun }; 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun partition@c0000 { 155*4882a593Smuzhiyun label = "env"; 156*4882a593Smuzhiyun reg = <0xc0000 0x10000>; 157*4882a593Smuzhiyun }; 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun partition@d0000 { 160*4882a593Smuzhiyun label = "spare"; 161*4882a593Smuzhiyun reg = <0xd0000 0x320000>; 162*4882a593Smuzhiyun }; 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun partition@3f0000 { 165*4882a593Smuzhiyun label = "mfg"; 166*4882a593Smuzhiyun reg = <0x3f0000 0x10000>; 167*4882a593Smuzhiyun }; 168*4882a593Smuzhiyun }; 169*4882a593Smuzhiyun}; 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun&fec { 172*4882a593Smuzhiyun pinctrl-names = "default"; 173*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_enet>; 174*4882a593Smuzhiyun phy-mode = "rgmii-id"; 175*4882a593Smuzhiyun status = "okay"; 176*4882a593Smuzhiyun}; 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun&hdmi { 179*4882a593Smuzhiyun ddc-i2c-bus = <&i2c2>; 180*4882a593Smuzhiyun status = "okay"; 181*4882a593Smuzhiyun}; 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun&i2c1 { 184*4882a593Smuzhiyun clock-frequency = <100000>; 185*4882a593Smuzhiyun pinctrl-names = "default"; 186*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c1>; 187*4882a593Smuzhiyun status = "okay"; 188*4882a593Smuzhiyun}; 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun&i2c2 { 191*4882a593Smuzhiyun clock-frequency = <100000>; 192*4882a593Smuzhiyun pinctrl-names = "default"; 193*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c2>; 194*4882a593Smuzhiyun status = "okay"; 195*4882a593Smuzhiyun}; 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun&i2c3 { 198*4882a593Smuzhiyun clock-frequency = <100000>; 199*4882a593Smuzhiyun pinctrl-names = "default"; 200*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c3>; 201*4882a593Smuzhiyun status = "okay"; 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun pmic@58 { 204*4882a593Smuzhiyun compatible = "dlg,da9063"; 205*4882a593Smuzhiyun reg = <0x58>; 206*4882a593Smuzhiyun pinctrl-names = "default"; 207*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pmic>; 208*4882a593Smuzhiyun interrupt-parent = <&gpio7>; 209*4882a593Smuzhiyun interrupts = <13 IRQ_TYPE_LEVEL_LOW>; 210*4882a593Smuzhiyun 211*4882a593Smuzhiyun onkey { 212*4882a593Smuzhiyun compatible = "dlg,da9063-onkey"; 213*4882a593Smuzhiyun }; 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun regulators { 216*4882a593Smuzhiyun vdd_bcore1: bcore1 { 217*4882a593Smuzhiyun regulator-min-microvolt = <1420000>; 218*4882a593Smuzhiyun regulator-max-microvolt = <1420000>; 219*4882a593Smuzhiyun regulator-always-on; 220*4882a593Smuzhiyun regulator-boot-on; 221*4882a593Smuzhiyun }; 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun vdd_bcore2: bcore2 { 224*4882a593Smuzhiyun regulator-min-microvolt = <1420000>; 225*4882a593Smuzhiyun regulator-max-microvolt = <1420000>; 226*4882a593Smuzhiyun regulator-always-on; 227*4882a593Smuzhiyun regulator-boot-on; 228*4882a593Smuzhiyun }; 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun vdd_bpro: bpro { 231*4882a593Smuzhiyun regulator-min-microvolt = <1500000>; 232*4882a593Smuzhiyun regulator-max-microvolt = <1500000>; 233*4882a593Smuzhiyun regulator-always-on; 234*4882a593Smuzhiyun regulator-boot-on; 235*4882a593Smuzhiyun }; 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun vdd_bmem: bmem { 238*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 239*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 240*4882a593Smuzhiyun regulator-always-on; 241*4882a593Smuzhiyun regulator-boot-on; 242*4882a593Smuzhiyun }; 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun vdd_bio: bio { 245*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 246*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 247*4882a593Smuzhiyun regulator-always-on; 248*4882a593Smuzhiyun regulator-boot-on; 249*4882a593Smuzhiyun }; 250*4882a593Smuzhiyun 251*4882a593Smuzhiyun vdd_bperi: bperi { 252*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 253*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 254*4882a593Smuzhiyun regulator-always-on; 255*4882a593Smuzhiyun regulator-boot-on; 256*4882a593Smuzhiyun }; 257*4882a593Smuzhiyun 258*4882a593Smuzhiyun vdd_ldo1: ldo1 { 259*4882a593Smuzhiyun regulator-min-microvolt = <600000>; 260*4882a593Smuzhiyun regulator-max-microvolt = <1860000>; 261*4882a593Smuzhiyun }; 262*4882a593Smuzhiyun 263*4882a593Smuzhiyun vdd_ldo2: ldo2 { 264*4882a593Smuzhiyun regulator-min-microvolt = <600000>; 265*4882a593Smuzhiyun regulator-max-microvolt = <1860000>; 266*4882a593Smuzhiyun }; 267*4882a593Smuzhiyun 268*4882a593Smuzhiyun vdd_ldo3: ldo3 { 269*4882a593Smuzhiyun regulator-min-microvolt = <900000>; 270*4882a593Smuzhiyun regulator-max-microvolt = <3440000>; 271*4882a593Smuzhiyun }; 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun vdd_ldo4: ldo4 { 274*4882a593Smuzhiyun regulator-min-microvolt = <900000>; 275*4882a593Smuzhiyun regulator-max-microvolt = <3440000>; 276*4882a593Smuzhiyun }; 277*4882a593Smuzhiyun 278*4882a593Smuzhiyun vdd_ldo5: ldo5 { 279*4882a593Smuzhiyun regulator-min-microvolt = <900000>; 280*4882a593Smuzhiyun regulator-max-microvolt = <3600000>; 281*4882a593Smuzhiyun }; 282*4882a593Smuzhiyun 283*4882a593Smuzhiyun vdd_ldo6: ldo6 { 284*4882a593Smuzhiyun regulator-min-microvolt = <900000>; 285*4882a593Smuzhiyun regulator-max-microvolt = <3600000>; 286*4882a593Smuzhiyun }; 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun vdd_ldo7: ldo7 { 289*4882a593Smuzhiyun regulator-min-microvolt = <900000>; 290*4882a593Smuzhiyun regulator-max-microvolt = <3600000>; 291*4882a593Smuzhiyun }; 292*4882a593Smuzhiyun 293*4882a593Smuzhiyun vdd_ldo8: ldo8 { 294*4882a593Smuzhiyun regulator-min-microvolt = <900000>; 295*4882a593Smuzhiyun regulator-max-microvolt = <3600000>; 296*4882a593Smuzhiyun }; 297*4882a593Smuzhiyun 298*4882a593Smuzhiyun vdd_ldo9: ldo9 { 299*4882a593Smuzhiyun regulator-min-microvolt = <950000>; 300*4882a593Smuzhiyun regulator-max-microvolt = <3600000>; 301*4882a593Smuzhiyun }; 302*4882a593Smuzhiyun 303*4882a593Smuzhiyun vdd_ldo10: ldo10 { 304*4882a593Smuzhiyun regulator-min-microvolt = <900000>; 305*4882a593Smuzhiyun regulator-max-microvolt = <3600000>; 306*4882a593Smuzhiyun }; 307*4882a593Smuzhiyun 308*4882a593Smuzhiyun vdd_ldo11: ldo11 { 309*4882a593Smuzhiyun regulator-min-microvolt = <900000>; 310*4882a593Smuzhiyun regulator-max-microvolt = <3600000>; 311*4882a593Smuzhiyun regulator-always-on; 312*4882a593Smuzhiyun regulator-boot-on; 313*4882a593Smuzhiyun }; 314*4882a593Smuzhiyun }; 315*4882a593Smuzhiyun }; 316*4882a593Smuzhiyun 317*4882a593Smuzhiyun rtc@32 { 318*4882a593Smuzhiyun compatible = "epson,rx8010"; 319*4882a593Smuzhiyun pinctrl-names = "default"; 320*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_rtc>; 321*4882a593Smuzhiyun reg = <0x32>; 322*4882a593Smuzhiyun interrupt-parent = <&gpio4>; 323*4882a593Smuzhiyun interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; 324*4882a593Smuzhiyun }; 325*4882a593Smuzhiyun}; 326*4882a593Smuzhiyun 327*4882a593Smuzhiyun&pcie { 328*4882a593Smuzhiyun pinctrl-names = "default"; 329*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pcie>; 330*4882a593Smuzhiyun reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; 331*4882a593Smuzhiyun fsl,tx-swing-full = <103>; 332*4882a593Smuzhiyun fsl,tx-swing-low = <103>; 333*4882a593Smuzhiyun status = "okay"; 334*4882a593Smuzhiyun}; 335*4882a593Smuzhiyun 336*4882a593Smuzhiyun&pwm1 { 337*4882a593Smuzhiyun #pwm-cells = <2>; 338*4882a593Smuzhiyun pinctrl-names = "default"; 339*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pwm1>; 340*4882a593Smuzhiyun status = "okay"; 341*4882a593Smuzhiyun}; 342*4882a593Smuzhiyun 343*4882a593Smuzhiyun&pwm2 { 344*4882a593Smuzhiyun pinctrl-names = "default"; 345*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pwm2>; 346*4882a593Smuzhiyun status = "disabled"; 347*4882a593Smuzhiyun}; 348*4882a593Smuzhiyun 349*4882a593Smuzhiyun&sata { 350*4882a593Smuzhiyun status = "okay"; 351*4882a593Smuzhiyun}; 352*4882a593Smuzhiyun 353*4882a593Smuzhiyun&ssi1 { 354*4882a593Smuzhiyun status = "okay"; 355*4882a593Smuzhiyun}; 356*4882a593Smuzhiyun 357*4882a593Smuzhiyun&uart3 { 358*4882a593Smuzhiyun pinctrl-names = "default"; 359*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart3>; 360*4882a593Smuzhiyun uart-has-rtscts; 361*4882a593Smuzhiyun status = "okay"; 362*4882a593Smuzhiyun}; 363*4882a593Smuzhiyun 364*4882a593Smuzhiyun&uart4 { 365*4882a593Smuzhiyun pinctrl-names = "default"; 366*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart4>; 367*4882a593Smuzhiyun status = "okay"; 368*4882a593Smuzhiyun}; 369*4882a593Smuzhiyun 370*4882a593Smuzhiyun&usbh1 { 371*4882a593Smuzhiyun pinctrl-names = "default"; 372*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usbhub>; 373*4882a593Smuzhiyun vbus-supply = <®_usb_h1_vbus>; 374*4882a593Smuzhiyun reset-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>; 375*4882a593Smuzhiyun status = "okay"; 376*4882a593Smuzhiyun}; 377*4882a593Smuzhiyun 378*4882a593Smuzhiyun&usbotg { 379*4882a593Smuzhiyun vbus-supply = <®_usb_otg_vbus>; 380*4882a593Smuzhiyun pinctrl-names = "default"; 381*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usbotg>; 382*4882a593Smuzhiyun disable-over-current; 383*4882a593Smuzhiyun status = "okay"; 384*4882a593Smuzhiyun}; 385*4882a593Smuzhiyun 386*4882a593Smuzhiyun&usdhc2 { 387*4882a593Smuzhiyun pinctrl-names = "default"; 388*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc2>; 389*4882a593Smuzhiyun cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; 390*4882a593Smuzhiyun no-1-8-v; 391*4882a593Smuzhiyun keep-power-in-suspend; 392*4882a593Smuzhiyun wakeup-source; 393*4882a593Smuzhiyun status = "okay"; 394*4882a593Smuzhiyun}; 395*4882a593Smuzhiyun 396*4882a593Smuzhiyun&usdhc3 { 397*4882a593Smuzhiyun pinctrl-names = "default"; 398*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc3 &pinctrl_usdhc3_reset>; 399*4882a593Smuzhiyun bus-width = <8>; 400*4882a593Smuzhiyun vmmc-supply = <&vdd_bperi>; 401*4882a593Smuzhiyun non-removable; 402*4882a593Smuzhiyun keep-power-in-suspend; 403*4882a593Smuzhiyun status = "okay"; 404*4882a593Smuzhiyun}; 405*4882a593Smuzhiyun 406*4882a593Smuzhiyun&wdog1 { 407*4882a593Smuzhiyun pinctrl-names = "default"; 408*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_wdog>; 409*4882a593Smuzhiyun fsl,ext-reset-output; 410*4882a593Smuzhiyun}; 411*4882a593Smuzhiyun 412*4882a593Smuzhiyun&iomuxc { 413*4882a593Smuzhiyun pinctrl-names = "default"; 414*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_hog>; 415*4882a593Smuzhiyun 416*4882a593Smuzhiyun pinctrl_audmux: audmuxgrp { 417*4882a593Smuzhiyun fsl,pins = < 418*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 419*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0 420*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 421*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 422*4882a593Smuzhiyun >; 423*4882a593Smuzhiyun }; 424*4882a593Smuzhiyun 425*4882a593Smuzhiyun pinctrl_display: dispgrp { 426*4882a593Smuzhiyun fsl,pins = < 427*4882a593Smuzhiyun /* BLEN_OUT */ 428*4882a593Smuzhiyun MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 429*4882a593Smuzhiyun /* LVDS_PPEN_OUT */ 430*4882a593Smuzhiyun MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 431*4882a593Smuzhiyun >; 432*4882a593Smuzhiyun }; 433*4882a593Smuzhiyun 434*4882a593Smuzhiyun pinctrl_ecspi1: ecspi1grp { 435*4882a593Smuzhiyun fsl,pins = < 436*4882a593Smuzhiyun MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 437*4882a593Smuzhiyun MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 438*4882a593Smuzhiyun MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 439*4882a593Smuzhiyun /* SPI1 CS */ 440*4882a593Smuzhiyun MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 441*4882a593Smuzhiyun >; 442*4882a593Smuzhiyun }; 443*4882a593Smuzhiyun 444*4882a593Smuzhiyun pinctrl_ecspi5: ecspi5grp { 445*4882a593Smuzhiyun fsl,pins = < 446*4882a593Smuzhiyun MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x1b0b0 447*4882a593Smuzhiyun MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x1b0b0 448*4882a593Smuzhiyun MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x1b0b0 449*4882a593Smuzhiyun MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0 450*4882a593Smuzhiyun >; 451*4882a593Smuzhiyun }; 452*4882a593Smuzhiyun 453*4882a593Smuzhiyun pinctrl_enet: enetgrp { 454*4882a593Smuzhiyun fsl,pins = < 455*4882a593Smuzhiyun MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 456*4882a593Smuzhiyun MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 457*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 458*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 459*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 460*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 461*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 462*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 463*4882a593Smuzhiyun MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 464*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 465*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 466*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 467*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 468*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 469*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 470*4882a593Smuzhiyun /* FEC Reset */ 471*4882a593Smuzhiyun MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 472*4882a593Smuzhiyun /* AR8033 Interrupt */ 473*4882a593Smuzhiyun MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 474*4882a593Smuzhiyun >; 475*4882a593Smuzhiyun }; 476*4882a593Smuzhiyun 477*4882a593Smuzhiyun pinctrl_hog: hoggrp { 478*4882a593Smuzhiyun fsl,pins = < 479*4882a593Smuzhiyun /* GPIO 0-7 */ 480*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 481*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 482*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 483*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 484*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 485*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b0 486*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 487*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x1b0b0 488*4882a593Smuzhiyun /* SUS_S3_OUT to CPLD */ 489*4882a593Smuzhiyun MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 490*4882a593Smuzhiyun >; 491*4882a593Smuzhiyun }; 492*4882a593Smuzhiyun 493*4882a593Smuzhiyun pinctrl_i2c1: i2c1grp { 494*4882a593Smuzhiyun fsl,pins = < 495*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 496*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 497*4882a593Smuzhiyun >; 498*4882a593Smuzhiyun }; 499*4882a593Smuzhiyun 500*4882a593Smuzhiyun pinctrl_i2c2: i2c2grp { 501*4882a593Smuzhiyun fsl,pins = < 502*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 503*4882a593Smuzhiyun MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 504*4882a593Smuzhiyun >; 505*4882a593Smuzhiyun }; 506*4882a593Smuzhiyun 507*4882a593Smuzhiyun pinctrl_i2c3: i2c3grp { 508*4882a593Smuzhiyun fsl,pins = < 509*4882a593Smuzhiyun MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 510*4882a593Smuzhiyun MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 511*4882a593Smuzhiyun >; 512*4882a593Smuzhiyun }; 513*4882a593Smuzhiyun 514*4882a593Smuzhiyun pinctrl_pcie: pciegrp { 515*4882a593Smuzhiyun fsl,pins = < 516*4882a593Smuzhiyun /* PCIe Reset */ 517*4882a593Smuzhiyun MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 518*4882a593Smuzhiyun /* PCIe Wake */ 519*4882a593Smuzhiyun MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 520*4882a593Smuzhiyun >; 521*4882a593Smuzhiyun }; 522*4882a593Smuzhiyun 523*4882a593Smuzhiyun pinctrl_pmic: pmicgrp { 524*4882a593Smuzhiyun fsl,pins = < 525*4882a593Smuzhiyun /* PMIC Interrupt */ 526*4882a593Smuzhiyun MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 527*4882a593Smuzhiyun >; 528*4882a593Smuzhiyun }; 529*4882a593Smuzhiyun 530*4882a593Smuzhiyun pinctrl_pwm1: pwm1grp { 531*4882a593Smuzhiyun fsl,pins = < 532*4882a593Smuzhiyun MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 533*4882a593Smuzhiyun >; 534*4882a593Smuzhiyun }; 535*4882a593Smuzhiyun 536*4882a593Smuzhiyun pinctrl_pwm2: pwm2grp { 537*4882a593Smuzhiyun fsl,pins = < 538*4882a593Smuzhiyun MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 539*4882a593Smuzhiyun >; 540*4882a593Smuzhiyun }; 541*4882a593Smuzhiyun 542*4882a593Smuzhiyun pinctrl_rtc: rtcgrp { 543*4882a593Smuzhiyun fsl,pins = < 544*4882a593Smuzhiyun /* RTC_INT */ 545*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 546*4882a593Smuzhiyun >; 547*4882a593Smuzhiyun }; 548*4882a593Smuzhiyun 549*4882a593Smuzhiyun pinctrl_uart3: uart3grp { 550*4882a593Smuzhiyun fsl,pins = < 551*4882a593Smuzhiyun MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 552*4882a593Smuzhiyun MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 553*4882a593Smuzhiyun MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 554*4882a593Smuzhiyun MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 555*4882a593Smuzhiyun >; 556*4882a593Smuzhiyun }; 557*4882a593Smuzhiyun 558*4882a593Smuzhiyun pinctrl_uart4: uart4grp { 559*4882a593Smuzhiyun fsl,pins = < 560*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 561*4882a593Smuzhiyun MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 562*4882a593Smuzhiyun >; 563*4882a593Smuzhiyun }; 564*4882a593Smuzhiyun 565*4882a593Smuzhiyun pinctrl_usbhub: usbhubgrp { 566*4882a593Smuzhiyun fsl,pins = < 567*4882a593Smuzhiyun /* HUB_RESET */ 568*4882a593Smuzhiyun MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b0 569*4882a593Smuzhiyun >; 570*4882a593Smuzhiyun }; 571*4882a593Smuzhiyun 572*4882a593Smuzhiyun pinctrl_usbotg: usbotggrp { 573*4882a593Smuzhiyun fsl,pins = < 574*4882a593Smuzhiyun MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 575*4882a593Smuzhiyun >; 576*4882a593Smuzhiyun }; 577*4882a593Smuzhiyun 578*4882a593Smuzhiyun pinctrl_usdhc2: usdhc2grp { 579*4882a593Smuzhiyun fsl,pins = < 580*4882a593Smuzhiyun MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 581*4882a593Smuzhiyun MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 582*4882a593Smuzhiyun MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 583*4882a593Smuzhiyun MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 584*4882a593Smuzhiyun MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 585*4882a593Smuzhiyun MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 586*4882a593Smuzhiyun /* uSDHC2 CD */ 587*4882a593Smuzhiyun MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 588*4882a593Smuzhiyun >; 589*4882a593Smuzhiyun }; 590*4882a593Smuzhiyun 591*4882a593Smuzhiyun pinctrl_usdhc3: usdhc3grp { 592*4882a593Smuzhiyun fsl,pins = < 593*4882a593Smuzhiyun MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 594*4882a593Smuzhiyun MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 595*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 596*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 597*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 598*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 599*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 600*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 601*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 602*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 603*4882a593Smuzhiyun >; 604*4882a593Smuzhiyun }; 605*4882a593Smuzhiyun 606*4882a593Smuzhiyun pinctrl_usdhc3_reset: usdhc3grp-reset { 607*4882a593Smuzhiyun fsl,pins = < 608*4882a593Smuzhiyun MX6QDL_PAD_SD3_RST__SD3_RESET 0x170F9 609*4882a593Smuzhiyun >; 610*4882a593Smuzhiyun }; 611*4882a593Smuzhiyun 612*4882a593Smuzhiyun pinctrl_usdhc4: usdhc4grp { 613*4882a593Smuzhiyun fsl,pins = < 614*4882a593Smuzhiyun MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 615*4882a593Smuzhiyun MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059 616*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 617*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 618*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 619*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 620*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 621*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 622*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 623*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 624*4882a593Smuzhiyun /* uSDHC4 CD */ 625*4882a593Smuzhiyun MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0 626*4882a593Smuzhiyun /* uSDHC4 SDIO PWR */ 627*4882a593Smuzhiyun MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 628*4882a593Smuzhiyun /* uSDHC4 SDIO WP */ 629*4882a593Smuzhiyun MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 630*4882a593Smuzhiyun /* uSDHC4 SDIO LED */ 631*4882a593Smuzhiyun MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 632*4882a593Smuzhiyun >; 633*4882a593Smuzhiyun }; 634*4882a593Smuzhiyun 635*4882a593Smuzhiyun pinctrl_wdog: wdoggrp { 636*4882a593Smuzhiyun fsl,pins = < 637*4882a593Smuzhiyun MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0 638*4882a593Smuzhiyun >; 639*4882a593Smuzhiyun }; 640*4882a593Smuzhiyun}; 641