1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright 2011 Freescale Semiconductor, Inc. 4*4882a593Smuzhiyun * Copyright 2011 Linaro Ltd. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/dts-v1/; 8*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 9*4882a593Smuzhiyun#include "imx6q.dtsi" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun model = "Freescale i.MX6 Quad Armadillo2 Board"; 13*4882a593Smuzhiyun compatible = "fsl,imx6q-arm2", "fsl,imx6q"; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun memory@10000000 { 16*4882a593Smuzhiyun device_type = "memory"; 17*4882a593Smuzhiyun reg = <0x10000000 0x80000000>; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun regulators { 21*4882a593Smuzhiyun compatible = "simple-bus"; 22*4882a593Smuzhiyun #address-cells = <1>; 23*4882a593Smuzhiyun #size-cells = <0>; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun reg_3p3v: regulator@0 { 26*4882a593Smuzhiyun compatible = "regulator-fixed"; 27*4882a593Smuzhiyun reg = <0>; 28*4882a593Smuzhiyun regulator-name = "3P3V"; 29*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 30*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 31*4882a593Smuzhiyun regulator-always-on; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun reg_usb_otg_vbus: regulator@1 { 35*4882a593Smuzhiyun compatible = "regulator-fixed"; 36*4882a593Smuzhiyun reg = <1>; 37*4882a593Smuzhiyun regulator-name = "usb_otg_vbus"; 38*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 39*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 40*4882a593Smuzhiyun gpio = <&gpio3 22 0>; 41*4882a593Smuzhiyun enable-active-high; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun leds { 46*4882a593Smuzhiyun compatible = "gpio-leds"; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun debug-led { 49*4882a593Smuzhiyun label = "Heartbeat"; 50*4882a593Smuzhiyun gpios = <&gpio3 25 0>; 51*4882a593Smuzhiyun linux,default-trigger = "heartbeat"; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun}; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun&gpmi { 57*4882a593Smuzhiyun pinctrl-names = "default"; 58*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_gpmi_nand>; 59*4882a593Smuzhiyun status = "disabled"; /* gpmi nand conflicts with SD */ 60*4882a593Smuzhiyun}; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun&iomuxc { 63*4882a593Smuzhiyun pinctrl-names = "default"; 64*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_hog>; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun imx6q-arm2 { 67*4882a593Smuzhiyun pinctrl_hog: hoggrp { 68*4882a593Smuzhiyun fsl,pins = < 69*4882a593Smuzhiyun MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x80000000 70*4882a593Smuzhiyun >; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun pinctrl_enet: enetgrp { 74*4882a593Smuzhiyun fsl,pins = < 75*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 76*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 77*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 78*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 79*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 80*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 81*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 82*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 83*4882a593Smuzhiyun MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 84*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 85*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 86*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 87*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 88*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 89*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 90*4882a593Smuzhiyun MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 91*4882a593Smuzhiyun >; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun pinctrl_gpmi_nand: gpminandgrp { 95*4882a593Smuzhiyun fsl,pins = < 96*4882a593Smuzhiyun MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 97*4882a593Smuzhiyun MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 98*4882a593Smuzhiyun MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 99*4882a593Smuzhiyun MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 100*4882a593Smuzhiyun MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 101*4882a593Smuzhiyun MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 102*4882a593Smuzhiyun MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 103*4882a593Smuzhiyun MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 104*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 105*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 106*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 107*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 108*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 109*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 110*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 111*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 112*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 113*4882a593Smuzhiyun >; 114*4882a593Smuzhiyun }; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun pinctrl_uart2: uart2grp { 117*4882a593Smuzhiyun fsl,pins = < 118*4882a593Smuzhiyun MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 119*4882a593Smuzhiyun MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 120*4882a593Smuzhiyun MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 121*4882a593Smuzhiyun MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 122*4882a593Smuzhiyun >; 123*4882a593Smuzhiyun }; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun pinctrl_uart4: uart4grp { 126*4882a593Smuzhiyun fsl,pins = < 127*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 128*4882a593Smuzhiyun MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 129*4882a593Smuzhiyun >; 130*4882a593Smuzhiyun }; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun pinctrl_usbotg: usbotggrp { 133*4882a593Smuzhiyun fsl,pins = < 134*4882a593Smuzhiyun MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 135*4882a593Smuzhiyun >; 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun pinctrl_usdhc3: usdhc3grp { 139*4882a593Smuzhiyun fsl,pins = < 140*4882a593Smuzhiyun MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 141*4882a593Smuzhiyun MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 142*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 143*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 144*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 145*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 146*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 147*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 148*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 149*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 150*4882a593Smuzhiyun >; 151*4882a593Smuzhiyun }; 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun pinctrl_usdhc3_cdwp: usdhc3cdwp { 154*4882a593Smuzhiyun fsl,pins = < 155*4882a593Smuzhiyun MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 156*4882a593Smuzhiyun MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 157*4882a593Smuzhiyun >; 158*4882a593Smuzhiyun }; 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun pinctrl_usdhc4: usdhc4grp { 161*4882a593Smuzhiyun fsl,pins = < 162*4882a593Smuzhiyun MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 163*4882a593Smuzhiyun MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 164*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 165*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 166*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 167*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 168*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 169*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 170*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 171*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 172*4882a593Smuzhiyun >; 173*4882a593Smuzhiyun }; 174*4882a593Smuzhiyun }; 175*4882a593Smuzhiyun}; 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun&fec { 178*4882a593Smuzhiyun pinctrl-names = "default"; 179*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_enet>; 180*4882a593Smuzhiyun phy-mode = "rgmii"; 181*4882a593Smuzhiyun interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, 182*4882a593Smuzhiyun <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; 183*4882a593Smuzhiyun fsl,err006687-workaround-present; 184*4882a593Smuzhiyun status = "okay"; 185*4882a593Smuzhiyun}; 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun&usbotg { 188*4882a593Smuzhiyun vbus-supply = <®_usb_otg_vbus>; 189*4882a593Smuzhiyun pinctrl-names = "default"; 190*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usbotg>; 191*4882a593Smuzhiyun disable-over-current; 192*4882a593Smuzhiyun status = "okay"; 193*4882a593Smuzhiyun}; 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun&usdhc3 { 196*4882a593Smuzhiyun cd-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; 197*4882a593Smuzhiyun wp-gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>; 198*4882a593Smuzhiyun vmmc-supply = <®_3p3v>; 199*4882a593Smuzhiyun pinctrl-names = "default"; 200*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc3 201*4882a593Smuzhiyun &pinctrl_usdhc3_cdwp>; 202*4882a593Smuzhiyun status = "okay"; 203*4882a593Smuzhiyun}; 204*4882a593Smuzhiyun 205*4882a593Smuzhiyun&usdhc4 { 206*4882a593Smuzhiyun non-removable; 207*4882a593Smuzhiyun vmmc-supply = <®_3p3v>; 208*4882a593Smuzhiyun pinctrl-names = "default"; 209*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc4>; 210*4882a593Smuzhiyun status = "okay"; 211*4882a593Smuzhiyun}; 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun&uart2 { 214*4882a593Smuzhiyun pinctrl-names = "default"; 215*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart2>; 216*4882a593Smuzhiyun fsl,dte-mode; 217*4882a593Smuzhiyun uart-has-rtscts; 218*4882a593Smuzhiyun status = "okay"; 219*4882a593Smuzhiyun}; 220*4882a593Smuzhiyun 221*4882a593Smuzhiyun&uart4 { 222*4882a593Smuzhiyun pinctrl-names = "default"; 223*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart4>; 224*4882a593Smuzhiyun status = "okay"; 225*4882a593Smuzhiyun}; 226