1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun// 3*4882a593Smuzhiyun// Copyright (C) 2015-2018 Y Soft Corporation, a.s. 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 6*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h> 7*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 8*4882a593Smuzhiyun#include <dt-bindings/leds/common.h> 9*4882a593Smuzhiyun#include <dt-bindings/pwm/pwm.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun aliases: aliases { 13*4882a593Smuzhiyun ethernet1 = ð1; 14*4882a593Smuzhiyun ethernet2 = ð2; 15*4882a593Smuzhiyun }; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun backlight: backlight { 18*4882a593Smuzhiyun compatible = "pwm-backlight"; 19*4882a593Smuzhiyun pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>; 20*4882a593Smuzhiyun brightness-levels = <0 32 64 128 255>; 21*4882a593Smuzhiyun default-brightness-level = <32>; 22*4882a593Smuzhiyun num-interpolated-steps = <8>; 23*4882a593Smuzhiyun power-supply = <&sw2_reg>; 24*4882a593Smuzhiyun status = "disabled"; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun lcd_display: display { 28*4882a593Smuzhiyun compatible = "fsl,imx-parallel-display"; 29*4882a593Smuzhiyun #address-cells = <1>; 30*4882a593Smuzhiyun #size-cells = <0>; 31*4882a593Smuzhiyun interface-pix-fmt = "rgb24"; 32*4882a593Smuzhiyun pinctrl-names = "default"; 33*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_ipu1>; 34*4882a593Smuzhiyun status = "disabled"; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun port@0 { 37*4882a593Smuzhiyun reg = <0>; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun lcd_display_in: endpoint { 40*4882a593Smuzhiyun remote-endpoint = <&ipu1_di0_disp0>; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun port@1 { 45*4882a593Smuzhiyun reg = <1>; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun lcd_display_out: endpoint { 48*4882a593Smuzhiyun remote-endpoint = <&lcd_panel_in>; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun panel: panel { 54*4882a593Smuzhiyun compatible = "dataimage,scf0700c48ggu18"; 55*4882a593Smuzhiyun power-supply = <&sw2_reg>; 56*4882a593Smuzhiyun status = "disabled"; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun port { 59*4882a593Smuzhiyun lcd_panel_in: endpoint { 60*4882a593Smuzhiyun remote-endpoint = <&lcd_display_out>; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun reg_pcie: regulator-pcie { 66*4882a593Smuzhiyun compatible = "regulator-fixed"; 67*4882a593Smuzhiyun pinctrl-names = "default"; 68*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pcie_reg>; 69*4882a593Smuzhiyun regulator-name = "MPCIE_3V3"; 70*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 71*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 72*4882a593Smuzhiyun gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; 73*4882a593Smuzhiyun enable-active-high; 74*4882a593Smuzhiyun status = "disabled"; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun reg_usb_h1_vbus: regulator-usb-h1-vbus { 78*4882a593Smuzhiyun compatible = "regulator-fixed"; 79*4882a593Smuzhiyun pinctrl-names = "default"; 80*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usbh1_vbus>; 81*4882a593Smuzhiyun regulator-name = "usb_h1_vbus"; 82*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 83*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 84*4882a593Smuzhiyun gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>; 85*4882a593Smuzhiyun enable-active-high; 86*4882a593Smuzhiyun status = "disabled"; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun reg_usb_otg_vbus: regulator-usb-otg-vbus { 90*4882a593Smuzhiyun compatible = "regulator-fixed"; 91*4882a593Smuzhiyun pinctrl-names = "default"; 92*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usbotg_vbus>; 93*4882a593Smuzhiyun regulator-name = "usb_otg_vbus"; 94*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 95*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 96*4882a593Smuzhiyun gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 97*4882a593Smuzhiyun enable-active-high; 98*4882a593Smuzhiyun status = "okay"; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun}; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun&fec { 103*4882a593Smuzhiyun pinctrl-names = "default"; 104*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_enet>; 105*4882a593Smuzhiyun phy-mode = "rgmii-id"; 106*4882a593Smuzhiyun phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; 107*4882a593Smuzhiyun phy-reset-duration = <20>; 108*4882a593Smuzhiyun phy-supply = <&sw2_reg>; 109*4882a593Smuzhiyun status = "okay"; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun fixed-link { 112*4882a593Smuzhiyun speed = <1000>; 113*4882a593Smuzhiyun full-duplex; 114*4882a593Smuzhiyun }; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun mdio { 117*4882a593Smuzhiyun #address-cells = <1>; 118*4882a593Smuzhiyun #size-cells = <0>; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun phy_port2: phy@1 { 121*4882a593Smuzhiyun reg = <1>; 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun phy_port3: phy@2 { 125*4882a593Smuzhiyun reg = <2>; 126*4882a593Smuzhiyun }; 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun switch@10 { 129*4882a593Smuzhiyun compatible = "qca,qca8334"; 130*4882a593Smuzhiyun reg = <10>; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun switch_ports: ports { 133*4882a593Smuzhiyun #address-cells = <1>; 134*4882a593Smuzhiyun #size-cells = <0>; 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun ethphy0: port@0 { 137*4882a593Smuzhiyun reg = <0>; 138*4882a593Smuzhiyun label = "cpu"; 139*4882a593Smuzhiyun phy-mode = "rgmii-id"; 140*4882a593Smuzhiyun ethernet = <&fec>; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun fixed-link { 143*4882a593Smuzhiyun speed = <1000>; 144*4882a593Smuzhiyun full-duplex; 145*4882a593Smuzhiyun }; 146*4882a593Smuzhiyun }; 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun eth2: port@2 { 149*4882a593Smuzhiyun reg = <2>; 150*4882a593Smuzhiyun label = "eth2"; 151*4882a593Smuzhiyun phy-handle = <&phy_port2>; 152*4882a593Smuzhiyun }; 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun eth1: port@3 { 155*4882a593Smuzhiyun reg = <3>; 156*4882a593Smuzhiyun label = "eth1"; 157*4882a593Smuzhiyun phy-handle = <&phy_port3>; 158*4882a593Smuzhiyun }; 159*4882a593Smuzhiyun }; 160*4882a593Smuzhiyun }; 161*4882a593Smuzhiyun }; 162*4882a593Smuzhiyun}; 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun&hdmi { 165*4882a593Smuzhiyun pinctrl-names = "default"; 166*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_hdmi_cec>; 167*4882a593Smuzhiyun ddc-i2c-bus = <&i2c2>; 168*4882a593Smuzhiyun status = "disabled"; 169*4882a593Smuzhiyun}; 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun&i2c2 { 172*4882a593Smuzhiyun clock-frequency = <100000>; 173*4882a593Smuzhiyun pinctrl-names = "default"; 174*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c2>; 175*4882a593Smuzhiyun status = "okay"; 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun pmic@8 { 178*4882a593Smuzhiyun compatible = "fsl,pfuze200"; 179*4882a593Smuzhiyun pinctrl-names = "default"; 180*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pmic>; 181*4882a593Smuzhiyun reg = <0x8>; 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun regulators { 184*4882a593Smuzhiyun sw1a_reg: sw1ab { 185*4882a593Smuzhiyun regulator-min-microvolt = <300000>; 186*4882a593Smuzhiyun regulator-max-microvolt = <1875000>; 187*4882a593Smuzhiyun regulator-boot-on; 188*4882a593Smuzhiyun regulator-always-on; 189*4882a593Smuzhiyun regulator-ramp-delay = <6250>; 190*4882a593Smuzhiyun }; 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun sw2_reg: sw2 { 193*4882a593Smuzhiyun regulator-min-microvolt = <800000>; 194*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 195*4882a593Smuzhiyun regulator-boot-on; 196*4882a593Smuzhiyun regulator-always-on; 197*4882a593Smuzhiyun }; 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun sw3a_reg: sw3a { 200*4882a593Smuzhiyun regulator-min-microvolt = <400000>; 201*4882a593Smuzhiyun regulator-max-microvolt = <1975000>; 202*4882a593Smuzhiyun regulator-boot-on; 203*4882a593Smuzhiyun regulator-always-on; 204*4882a593Smuzhiyun }; 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun sw3b_reg: sw3b { 207*4882a593Smuzhiyun regulator-min-microvolt = <400000>; 208*4882a593Smuzhiyun regulator-max-microvolt = <1975000>; 209*4882a593Smuzhiyun regulator-boot-on; 210*4882a593Smuzhiyun regulator-always-on; 211*4882a593Smuzhiyun }; 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun swbst_reg: swbst { 214*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 215*4882a593Smuzhiyun regulator-max-microvolt = <5150000>; 216*4882a593Smuzhiyun }; 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun vgen1_reg: vgen1 { 219*4882a593Smuzhiyun regulator-min-microvolt = <800000>; 220*4882a593Smuzhiyun regulator-max-microvolt = <1550000>; 221*4882a593Smuzhiyun }; 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun vgen2_reg: vgen2 { 224*4882a593Smuzhiyun regulator-min-microvolt = <800000>; 225*4882a593Smuzhiyun regulator-max-microvolt = <1550000>; 226*4882a593Smuzhiyun }; 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun vgen3_reg: vgen3 { 229*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 230*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 231*4882a593Smuzhiyun regulator-always-on; 232*4882a593Smuzhiyun }; 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun vgen4_reg: vgen4 { 235*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 236*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 237*4882a593Smuzhiyun regulator-always-on; 238*4882a593Smuzhiyun }; 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun vgen5_reg: vgen5 { 241*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 242*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 243*4882a593Smuzhiyun regulator-always-on; 244*4882a593Smuzhiyun }; 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun vgen6_reg: vgen6 { 247*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 248*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 249*4882a593Smuzhiyun regulator-always-on; 250*4882a593Smuzhiyun }; 251*4882a593Smuzhiyun 252*4882a593Smuzhiyun vref_reg: vrefddr { 253*4882a593Smuzhiyun regulator-boot-on; 254*4882a593Smuzhiyun regulator-always-on; 255*4882a593Smuzhiyun }; 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun vsnvs_reg: vsnvs { 258*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 259*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 260*4882a593Smuzhiyun regulator-boot-on; 261*4882a593Smuzhiyun regulator-always-on; 262*4882a593Smuzhiyun }; 263*4882a593Smuzhiyun }; 264*4882a593Smuzhiyun }; 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun leds: led-controller@30 { 267*4882a593Smuzhiyun compatible = "ti,lp5562"; 268*4882a593Smuzhiyun reg = <0x30>; 269*4882a593Smuzhiyun clock-mode = /bits/ 8 <1>; 270*4882a593Smuzhiyun status = "disabled"; 271*4882a593Smuzhiyun #address-cells = <1>; 272*4882a593Smuzhiyun #size-cells = <0>; 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun chan@0 { 275*4882a593Smuzhiyun chan-name = "R"; 276*4882a593Smuzhiyun led-cur = /bits/ 8 <0x20>; 277*4882a593Smuzhiyun max-cur = /bits/ 8 <0x60>; 278*4882a593Smuzhiyun reg = <0>; 279*4882a593Smuzhiyun color = <LED_COLOR_ID_RED>; 280*4882a593Smuzhiyun }; 281*4882a593Smuzhiyun 282*4882a593Smuzhiyun chan@1 { 283*4882a593Smuzhiyun chan-name = "G"; 284*4882a593Smuzhiyun led-cur = /bits/ 8 <0x20>; 285*4882a593Smuzhiyun max-cur = /bits/ 8 <0x60>; 286*4882a593Smuzhiyun reg = <1>; 287*4882a593Smuzhiyun color = <LED_COLOR_ID_GREEN>; 288*4882a593Smuzhiyun }; 289*4882a593Smuzhiyun 290*4882a593Smuzhiyun chan@2 { 291*4882a593Smuzhiyun chan-name = "B"; 292*4882a593Smuzhiyun led-cur = /bits/ 8 <0x20>; 293*4882a593Smuzhiyun max-cur = /bits/ 8 <0x60>; 294*4882a593Smuzhiyun reg = <2>; 295*4882a593Smuzhiyun color = <LED_COLOR_ID_BLUE>; 296*4882a593Smuzhiyun }; 297*4882a593Smuzhiyun 298*4882a593Smuzhiyun chan@3 { 299*4882a593Smuzhiyun chan-name = "W"; 300*4882a593Smuzhiyun led-cur = /bits/ 8 <0x0>; 301*4882a593Smuzhiyun max-cur = /bits/ 8 <0x0>; 302*4882a593Smuzhiyun reg = <3>; 303*4882a593Smuzhiyun color = <LED_COLOR_ID_WHITE>; 304*4882a593Smuzhiyun }; 305*4882a593Smuzhiyun }; 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun eeprom@57 { 308*4882a593Smuzhiyun compatible = "atmel,24c128"; 309*4882a593Smuzhiyun reg = <0x57>; 310*4882a593Smuzhiyun pagesize = <64>; 311*4882a593Smuzhiyun status = "okay"; 312*4882a593Smuzhiyun }; 313*4882a593Smuzhiyun 314*4882a593Smuzhiyun touchscreen: touchscreen@5c { 315*4882a593Smuzhiyun compatible = "pixcir,pixcir_tangoc"; 316*4882a593Smuzhiyun reg = <0x5c>; 317*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_touch>; 318*4882a593Smuzhiyun interrupt-parent = <&gpio4>; 319*4882a593Smuzhiyun interrupts = <5 IRQ_TYPE_EDGE_FALLING>; 320*4882a593Smuzhiyun attb-gpio = <&gpio4 5 GPIO_ACTIVE_HIGH>; 321*4882a593Smuzhiyun reset-gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; 322*4882a593Smuzhiyun touchscreen-size-x = <800>; 323*4882a593Smuzhiyun touchscreen-size-y = <480>; 324*4882a593Smuzhiyun status = "disabled"; 325*4882a593Smuzhiyun }; 326*4882a593Smuzhiyun}; 327*4882a593Smuzhiyun 328*4882a593Smuzhiyun&i2c3 { 329*4882a593Smuzhiyun clock-frequency = <100000>; 330*4882a593Smuzhiyun pinctrl-names = "default"; 331*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c3>; 332*4882a593Smuzhiyun status = "okay"; 333*4882a593Smuzhiyun 334*4882a593Smuzhiyun oled_1309: oled@3c { 335*4882a593Smuzhiyun compatible = "solomon,ssd1309fb-i2c"; 336*4882a593Smuzhiyun reg = <0x3c>; 337*4882a593Smuzhiyun solomon,height = <64>; 338*4882a593Smuzhiyun solomon,width = <128>; 339*4882a593Smuzhiyun solomon,page-offset = <0>; 340*4882a593Smuzhiyun solomon,segment-no-remap; 341*4882a593Smuzhiyun solomon,prechargep2 = <15>; 342*4882a593Smuzhiyun reset-gpios = <&gpio_oled 1 GPIO_ACTIVE_LOW>; 343*4882a593Smuzhiyun vbat-supply = <&sw2_reg>; 344*4882a593Smuzhiyun status = "disabled"; 345*4882a593Smuzhiyun }; 346*4882a593Smuzhiyun 347*4882a593Smuzhiyun oled_1305: oled@3d { 348*4882a593Smuzhiyun compatible = "solomon,ssd1305fb-i2c"; 349*4882a593Smuzhiyun reg = <0x3d>; 350*4882a593Smuzhiyun solomon,height = <64>; 351*4882a593Smuzhiyun solomon,width = <128>; 352*4882a593Smuzhiyun solomon,page-offset = <0>; 353*4882a593Smuzhiyun solomon,prechargep2 = <15>; 354*4882a593Smuzhiyun reset-gpios = <&gpio_oled 1 GPIO_ACTIVE_LOW>; 355*4882a593Smuzhiyun vbat-supply = <&sw2_reg>; 356*4882a593Smuzhiyun status = "disabled"; 357*4882a593Smuzhiyun }; 358*4882a593Smuzhiyun 359*4882a593Smuzhiyun gpio_oled: gpio@41 { 360*4882a593Smuzhiyun compatible = "nxp,pca9536"; 361*4882a593Smuzhiyun gpio-controller; 362*4882a593Smuzhiyun #gpio-cells = <2>; 363*4882a593Smuzhiyun reg = <0x41>; 364*4882a593Smuzhiyun vcc-supply = <&sw2_reg>; 365*4882a593Smuzhiyun status = "disabled"; 366*4882a593Smuzhiyun }; 367*4882a593Smuzhiyun 368*4882a593Smuzhiyun touchkeys: keys@5a { 369*4882a593Smuzhiyun compatible = "fsl,mpr121-touchkey"; 370*4882a593Smuzhiyun reg = <0x5a>; 371*4882a593Smuzhiyun vdd-supply = <&sw2_reg>; 372*4882a593Smuzhiyun autorepeat; 373*4882a593Smuzhiyun linux,keycodes = <KEY_1>, <KEY_2>, <KEY_3>, <KEY_4>, <KEY_5>, 374*4882a593Smuzhiyun <KEY_6>, <KEY_7>, <KEY_8>, <KEY_9>, 375*4882a593Smuzhiyun <KEY_BACKSPACE>, <KEY_0>, <KEY_ENTER>; 376*4882a593Smuzhiyun poll-interval = <50>; 377*4882a593Smuzhiyun status = "disabled"; 378*4882a593Smuzhiyun }; 379*4882a593Smuzhiyun}; 380*4882a593Smuzhiyun 381*4882a593Smuzhiyun&iomuxc { 382*4882a593Smuzhiyun pinctrl_enet: enetgrp { 383*4882a593Smuzhiyun fsl,pins = < 384*4882a593Smuzhiyun MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b020 385*4882a593Smuzhiyun MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b020 386*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b020 387*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b020 388*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b020 389*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b020 390*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b020 391*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b020 392*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b020 393*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b020 394*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b020 395*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b020 396*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b020 397*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b020 398*4882a593Smuzhiyun MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b010 399*4882a593Smuzhiyun MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b010 400*4882a593Smuzhiyun MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b098 401*4882a593Smuzhiyun >; 402*4882a593Smuzhiyun }; 403*4882a593Smuzhiyun 404*4882a593Smuzhiyun pinctrl_hdmi_cec: hdmicecgrp { 405*4882a593Smuzhiyun fsl,pins = < 406*4882a593Smuzhiyun MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1b898 407*4882a593Smuzhiyun >; 408*4882a593Smuzhiyun }; 409*4882a593Smuzhiyun 410*4882a593Smuzhiyun pinctrl_i2c2: i2c2grp { 411*4882a593Smuzhiyun fsl,pins = < 412*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b899 413*4882a593Smuzhiyun MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b899 414*4882a593Smuzhiyun >; 415*4882a593Smuzhiyun }; 416*4882a593Smuzhiyun 417*4882a593Smuzhiyun pinctrl_i2c3: i2c3grp { 418*4882a593Smuzhiyun fsl,pins = < 419*4882a593Smuzhiyun MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b899 420*4882a593Smuzhiyun MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b899 421*4882a593Smuzhiyun >; 422*4882a593Smuzhiyun }; 423*4882a593Smuzhiyun 424*4882a593Smuzhiyun pinctrl_ipu1: ipu1grp { 425*4882a593Smuzhiyun fsl,pins = < 426*4882a593Smuzhiyun MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 427*4882a593Smuzhiyun MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 428*4882a593Smuzhiyun MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 429*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 430*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 431*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 432*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 433*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 434*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 435*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 436*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 437*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 438*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 439*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 440*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 441*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 442*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 443*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 444*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 445*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 446*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 447*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 448*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 449*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 450*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 451*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 452*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 453*4882a593Smuzhiyun >; 454*4882a593Smuzhiyun }; 455*4882a593Smuzhiyun 456*4882a593Smuzhiyun pinctrl_pcie: pciegrp { 457*4882a593Smuzhiyun fsl,pins = < 458*4882a593Smuzhiyun MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b098 459*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b098 460*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b098 461*4882a593Smuzhiyun >; 462*4882a593Smuzhiyun }; 463*4882a593Smuzhiyun 464*4882a593Smuzhiyun pinctrl_pcie_reg: pciereggrp { 465*4882a593Smuzhiyun fsl,pins = < 466*4882a593Smuzhiyun MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b098 467*4882a593Smuzhiyun >; 468*4882a593Smuzhiyun }; 469*4882a593Smuzhiyun 470*4882a593Smuzhiyun pinctrl_pmic: pmicgrp { 471*4882a593Smuzhiyun fsl,pins = < 472*4882a593Smuzhiyun MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b098 473*4882a593Smuzhiyun >; 474*4882a593Smuzhiyun }; 475*4882a593Smuzhiyun 476*4882a593Smuzhiyun pinctrl_pwm1: pwm1grp { 477*4882a593Smuzhiyun fsl,pins = < 478*4882a593Smuzhiyun MX6QDL_PAD_GPIO_9__PWM1_OUT 0x8 479*4882a593Smuzhiyun >; 480*4882a593Smuzhiyun }; 481*4882a593Smuzhiyun 482*4882a593Smuzhiyun pinctrl_touch: touchgrp { 483*4882a593Smuzhiyun fsl,pins = < 484*4882a593Smuzhiyun MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b098 485*4882a593Smuzhiyun MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b098 486*4882a593Smuzhiyun >; 487*4882a593Smuzhiyun }; 488*4882a593Smuzhiyun 489*4882a593Smuzhiyun pinctrl_uart1: uart1grp { 490*4882a593Smuzhiyun fsl,pins = < 491*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0a8 492*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0a8 493*4882a593Smuzhiyun >; 494*4882a593Smuzhiyun }; 495*4882a593Smuzhiyun 496*4882a593Smuzhiyun pinctrl_uart2: uart2grp { 497*4882a593Smuzhiyun fsl,pins = < 498*4882a593Smuzhiyun MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b098 499*4882a593Smuzhiyun MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b098 500*4882a593Smuzhiyun >; 501*4882a593Smuzhiyun }; 502*4882a593Smuzhiyun 503*4882a593Smuzhiyun pinctrl_usbh1: usbh1grp { 504*4882a593Smuzhiyun fsl,pins = < 505*4882a593Smuzhiyun MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1b098 506*4882a593Smuzhiyun >; 507*4882a593Smuzhiyun }; 508*4882a593Smuzhiyun 509*4882a593Smuzhiyun pinctrl_usbh1_vbus: usbh1-vbus { 510*4882a593Smuzhiyun fsl,pins = < 511*4882a593Smuzhiyun MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x98 512*4882a593Smuzhiyun >; 513*4882a593Smuzhiyun }; 514*4882a593Smuzhiyun 515*4882a593Smuzhiyun pinctrl_usbotg: usbotggrp { 516*4882a593Smuzhiyun fsl,pins = < 517*4882a593Smuzhiyun MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1b098 518*4882a593Smuzhiyun MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b098 519*4882a593Smuzhiyun >; 520*4882a593Smuzhiyun }; 521*4882a593Smuzhiyun 522*4882a593Smuzhiyun pinctrl_usbotg_vbus: usbotg-vbus { 523*4882a593Smuzhiyun fsl,pins = < 524*4882a593Smuzhiyun MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x98 525*4882a593Smuzhiyun >; 526*4882a593Smuzhiyun }; 527*4882a593Smuzhiyun 528*4882a593Smuzhiyun pinctrl_usdhc3: usdhc3grp { 529*4882a593Smuzhiyun fsl,pins = < 530*4882a593Smuzhiyun MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b018 531*4882a593Smuzhiyun MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b018 532*4882a593Smuzhiyun MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 533*4882a593Smuzhiyun MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 534*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 535*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 536*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 537*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 538*4882a593Smuzhiyun >; 539*4882a593Smuzhiyun }; 540*4882a593Smuzhiyun 541*4882a593Smuzhiyun pinctrl_usdhc4: usdhc4grp { 542*4882a593Smuzhiyun fsl,pins = < 543*4882a593Smuzhiyun MX6QDL_PAD_SD4_CMD__SD4_CMD 0x1f069 544*4882a593Smuzhiyun MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10069 545*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17069 546*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17069 547*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17069 548*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17069 549*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17069 550*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17069 551*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17069 552*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17069 553*4882a593Smuzhiyun >; 554*4882a593Smuzhiyun }; 555*4882a593Smuzhiyun 556*4882a593Smuzhiyun pinctrl_wdog: wdoggrp { 557*4882a593Smuzhiyun fsl,pins = < 558*4882a593Smuzhiyun MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0 559*4882a593Smuzhiyun >; 560*4882a593Smuzhiyun }; 561*4882a593Smuzhiyun}; 562*4882a593Smuzhiyun 563*4882a593Smuzhiyun&ipu1_di0_disp0 { 564*4882a593Smuzhiyun remote-endpoint = <&lcd_display_in>; 565*4882a593Smuzhiyun}; 566*4882a593Smuzhiyun 567*4882a593Smuzhiyun&pcie { 568*4882a593Smuzhiyun pinctrl-names = "default"; 569*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pcie>; 570*4882a593Smuzhiyun reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; 571*4882a593Smuzhiyun vpcie-supply = <®_pcie>; 572*4882a593Smuzhiyun status = "disabled"; 573*4882a593Smuzhiyun}; 574*4882a593Smuzhiyun 575*4882a593Smuzhiyun&pwm1 { 576*4882a593Smuzhiyun pinctrl-names = "default"; 577*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pwm1>; 578*4882a593Smuzhiyun status = "disabled"; 579*4882a593Smuzhiyun}; 580*4882a593Smuzhiyun 581*4882a593Smuzhiyun&uart1 { 582*4882a593Smuzhiyun pinctrl-names = "default"; 583*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart1>; 584*4882a593Smuzhiyun status = "okay"; 585*4882a593Smuzhiyun}; 586*4882a593Smuzhiyun 587*4882a593Smuzhiyun&uart2 { 588*4882a593Smuzhiyun pinctrl-names = "default"; 589*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart2>; 590*4882a593Smuzhiyun status = "okay"; 591*4882a593Smuzhiyun}; 592*4882a593Smuzhiyun 593*4882a593Smuzhiyun&usbh1 { 594*4882a593Smuzhiyun pinctrl-names = "default"; 595*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usbh1>; 596*4882a593Smuzhiyun vbus-supply = <®_usb_h1_vbus>; 597*4882a593Smuzhiyun over-current-active-low; 598*4882a593Smuzhiyun status = "disabled"; 599*4882a593Smuzhiyun}; 600*4882a593Smuzhiyun 601*4882a593Smuzhiyun&usbotg { 602*4882a593Smuzhiyun pinctrl-names = "default"; 603*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usbotg>; 604*4882a593Smuzhiyun vbus-supply = <®_usb_otg_vbus>; 605*4882a593Smuzhiyun over-current-active-low; 606*4882a593Smuzhiyun srp-disable; 607*4882a593Smuzhiyun hnp-disable; 608*4882a593Smuzhiyun adp-disable; 609*4882a593Smuzhiyun status = "okay"; 610*4882a593Smuzhiyun}; 611*4882a593Smuzhiyun 612*4882a593Smuzhiyun&usbphy1 { 613*4882a593Smuzhiyun fsl,tx-d-cal = <106>; 614*4882a593Smuzhiyun status = "okay"; 615*4882a593Smuzhiyun}; 616*4882a593Smuzhiyun 617*4882a593Smuzhiyun&usbphy2 { 618*4882a593Smuzhiyun fsl,tx-d-cal = <109>; 619*4882a593Smuzhiyun status = "disabled"; 620*4882a593Smuzhiyun}; 621*4882a593Smuzhiyun 622*4882a593Smuzhiyun&usdhc3 { 623*4882a593Smuzhiyun pinctrl-names = "default"; 624*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc3>; 625*4882a593Smuzhiyun bus-width = <4>; 626*4882a593Smuzhiyun cd-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>; 627*4882a593Smuzhiyun wp-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; 628*4882a593Smuzhiyun no-1-8-v; 629*4882a593Smuzhiyun keep-power-in-suspend; 630*4882a593Smuzhiyun wakeup-source; 631*4882a593Smuzhiyun vmmc-supply = <&sw2_reg>; 632*4882a593Smuzhiyun status = "disabled"; 633*4882a593Smuzhiyun}; 634*4882a593Smuzhiyun 635*4882a593Smuzhiyun&usdhc4 { 636*4882a593Smuzhiyun pinctrl-names = "default"; 637*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc4>; 638*4882a593Smuzhiyun bus-width = <8>; 639*4882a593Smuzhiyun non-removable; 640*4882a593Smuzhiyun no-1-8-v; 641*4882a593Smuzhiyun keep-power-in-suspend; 642*4882a593Smuzhiyun vmmc-supply = <&sw2_reg>; 643*4882a593Smuzhiyun status = "okay"; 644*4882a593Smuzhiyun}; 645*4882a593Smuzhiyun 646*4882a593Smuzhiyun&wdog1 { 647*4882a593Smuzhiyun status = "disabled"; 648*4882a593Smuzhiyun}; 649*4882a593Smuzhiyun 650*4882a593Smuzhiyun&wdog2 { 651*4882a593Smuzhiyun pinctrl-names = "default"; 652*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_wdog>; 653*4882a593Smuzhiyun fsl,ext-reset-output; 654*4882a593Smuzhiyun status = "okay"; 655*4882a593Smuzhiyun}; 656