xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/imx6dl-prtrvt.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2014 Protonic Holland
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun/dts-v1/;
7*4882a593Smuzhiyun#include "imx6dl.dtsi"
8*4882a593Smuzhiyun#include "imx6qdl-prti6q.dtsi"
9*4882a593Smuzhiyun#include <dt-bindings/leds/common.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun/ {
12*4882a593Smuzhiyun	model = "Protonic RVT board";
13*4882a593Smuzhiyun	compatible = "prt,prtrvt", "fsl,imx6dl";
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun	memory@10000000 {
16*4882a593Smuzhiyun		device_type = "memory";
17*4882a593Smuzhiyun		reg = <0x10000000 0x10000000>;
18*4882a593Smuzhiyun	};
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun	leds {
21*4882a593Smuzhiyun		compatible = "gpio-leds";
22*4882a593Smuzhiyun		pinctrl-names = "default";
23*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_leds>;
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun		led-debug0 {
26*4882a593Smuzhiyun			function = LED_FUNCTION_STATUS;
27*4882a593Smuzhiyun			gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
28*4882a593Smuzhiyun			linux,default-trigger = "heartbeat";
29*4882a593Smuzhiyun		};
30*4882a593Smuzhiyun	};
31*4882a593Smuzhiyun};
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun&can1 {
34*4882a593Smuzhiyun	pinctrl-names = "default";
35*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_can1 &pinctrl_can1phy>;
36*4882a593Smuzhiyun	status = "okay";
37*4882a593Smuzhiyun};
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun&ecspi1 {
40*4882a593Smuzhiyun	cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
41*4882a593Smuzhiyun	pinctrl-names = "default";
42*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_ecspi1>;
43*4882a593Smuzhiyun	status = "okay";
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun	flash@0 {
46*4882a593Smuzhiyun		compatible = "jedec,spi-nor";
47*4882a593Smuzhiyun		reg = <0>;
48*4882a593Smuzhiyun		spi-max-frequency = <20000000>;
49*4882a593Smuzhiyun		#address-cells = <1>;
50*4882a593Smuzhiyun		#size-cells = <1>;
51*4882a593Smuzhiyun	};
52*4882a593Smuzhiyun};
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun&ecspi3 {
55*4882a593Smuzhiyun	cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
56*4882a593Smuzhiyun	pinctrl-names = "default";
57*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_ecspi3>;
58*4882a593Smuzhiyun	status = "okay";
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun	nfc@0 {
61*4882a593Smuzhiyun		compatible = "ti,trf7970a";
62*4882a593Smuzhiyun		reg = <0>;
63*4882a593Smuzhiyun		pinctrl-names = "default";
64*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_nfc>;
65*4882a593Smuzhiyun		spi-max-frequency = <2000000>;
66*4882a593Smuzhiyun		interrupts-extended = <&gpio5 14 IRQ_TYPE_LEVEL_LOW>;
67*4882a593Smuzhiyun		ti,enable-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>,
68*4882a593Smuzhiyun				  <&gpio5 11 GPIO_ACTIVE_LOW>;
69*4882a593Smuzhiyun		vin-supply = <&reg_3v3>;
70*4882a593Smuzhiyun		vin-voltage-override = <3100000>;
71*4882a593Smuzhiyun		autosuspend-delay = <30000>;
72*4882a593Smuzhiyun		irq-status-read-quirk;
73*4882a593Smuzhiyun		en2-rf-quirk;
74*4882a593Smuzhiyun		t5t-rmb-extra-byte-quirk;
75*4882a593Smuzhiyun		status = "okay";
76*4882a593Smuzhiyun	};
77*4882a593Smuzhiyun};
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun&i2c3 {
80*4882a593Smuzhiyun	adc@49 {
81*4882a593Smuzhiyun		compatible = "ti,ads1015";
82*4882a593Smuzhiyun		reg = <0x49>;
83*4882a593Smuzhiyun		#address-cells = <1>;
84*4882a593Smuzhiyun		#size-cells = <0>;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun		/* nc */
87*4882a593Smuzhiyun		channel@4 {
88*4882a593Smuzhiyun			reg = <4>;
89*4882a593Smuzhiyun			ti,gain = <3>;
90*4882a593Smuzhiyun			ti,datarate = <3>;
91*4882a593Smuzhiyun		};
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun		/* nc */
94*4882a593Smuzhiyun		channel@5 {
95*4882a593Smuzhiyun			reg = <5>;
96*4882a593Smuzhiyun			ti,gain = <3>;
97*4882a593Smuzhiyun			ti,datarate = <3>;
98*4882a593Smuzhiyun		};
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun		/* can1_l */
101*4882a593Smuzhiyun		channel@6 {
102*4882a593Smuzhiyun			reg = <6>;
103*4882a593Smuzhiyun			ti,gain = <3>;
104*4882a593Smuzhiyun			ti,datarate = <3>;
105*4882a593Smuzhiyun		};
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun		/* can1_h */
108*4882a593Smuzhiyun		channel@7 {
109*4882a593Smuzhiyun			reg = <7>;
110*4882a593Smuzhiyun			ti,gain = <3>;
111*4882a593Smuzhiyun			ti,datarate = <3>;
112*4882a593Smuzhiyun		};
113*4882a593Smuzhiyun	};
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun	rtc@51 {
116*4882a593Smuzhiyun		compatible = "nxp,pcf8563";
117*4882a593Smuzhiyun		reg = <0x51>;
118*4882a593Smuzhiyun	};
119*4882a593Smuzhiyun};
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun&pcie {
122*4882a593Smuzhiyun	status = "okay";
123*4882a593Smuzhiyun};
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun&usbh1 {
126*4882a593Smuzhiyun	status = "disabled";
127*4882a593Smuzhiyun};
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun&vpu {
130*4882a593Smuzhiyun	status = "disabled";
131*4882a593Smuzhiyun};
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun&iomuxc {
134*4882a593Smuzhiyun	pinctrl_can1phy: can1phy {
135*4882a593Smuzhiyun		fsl,pins = <
136*4882a593Smuzhiyun			/* CAN1_SR */
137*4882a593Smuzhiyun			MX6QDL_PAD_KEY_COL3__GPIO4_IO12	0x13070
138*4882a593Smuzhiyun			/* CAN1_TERM */
139*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_0__GPIO1_IO00	0x1b0b0
140*4882a593Smuzhiyun		>;
141*4882a593Smuzhiyun	};
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun	pinctrl_ecspi1: ecspi1grp {
144*4882a593Smuzhiyun		fsl,pins = <
145*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D17__ECSPI1_MISO		0x100b1
146*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D18__ECSPI1_MOSI		0x100b1
147*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D16__ECSPI1_SCLK		0x100b1
148*4882a593Smuzhiyun			/* CS */
149*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D19__GPIO3_IO19		0x000b1
150*4882a593Smuzhiyun		>;
151*4882a593Smuzhiyun	};
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun	pinctrl_ecspi3: ecspi3grp {
154*4882a593Smuzhiyun		fsl,pins = <
155*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK	0x100b1
156*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI	0x100b1
157*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO	0x100b1
158*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24	0x000b1
159*4882a593Smuzhiyun		>;
160*4882a593Smuzhiyun	};
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun	pinctrl_leds: ledsgrp {
163*4882a593Smuzhiyun		fsl,pins = <
164*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_8__GPIO1_IO08		0x1b0b0
165*4882a593Smuzhiyun		>;
166*4882a593Smuzhiyun	};
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun	pinctrl_nfc: nfcgrp {
169*4882a593Smuzhiyun		fsl,pins = <
170*4882a593Smuzhiyun			/* NFC_ASK_OOK */
171*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09	0x100b1
172*4882a593Smuzhiyun			/* NFC_PWR_EN */
173*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10	0x100b1
174*4882a593Smuzhiyun			/* NFC_EN2 */
175*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11	0x100b1
176*4882a593Smuzhiyun			/* NFC_EN */
177*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12	0x100b1
178*4882a593Smuzhiyun			/* NFC_MOD */
179*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13	0x100b1
180*4882a593Smuzhiyun			/* NFC_IRQ */
181*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14	0x100b1
182*4882a593Smuzhiyun		>;
183*4882a593Smuzhiyun	};
184*4882a593Smuzhiyun};
185