xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/imx6dl-mamoj.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (C) 2018 BTicino
4*4882a593Smuzhiyun * Copyright (C) 2018 Amarula Solutions B.V.
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun/dts-v1/;
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
10*4882a593Smuzhiyun#include "imx6dl.dtsi"
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun/ {
13*4882a593Smuzhiyun	model = "BTicino i.MX6DL Mamoj board";
14*4882a593Smuzhiyun	compatible = "bticino,imx6dl-mamoj", "fsl,imx6dl";
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun	/* Will be filled by the bootloader */
17*4882a593Smuzhiyun	memory@10000000 {
18*4882a593Smuzhiyun		device_type = "memory";
19*4882a593Smuzhiyun		reg = <0x10000000 0>;
20*4882a593Smuzhiyun	};
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun	backlight_lcd: backlight-lcd {
23*4882a593Smuzhiyun		compatible = "pwm-backlight";
24*4882a593Smuzhiyun		pwms = <&pwm3 0 25000>; /* 25000ns -> 40kHz */
25*4882a593Smuzhiyun		brightness-levels = <0 4 8 16 32 64 128 160 192 224 255>;
26*4882a593Smuzhiyun		default-brightness-level = <7>;
27*4882a593Smuzhiyun	};
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun	display: disp0 {
30*4882a593Smuzhiyun		compatible = "fsl,imx-parallel-display";
31*4882a593Smuzhiyun		#address-cells = <1>;
32*4882a593Smuzhiyun		#size-cells = <0>;
33*4882a593Smuzhiyun		interface-pix-fmt = "rgb24";
34*4882a593Smuzhiyun		pinctrl-names = "default";
35*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_ipu1_lcdif>;
36*4882a593Smuzhiyun		status = "okay";
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun		port@0 {
39*4882a593Smuzhiyun			reg = <0>;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun			lcd_display_in: endpoint {
42*4882a593Smuzhiyun				remote-endpoint = <&ipu1_di0_disp0>;
43*4882a593Smuzhiyun			};
44*4882a593Smuzhiyun		};
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun		port@1 {
47*4882a593Smuzhiyun			reg = <1>;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun			lcd_display_out: endpoint {
50*4882a593Smuzhiyun				remote-endpoint = <&lcd_panel_in>;
51*4882a593Smuzhiyun			};
52*4882a593Smuzhiyun		};
53*4882a593Smuzhiyun	};
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun	panel-lcd {
56*4882a593Smuzhiyun		compatible = "rocktech,rk070er9427";
57*4882a593Smuzhiyun		backlight = <&backlight_lcd>;
58*4882a593Smuzhiyun		power-supply = <&reg_lcd_lr>;
59*4882a593Smuzhiyun		pinctrl-names = "default";
60*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_ipu1_lcdif_pwr>;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun		port {
63*4882a593Smuzhiyun			lcd_panel_in: endpoint {
64*4882a593Smuzhiyun				remote-endpoint = <&lcd_display_out>;
65*4882a593Smuzhiyun			};
66*4882a593Smuzhiyun		};
67*4882a593Smuzhiyun	};
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun	reg_lcd_3v3: regulator-lcd-dvdd {
70*4882a593Smuzhiyun		compatible = "regulator-fixed";
71*4882a593Smuzhiyun		regulator-name = "lcd-dvdd";
72*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
73*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
74*4882a593Smuzhiyun		gpio = <&gpio3 1 0>;
75*4882a593Smuzhiyun		enable-active-high;
76*4882a593Smuzhiyun		startup-delay-us = <21000>;
77*4882a593Smuzhiyun	};
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun	reg_lcd_power: regulator-lcd-power {
80*4882a593Smuzhiyun		compatible = "regulator-fixed";
81*4882a593Smuzhiyun		regulator-name = "lcd-enable";
82*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
83*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
84*4882a593Smuzhiyun		gpio = <&gpio3 6 0>;
85*4882a593Smuzhiyun		enable-active-high;
86*4882a593Smuzhiyun		vin-supply = <&reg_lcd_3v3>;
87*4882a593Smuzhiyun	};
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun	reg_lcd_vgl: regulator-lcd-vgl {
90*4882a593Smuzhiyun		compatible = "regulator-fixed";
91*4882a593Smuzhiyun		regulator-name = "lcd-vgl";
92*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
93*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
94*4882a593Smuzhiyun		gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>;
95*4882a593Smuzhiyun		startup-delay-us = <6000>;
96*4882a593Smuzhiyun		enable-active-high;
97*4882a593Smuzhiyun		vin-supply = <&reg_lcd_power>;
98*4882a593Smuzhiyun	};
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun	reg_lcd_vgh: regulator-lcd-vgh {
101*4882a593Smuzhiyun		compatible = "regulator-fixed";
102*4882a593Smuzhiyun		regulator-name = "lcd-vgh";
103*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
104*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
105*4882a593Smuzhiyun		gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
106*4882a593Smuzhiyun		startup-delay-us = <6000>;
107*4882a593Smuzhiyun		enable-active-high;
108*4882a593Smuzhiyun		vin-supply = <&reg_lcd_avdd>;
109*4882a593Smuzhiyun	};
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun	reg_lcd_vcom: regulator-lcd-vcom {
112*4882a593Smuzhiyun		compatible = "regulator-fixed";
113*4882a593Smuzhiyun		regulator-name = "lcd-vcom";
114*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
115*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
116*4882a593Smuzhiyun		gpio = <&gpio4 14 GPIO_ACTIVE_HIGH>;
117*4882a593Smuzhiyun		startup-delay-us = <11000>;
118*4882a593Smuzhiyun		enable-active-high;
119*4882a593Smuzhiyun		vin-supply = <&reg_lcd_vgh>;
120*4882a593Smuzhiyun	};
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun	reg_lcd_lr: regulator-lcd-lr {
123*4882a593Smuzhiyun		compatible = "regulator-fixed";
124*4882a593Smuzhiyun		regulator-name = "lcd-lr";
125*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
126*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
127*4882a593Smuzhiyun		gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
128*4882a593Smuzhiyun		enable-active-high;
129*4882a593Smuzhiyun		vin-supply = <&reg_lcd_vcom>;
130*4882a593Smuzhiyun	};
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun	reg_lcd_avdd: regulator-lcd-avdd {
133*4882a593Smuzhiyun		compatible = "regulator-fixed";
134*4882a593Smuzhiyun		regulator-name = "lcd-avdd";
135*4882a593Smuzhiyun		regulator-min-microvolt = <10280000>;
136*4882a593Smuzhiyun		regulator-max-microvolt = <10280000>;
137*4882a593Smuzhiyun		gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>;
138*4882a593Smuzhiyun		startup-delay-us = <6000>;
139*4882a593Smuzhiyun		enable-active-high;
140*4882a593Smuzhiyun		vin-supply = <&reg_lcd_vgl>;
141*4882a593Smuzhiyun	};
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun	reg_usb_host: regulator-usb-vbus {
144*4882a593Smuzhiyun		compatible = "regulator-fixed";
145*4882a593Smuzhiyun		regulator-name = "usbhost-vbus";
146*4882a593Smuzhiyun		pinctrl-names = "default";
147*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_usbhost>;
148*4882a593Smuzhiyun		regulator-min-microvolt = <50000000>;
149*4882a593Smuzhiyun		regulator-max-microvolt = <50000000>;
150*4882a593Smuzhiyun		gpio = <&gpio6 6 GPIO_ACTIVE_HIGH>;
151*4882a593Smuzhiyun		enable-active-high;
152*4882a593Smuzhiyun	};
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun	reg_wl18xx_vmmc:  regulator-wl18xx-vmcc {
155*4882a593Smuzhiyun		compatible = "regulator-fixed";
156*4882a593Smuzhiyun		regulator-name = "vwl1807";
157*4882a593Smuzhiyun		pinctrl-names = "default";
158*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_wlan>;
159*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
160*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
161*4882a593Smuzhiyun		gpio = <&gpio6 21 GPIO_ACTIVE_HIGH>;
162*4882a593Smuzhiyun		startup-delay-us = <70000>;
163*4882a593Smuzhiyun		enable-active-high;
164*4882a593Smuzhiyun	};
165*4882a593Smuzhiyun};
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun&fec {
168*4882a593Smuzhiyun	pinctrl-names = "default";
169*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_enet>;
170*4882a593Smuzhiyun	phy-mode = "mii";
171*4882a593Smuzhiyun	status = "okay";
172*4882a593Smuzhiyun};
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun&i2c3 {
175*4882a593Smuzhiyun	clock-frequency = <400000>;
176*4882a593Smuzhiyun	pinctrl-names = "default";
177*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c3>;
178*4882a593Smuzhiyun	status = "okay";
179*4882a593Smuzhiyun};
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun&i2c4 {
182*4882a593Smuzhiyun	clock-frequency = <100000>;
183*4882a593Smuzhiyun	pinctrl-names = "default";
184*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c4>;
185*4882a593Smuzhiyun	status = "okay";
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun	pfuze100: pmic@8 {
188*4882a593Smuzhiyun		compatible = "fsl,pfuze100";
189*4882a593Smuzhiyun		reg = <0x08>;
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun		regulators {
192*4882a593Smuzhiyun			/* CPU vdd_arm core */
193*4882a593Smuzhiyun			sw1a_reg: sw1ab {
194*4882a593Smuzhiyun				regulator-min-microvolt = <300000>;
195*4882a593Smuzhiyun				regulator-max-microvolt = <1875000>;
196*4882a593Smuzhiyun				regulator-boot-on;
197*4882a593Smuzhiyun				regulator-always-on;
198*4882a593Smuzhiyun				regulator-ramp-delay = <6250>;
199*4882a593Smuzhiyun			};
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun			/* SOC vdd_soc */
202*4882a593Smuzhiyun			sw1c_reg: sw1c {
203*4882a593Smuzhiyun				regulator-min-microvolt = <300000>;
204*4882a593Smuzhiyun				regulator-max-microvolt = <1875000>;
205*4882a593Smuzhiyun				regulator-boot-on;
206*4882a593Smuzhiyun				regulator-always-on;
207*4882a593Smuzhiyun				regulator-ramp-delay = <6250>;
208*4882a593Smuzhiyun			};
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun			/* I/O power GEN_3V3 */
211*4882a593Smuzhiyun			sw2_reg: sw2 {
212*4882a593Smuzhiyun				regulator-min-microvolt = <800000>;
213*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
214*4882a593Smuzhiyun				regulator-boot-on;
215*4882a593Smuzhiyun				regulator-always-on;
216*4882a593Smuzhiyun			};
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun			/* DDR memory */
219*4882a593Smuzhiyun			sw3a_reg: sw3a {
220*4882a593Smuzhiyun				regulator-min-microvolt = <400000>;
221*4882a593Smuzhiyun				regulator-max-microvolt = <1975000>;
222*4882a593Smuzhiyun				regulator-boot-on;
223*4882a593Smuzhiyun				regulator-always-on;
224*4882a593Smuzhiyun			};
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun			/* DDR memory */
227*4882a593Smuzhiyun			sw3b_reg: sw3b {
228*4882a593Smuzhiyun				regulator-min-microvolt = <400000>;
229*4882a593Smuzhiyun				regulator-max-microvolt = <1975000>;
230*4882a593Smuzhiyun				regulator-boot-on;
231*4882a593Smuzhiyun				regulator-always-on;
232*4882a593Smuzhiyun			};
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun			/* not used */
235*4882a593Smuzhiyun			sw4_reg: sw4 {
236*4882a593Smuzhiyun				regulator-min-microvolt = <800000>;
237*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
238*4882a593Smuzhiyun			};
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun			/* not used */
241*4882a593Smuzhiyun			swbst_reg: swbst {
242*4882a593Smuzhiyun				regulator-min-microvolt = <5000000>;
243*4882a593Smuzhiyun				regulator-max-microvolt = <5150000>;
244*4882a593Smuzhiyun			};
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun			/* PMIC vsnvs. EX boot mode */
247*4882a593Smuzhiyun			snvs_reg: vsnvs {
248*4882a593Smuzhiyun				regulator-min-microvolt = <1000000>;
249*4882a593Smuzhiyun				regulator-max-microvolt = <3000000>;
250*4882a593Smuzhiyun				regulator-boot-on;
251*4882a593Smuzhiyun				regulator-always-on;
252*4882a593Smuzhiyun			};
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun			vref_reg: vrefddr {
255*4882a593Smuzhiyun				regulator-boot-on;
256*4882a593Smuzhiyun				regulator-always-on;
257*4882a593Smuzhiyun			};
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun			/* not used */
260*4882a593Smuzhiyun			vgen1_reg: vgen1 {
261*4882a593Smuzhiyun				regulator-min-microvolt = <800000>;
262*4882a593Smuzhiyun				regulator-max-microvolt = <1550000>;
263*4882a593Smuzhiyun			};
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun			/* not used */
266*4882a593Smuzhiyun			vgen2_reg: vgen2 {
267*4882a593Smuzhiyun				regulator-min-microvolt = <800000>;
268*4882a593Smuzhiyun				regulator-max-microvolt = <1550000>;
269*4882a593Smuzhiyun			};
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun			/* not used */
272*4882a593Smuzhiyun			vgen3_reg: vgen3 {
273*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
274*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
275*4882a593Smuzhiyun			};
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun			/* 1v8 general power */
278*4882a593Smuzhiyun			vgen4_reg: vgen4 {
279*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
280*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
281*4882a593Smuzhiyun				regulator-always-on;
282*4882a593Smuzhiyun			};
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun			/* 2v8 general power IMX6 */
285*4882a593Smuzhiyun			vgen5_reg: vgen5 {
286*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
287*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
288*4882a593Smuzhiyun				regulator-always-on;
289*4882a593Smuzhiyun			};
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun			/* 3v3 Ethernet */
292*4882a593Smuzhiyun			vgen6_reg: vgen6 {
293*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
294*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
295*4882a593Smuzhiyun				regulator-always-on;
296*4882a593Smuzhiyun			};
297*4882a593Smuzhiyun		};
298*4882a593Smuzhiyun	};
299*4882a593Smuzhiyun};
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun&ipu1_di0_disp0 {
302*4882a593Smuzhiyun	remote-endpoint = <&lcd_display_in>;
303*4882a593Smuzhiyun};
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun&pwm3 {
306*4882a593Smuzhiyun	#pwm-cells = <2>;
307*4882a593Smuzhiyun	pinctrl-names = "default";
308*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pwm3>;
309*4882a593Smuzhiyun	status = "okay";
310*4882a593Smuzhiyun};
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun&uart3 {
313*4882a593Smuzhiyun	pinctrl-names = "default";
314*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart3>;
315*4882a593Smuzhiyun	status = "okay";
316*4882a593Smuzhiyun};
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun&usbh1 {
319*4882a593Smuzhiyun	vbus-supply = <&reg_usb_host>;
320*4882a593Smuzhiyun	status = "okay";
321*4882a593Smuzhiyun};
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun&usbotg {
324*4882a593Smuzhiyun	dr_mode = "peripheral";
325*4882a593Smuzhiyun	status = "okay";
326*4882a593Smuzhiyun};
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun&usdhc1 {
329*4882a593Smuzhiyun	pinctrl-names = "default";
330*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc1>;
331*4882a593Smuzhiyun	bus-width = <4>;
332*4882a593Smuzhiyun	vmmc-supply = <&reg_wl18xx_vmmc>;
333*4882a593Smuzhiyun	no-1-8-v;
334*4882a593Smuzhiyun	non-removable;
335*4882a593Smuzhiyun	wakeup-source;
336*4882a593Smuzhiyun	keep-power-in-suspend;
337*4882a593Smuzhiyun	cap-power-off-card;
338*4882a593Smuzhiyun	max-frequency = <25000000>;
339*4882a593Smuzhiyun	#address-cells = <1>;
340*4882a593Smuzhiyun	#size-cells = <0>;
341*4882a593Smuzhiyun	status = "okay";
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun	wlcore: wlcore@2 {
344*4882a593Smuzhiyun		compatible = "ti,wl1837";
345*4882a593Smuzhiyun		reg = <2>;
346*4882a593Smuzhiyun		interrupt-parent = <&gpio6>;
347*4882a593Smuzhiyun		interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
348*4882a593Smuzhiyun		tcxo-clock-frequency = <26000000>;
349*4882a593Smuzhiyun	};
350*4882a593Smuzhiyun};
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun&usdhc3 {
353*4882a593Smuzhiyun	pinctrl-names = "default";
354*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc3>;
355*4882a593Smuzhiyun	bus-width = <8>;
356*4882a593Smuzhiyun	non-removable;
357*4882a593Smuzhiyun	keep-power-in-suspend;
358*4882a593Smuzhiyun	status = "okay";
359*4882a593Smuzhiyun};
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun&iomuxc {
362*4882a593Smuzhiyun	pinctrl_enet: enetgrp {
363*4882a593Smuzhiyun		fsl,pins = <
364*4882a593Smuzhiyun			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
365*4882a593Smuzhiyun			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
366*4882a593Smuzhiyun			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b1
367*4882a593Smuzhiyun			MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0	0x1b0b0
368*4882a593Smuzhiyun			MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1	0x1b0b0
369*4882a593Smuzhiyun			MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2	0x1b0b0
370*4882a593Smuzhiyun			MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3	0x1b0b0
371*4882a593Smuzhiyun			MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN	0x1b0b0
372*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_19__ENET_TX_ER		0x1b0b0
373*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_18__ENET_RX_CLK		0x1b0b1
374*4882a593Smuzhiyun			MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0	0x1b0b0
375*4882a593Smuzhiyun			MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1	0x1b0b0
376*4882a593Smuzhiyun			MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2	0x1b0b0
377*4882a593Smuzhiyun			MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3      0x1b0b0
378*4882a593Smuzhiyun			MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN	0x1b0b0
379*4882a593Smuzhiyun			MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER	0x1b0b0
380*4882a593Smuzhiyun			MX6QDL_PAD_KEY_COL3__ENET_CRS		0x1b0b0
381*4882a593Smuzhiyun			MX6QDL_PAD_KEY_ROW1__ENET_COL		0x1b0b0
382*4882a593Smuzhiyun		>;
383*4882a593Smuzhiyun	};
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun	pinctrl_i2c3: i2c3grp {
386*4882a593Smuzhiyun		fsl,pins = <
387*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_3__I2C3_SCL     0x4001b8b1
388*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_6__I2C3_SDA     0x4001b8b1
389*4882a593Smuzhiyun		>;
390*4882a593Smuzhiyun	};
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun	pinctrl_i2c4: i2c4grp {
393*4882a593Smuzhiyun		fsl,pins = <
394*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_7__I2C4_SCL	0x4001b8b1
395*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_8__I2C4_SDA	0x4001b8b1
396*4882a593Smuzhiyun		>;
397*4882a593Smuzhiyun	};
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun	pinctrl_ipu1_lcdif: pinctrlipu1lcdif { /* parallel port 24-bit */
400*4882a593Smuzhiyun		fsl,pins = <
401*4882a593Smuzhiyun			MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 /* VDOUT_PCLK */
402*4882a593Smuzhiyun			MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
403*4882a593Smuzhiyun			MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10 /* VDOUT_HSYNC */
404*4882a593Smuzhiyun			MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10 /* VDOUT_VSYNC */
405*4882a593Smuzhiyun			MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04	   0x10 /* VDOUT_RESET */
406*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
407*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
408*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
409*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
410*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
411*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
412*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
413*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
414*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
415*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
416*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
417*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
418*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
419*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
420*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
421*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
422*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
423*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
424*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
425*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
426*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
427*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
428*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
429*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
430*4882a593Smuzhiyun		>;
431*4882a593Smuzhiyun	};
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun	pinctrl_ipu1_lcdif_pwr: ipu1lcdifpwrgrp {
434*4882a593Smuzhiyun		fsl,pins = <
435*4882a593Smuzhiyun			MX6QDL_PAD_EIM_DA1__GPIO3_IO01		0x40013058 /* EN_LCD33V */
436*4882a593Smuzhiyun			MX6QDL_PAD_SD4_DAT5__GPIO2_IO13		0x4001b0b0 /* EN_AVDD */
437*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D31__GPIO3_IO31		0x40013058 /* ENVGH */
438*4882a593Smuzhiyun			MX6QDL_PAD_EIM_A18__GPIO2_IO20		0x40013058 /* ENVGL */
439*4882a593Smuzhiyun			MX6QDL_PAD_EIM_DA6__GPIO3_IO06		0x40013058 /* LCD_POWER */
440*4882a593Smuzhiyun			MX6QDL_PAD_KEY_COL4__GPIO4_IO14		0x40013058 /* EN_VCOM_LCD */
441*4882a593Smuzhiyun			MX6QDL_PAD_KEY_ROW4__GPIO4_IO15		0x40013058 /* LCD_L_R */
442*4882a593Smuzhiyun			MX6QDL_PAD_EIM_DA2__GPIO3_IO02		0x40013058 /* LCD_U_D */
443*4882a593Smuzhiyun		>;
444*4882a593Smuzhiyun	};
445*4882a593Smuzhiyun
446*4882a593Smuzhiyun	pinctrl_pwm3: pwm3grp {
447*4882a593Smuzhiyun		fsl,pins = <
448*4882a593Smuzhiyun			MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
449*4882a593Smuzhiyun		>;
450*4882a593Smuzhiyun	};
451*4882a593Smuzhiyun
452*4882a593Smuzhiyun	pinctrl_uart3: uart3grp {
453*4882a593Smuzhiyun		fsl,pins = <
454*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D24__UART3_TX_DATA	0x1b0b1
455*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D25__UART3_RX_DATA	0x1b0b1
456*4882a593Smuzhiyun		>;
457*4882a593Smuzhiyun	};
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun	pinctrl_usbhost: usbhostgrp {
460*4882a593Smuzhiyun		fsl,pins = <
461*4882a593Smuzhiyun			MX6QDL_PAD_EIM_A23__GPIO6_IO06		0x4001b0b0
462*4882a593Smuzhiyun		>;
463*4882a593Smuzhiyun	};
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun	pinctrl_usdhc1: usdhc1grp {
466*4882a593Smuzhiyun		fsl,pins = <
467*4882a593Smuzhiyun			MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17069
468*4882a593Smuzhiyun			MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10079
469*4882a593Smuzhiyun			MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17069
470*4882a593Smuzhiyun			MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17069
471*4882a593Smuzhiyun			MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17069
472*4882a593Smuzhiyun			MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17069
473*4882a593Smuzhiyun		>;
474*4882a593Smuzhiyun	};
475*4882a593Smuzhiyun
476*4882a593Smuzhiyun	pinctrl_usdhc3: usdhc3grp {
477*4882a593Smuzhiyun		fsl,pins = <
478*4882a593Smuzhiyun			MX6QDL_PAD_SD3_CMD__SD3_CMD	0x17059
479*4882a593Smuzhiyun			MX6QDL_PAD_SD3_CLK__SD3_CLK	0x10059
480*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT0__SD3_DATA0	0x17059
481*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT1__SD3_DATA1	0x17059
482*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT2__SD3_DATA2	0x17059
483*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT3__SD3_DATA3	0x17059
484*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT4__SD3_DATA4	0x17059
485*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT5__SD3_DATA5	0x17059
486*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT6__SD3_DATA6	0x17059
487*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT7__SD3_DATA7	0x17059
488*4882a593Smuzhiyun		>;
489*4882a593Smuzhiyun	};
490*4882a593Smuzhiyun
491*4882a593Smuzhiyun	pinctrl_wlan: wlangrp {
492*4882a593Smuzhiyun		fsl,pins = <
493*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_TD1__GPIO6_IO21	0x4001b0b0
494*4882a593Smuzhiyun		>;
495*4882a593Smuzhiyun	};
496*4882a593Smuzhiyun};
497