1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun// 3*4882a593Smuzhiyun// Copyright (C) 2019 Logic PD, Inc. 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 6*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/ { 9*4882a593Smuzhiyun chosen { 10*4882a593Smuzhiyun stdout-path = &uart1; 11*4882a593Smuzhiyun }; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun memory@10000000 { 14*4882a593Smuzhiyun device_type = "memory"; 15*4882a593Smuzhiyun reg = <0x10000000 0x80000000>; 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun reg_wl18xx_vmmc: regulator-wl18xx { 19*4882a593Smuzhiyun compatible = "regulator-fixed"; 20*4882a593Smuzhiyun regulator-name = "vwl1837"; 21*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 22*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 23*4882a593Smuzhiyun gpio = <&gpio7 0 GPIO_ACTIVE_HIGH>; 24*4882a593Smuzhiyun startup-delay-us = <70000>; 25*4882a593Smuzhiyun enable-active-high; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun}; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun&clks { 30*4882a593Smuzhiyun assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 31*4882a593Smuzhiyun <&clks IMX6QDL_CLK_LDB_DI1_SEL>; 32*4882a593Smuzhiyun assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, 33*4882a593Smuzhiyun <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 34*4882a593Smuzhiyun}; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun&gpmi { 37*4882a593Smuzhiyun pinctrl-names = "default"; 38*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_gpmi_nand>; 39*4882a593Smuzhiyun nand-on-flash-bbt; 40*4882a593Smuzhiyun status = "okay"; 41*4882a593Smuzhiyun}; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun&i2c3 { 44*4882a593Smuzhiyun clock-frequency = <100000>; 45*4882a593Smuzhiyun pinctrl-names = "default"; 46*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c3>; 47*4882a593Smuzhiyun status = "okay"; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun pfuze100: pmic@8 { 50*4882a593Smuzhiyun compatible = "fsl,pfuze100"; 51*4882a593Smuzhiyun reg = <0x08>; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun regulators { 54*4882a593Smuzhiyun sw1a_reg: sw1ab { 55*4882a593Smuzhiyun regulator-min-microvolt = <725000>; 56*4882a593Smuzhiyun regulator-max-microvolt = <1450000>; 57*4882a593Smuzhiyun regulator-name = "vddcore"; 58*4882a593Smuzhiyun regulator-boot-on; 59*4882a593Smuzhiyun regulator-always-on; 60*4882a593Smuzhiyun regulator-ramp-delay = <6250>; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun sw1c_reg: sw1c { 64*4882a593Smuzhiyun regulator-min-microvolt = <725000>; 65*4882a593Smuzhiyun regulator-max-microvolt = <1450000>; 66*4882a593Smuzhiyun regulator-name = "vddsoc"; 67*4882a593Smuzhiyun regulator-boot-on; 68*4882a593Smuzhiyun regulator-always-on; 69*4882a593Smuzhiyun regulator-ramp-delay = <6250>; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun sw2_reg: sw2 { 73*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 74*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 75*4882a593Smuzhiyun regulator-name = "gen_3v3"; 76*4882a593Smuzhiyun regulator-boot-on; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun sw3a_reg: sw3a { 80*4882a593Smuzhiyun regulator-min-microvolt = <1350000>; 81*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 82*4882a593Smuzhiyun regulator-name = "sw3a_vddr"; 83*4882a593Smuzhiyun regulator-boot-on; 84*4882a593Smuzhiyun regulator-always-on; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun sw3b_reg: sw3b { 88*4882a593Smuzhiyun regulator-min-microvolt = <1350000>; 89*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 90*4882a593Smuzhiyun regulator-name = "sw3b_vddr"; 91*4882a593Smuzhiyun regulator-boot-on; 92*4882a593Smuzhiyun regulator-always-on; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun sw4_reg: sw4 { 96*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 97*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 98*4882a593Smuzhiyun regulator-name = "gen_rgmii"; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun swbst_reg: swbst { 102*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 103*4882a593Smuzhiyun regulator-max-microvolt = <5150000>; 104*4882a593Smuzhiyun regulator-name = "gen_5v0"; 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun snvs_reg: vsnvs { 108*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 109*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 110*4882a593Smuzhiyun regulator-name = "gen_vsns"; 111*4882a593Smuzhiyun regulator-boot-on; 112*4882a593Smuzhiyun regulator-always-on; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun vref_reg: vrefddr { 116*4882a593Smuzhiyun regulator-boot-on; 117*4882a593Smuzhiyun regulator-always-on; 118*4882a593Smuzhiyun }; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun vgen1_reg: vgen1 { 121*4882a593Smuzhiyun regulator-min-microvolt = <1500000>; 122*4882a593Smuzhiyun regulator-max-microvolt = <1500000>; 123*4882a593Smuzhiyun regulator-name = "gen_1v5"; 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun vgen2_reg: vgen2 { 127*4882a593Smuzhiyun regulator-name = "vgen2"; 128*4882a593Smuzhiyun regulator-min-microvolt = <800000>; 129*4882a593Smuzhiyun regulator-max-microvolt = <1550000>; 130*4882a593Smuzhiyun }; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun vgen3_reg: vgen3 { 133*4882a593Smuzhiyun regulator-name = "gen_vadj_0"; 134*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 135*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun vgen4_reg: vgen4 { 139*4882a593Smuzhiyun regulator-name = "gen_1v8"; 140*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 141*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 142*4882a593Smuzhiyun regulator-always-on; 143*4882a593Smuzhiyun }; 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun vgen5_reg: vgen5 { 146*4882a593Smuzhiyun regulator-name = "gen_vadj_1"; 147*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 148*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 149*4882a593Smuzhiyun regulator-always-on; 150*4882a593Smuzhiyun }; 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun vgen6_reg: vgen6 { 153*4882a593Smuzhiyun regulator-name = "gen_2v5"; 154*4882a593Smuzhiyun regulator-min-microvolt = <2500000>; 155*4882a593Smuzhiyun regulator-max-microvolt = <2500000>; 156*4882a593Smuzhiyun regulator-always-on; 157*4882a593Smuzhiyun }; 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun coin_reg: coin { 160*4882a593Smuzhiyun regulator-min-microvolt = <2500000>; 161*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 162*4882a593Smuzhiyun regulator-always-on; 163*4882a593Smuzhiyun }; 164*4882a593Smuzhiyun }; 165*4882a593Smuzhiyun }; 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun temperature-sensor@49 { 168*4882a593Smuzhiyun compatible = "ti,tmp102"; 169*4882a593Smuzhiyun reg = <0x49>; 170*4882a593Smuzhiyun interrupt-parent = <&gpio6>; 171*4882a593Smuzhiyun interrupts = <15 IRQ_TYPE_LEVEL_LOW>; 172*4882a593Smuzhiyun #thermal-sensor-cells = <1>; 173*4882a593Smuzhiyun }; 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun temperature-sensor@4a { 176*4882a593Smuzhiyun compatible = "ti,tmp102"; 177*4882a593Smuzhiyun reg = <0x4a>; 178*4882a593Smuzhiyun pinctrl-names = "default"; 179*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_tempsense>; 180*4882a593Smuzhiyun interrupt-parent = <&gpio6>; 181*4882a593Smuzhiyun interrupts = <15 IRQ_TYPE_LEVEL_LOW>; 182*4882a593Smuzhiyun #thermal-sensor-cells = <1>; 183*4882a593Smuzhiyun }; 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun eeprom@51 { 186*4882a593Smuzhiyun compatible = "atmel,24c64"; 187*4882a593Smuzhiyun pagesize = <32>; 188*4882a593Smuzhiyun read-only; /* Manufacturing EEPROM programmed at factory */ 189*4882a593Smuzhiyun reg = <0x51>; 190*4882a593Smuzhiyun }; 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun eeprom@52 { 193*4882a593Smuzhiyun compatible = "atmel,24c64"; 194*4882a593Smuzhiyun pagesize = <32>; 195*4882a593Smuzhiyun reg = <0x52>; 196*4882a593Smuzhiyun }; 197*4882a593Smuzhiyun}; 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun/* Reroute power feeding the CPU to come from the external PMIC */ 200*4882a593Smuzhiyun®_arm 201*4882a593Smuzhiyun{ 202*4882a593Smuzhiyun vin-supply = <&sw1a_reg>; 203*4882a593Smuzhiyun}; 204*4882a593Smuzhiyun 205*4882a593Smuzhiyun®_soc 206*4882a593Smuzhiyun{ 207*4882a593Smuzhiyun vin-supply = <&sw1c_reg>; 208*4882a593Smuzhiyun}; 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun&snvs_poweroff { 211*4882a593Smuzhiyun status = "okay"; 212*4882a593Smuzhiyun}; 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun&iomuxc { 215*4882a593Smuzhiyun pinctrl-names = "default"; 216*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_hog>; 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun pinctrl_gpmi_nand: gpmi-nandgrp { 219*4882a593Smuzhiyun fsl,pins = < 220*4882a593Smuzhiyun MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1 221*4882a593Smuzhiyun MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1 222*4882a593Smuzhiyun MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1 223*4882a593Smuzhiyun MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000 224*4882a593Smuzhiyun MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1 225*4882a593Smuzhiyun MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1 226*4882a593Smuzhiyun MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1 227*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1 228*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1 229*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1 230*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1 231*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1 232*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1 233*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1 234*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1 235*4882a593Smuzhiyun >; 236*4882a593Smuzhiyun }; 237*4882a593Smuzhiyun 238*4882a593Smuzhiyun pinctrl_hog: hoggrp { 239*4882a593Smuzhiyun fsl,pins = < /* Enable ARM Debugger */ 240*4882a593Smuzhiyun MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x1b0b0 241*4882a593Smuzhiyun MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x1b0b0 242*4882a593Smuzhiyun MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x1b0b0 243*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x1b0b0 244*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0x1b0b0 245*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0x1b0b0 246*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0x1b0b0 247*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0x1b0b0 248*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0x1b0b0 249*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0x1b0b0 250*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x1b0b0 251*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0x1b0b0 252*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0x1b0b0 253*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0x1b0b0 254*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0x1b0b0 255*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0x1b0b0 256*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0x1b0b0 257*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0x1b0b0 258*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0x1b0b0 259*4882a593Smuzhiyun MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 260*4882a593Smuzhiyun >; 261*4882a593Smuzhiyun }; 262*4882a593Smuzhiyun 263*4882a593Smuzhiyun pinctrl_i2c3: i2c3grp { 264*4882a593Smuzhiyun fsl,pins = < 265*4882a593Smuzhiyun MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 266*4882a593Smuzhiyun MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 267*4882a593Smuzhiyun >; 268*4882a593Smuzhiyun }; 269*4882a593Smuzhiyun 270*4882a593Smuzhiyun pinctrl_tempsense: tempsensegrp { 271*4882a593Smuzhiyun fsl,pins = < 272*4882a593Smuzhiyun MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 273*4882a593Smuzhiyun >; 274*4882a593Smuzhiyun }; 275*4882a593Smuzhiyun 276*4882a593Smuzhiyun pinctrl_uart1: uart1grp { 277*4882a593Smuzhiyun fsl,pins = < 278*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 279*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 280*4882a593Smuzhiyun >; 281*4882a593Smuzhiyun }; 282*4882a593Smuzhiyun 283*4882a593Smuzhiyun pinctrl_uart2: uart2grp { 284*4882a593Smuzhiyun fsl,pins = < 285*4882a593Smuzhiyun MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x13059 /* BT_EN */ 286*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 287*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 288*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 289*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 290*4882a593Smuzhiyun >; 291*4882a593Smuzhiyun }; 292*4882a593Smuzhiyun 293*4882a593Smuzhiyun pinctrl_usdhc1: usdhc1grp { 294*4882a593Smuzhiyun fsl,pins = < 295*4882a593Smuzhiyun MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170B9 296*4882a593Smuzhiyun MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100B9 297*4882a593Smuzhiyun MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170B9 298*4882a593Smuzhiyun MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170B9 299*4882a593Smuzhiyun MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170B9 300*4882a593Smuzhiyun MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170B9 301*4882a593Smuzhiyun >; 302*4882a593Smuzhiyun }; 303*4882a593Smuzhiyun 304*4882a593Smuzhiyun pinctrl_usdhc3: usdhc3grp { 305*4882a593Smuzhiyun fsl,pins = < 306*4882a593Smuzhiyun MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17049 307*4882a593Smuzhiyun MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10049 308*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17049 309*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17049 310*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17049 311*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17049 312*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x130b0 /* WL_IRQ */ 313*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* WLAN_EN */ 314*4882a593Smuzhiyun >; 315*4882a593Smuzhiyun }; 316*4882a593Smuzhiyun}; 317*4882a593Smuzhiyun 318*4882a593Smuzhiyun&snvs_poweroff { 319*4882a593Smuzhiyun status = "okay"; 320*4882a593Smuzhiyun}; 321*4882a593Smuzhiyun 322*4882a593Smuzhiyun&uart1 { 323*4882a593Smuzhiyun pinctrl-names = "default"; 324*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart1>; 325*4882a593Smuzhiyun status = "okay"; 326*4882a593Smuzhiyun}; 327*4882a593Smuzhiyun 328*4882a593Smuzhiyun&uart2 { 329*4882a593Smuzhiyun pinctrl-names = "default"; 330*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart2>; 331*4882a593Smuzhiyun uart-has-rtscts; 332*4882a593Smuzhiyun status = "okay"; 333*4882a593Smuzhiyun 334*4882a593Smuzhiyun bluetooth { 335*4882a593Smuzhiyun compatible = "ti,wl1837-st"; 336*4882a593Smuzhiyun enable-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; 337*4882a593Smuzhiyun }; 338*4882a593Smuzhiyun}; 339*4882a593Smuzhiyun 340*4882a593Smuzhiyun&usdhc1 { 341*4882a593Smuzhiyun pinctrl-names = "default", "state_100mhz", "state_200mhz"; 342*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc1>; 343*4882a593Smuzhiyun non-removable; 344*4882a593Smuzhiyun keep-power-in-suspend; 345*4882a593Smuzhiyun wakeup-source; 346*4882a593Smuzhiyun vmmc-supply = <&sw2_reg>; 347*4882a593Smuzhiyun status = "okay"; 348*4882a593Smuzhiyun}; 349*4882a593Smuzhiyun 350*4882a593Smuzhiyun&usdhc3 { 351*4882a593Smuzhiyun pinctrl-names = "default"; 352*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc3>; 353*4882a593Smuzhiyun non-removable; 354*4882a593Smuzhiyun cap-power-off-card; 355*4882a593Smuzhiyun keep-power-in-suspend; 356*4882a593Smuzhiyun wakeup-source; 357*4882a593Smuzhiyun vmmc-supply = <®_wl18xx_vmmc>; 358*4882a593Smuzhiyun #address-cells = <1>; 359*4882a593Smuzhiyun #size-cells = <0>; 360*4882a593Smuzhiyun status = "okay"; 361*4882a593Smuzhiyun 362*4882a593Smuzhiyun wlcore: wlcore@2 { 363*4882a593Smuzhiyun compatible = "ti,wl1837"; 364*4882a593Smuzhiyun reg = <2>; 365*4882a593Smuzhiyun interrupt-parent = <&gpio7>; 366*4882a593Smuzhiyun interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; 367*4882a593Smuzhiyun tcxo-clock-frequency = <26000000>; 368*4882a593Smuzhiyun }; 369*4882a593Smuzhiyun}; 370