xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun//
3*4882a593Smuzhiyun// Copyright (C) 2019 Logic PD, Inc.
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun/ {
6*4882a593Smuzhiyun	keyboard {
7*4882a593Smuzhiyun		compatible = "gpio-keys";
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun		btn0 {
10*4882a593Smuzhiyun			gpios = <&pcf8575 0 GPIO_ACTIVE_LOW>;
11*4882a593Smuzhiyun			label = "btn0";
12*4882a593Smuzhiyun			linux,code = <KEY_WAKEUP>;
13*4882a593Smuzhiyun			debounce-interval = <10>;
14*4882a593Smuzhiyun			wakeup-source;
15*4882a593Smuzhiyun		};
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun		btn1 {
18*4882a593Smuzhiyun			gpios = <&pcf8575 1 GPIO_ACTIVE_LOW>;
19*4882a593Smuzhiyun			label = "btn1";
20*4882a593Smuzhiyun			linux,code = <KEY_WAKEUP>;
21*4882a593Smuzhiyun			debounce-interval = <10>;
22*4882a593Smuzhiyun			wakeup-source;
23*4882a593Smuzhiyun		};
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun		btn2 {
26*4882a593Smuzhiyun			gpios = <&pcf8575 2 GPIO_ACTIVE_LOW>;
27*4882a593Smuzhiyun			label = "btn2";
28*4882a593Smuzhiyun			linux,code = <KEY_WAKEUP>;
29*4882a593Smuzhiyun			debounce-interval = <10>;
30*4882a593Smuzhiyun			wakeup-source;
31*4882a593Smuzhiyun		};
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun		btn3 {
34*4882a593Smuzhiyun			gpios = <&pcf8575 3 GPIO_ACTIVE_LOW>;
35*4882a593Smuzhiyun			label = "btn3";
36*4882a593Smuzhiyun			linux,code = <KEY_WAKEUP>;
37*4882a593Smuzhiyun			debounce-interval = <10>;
38*4882a593Smuzhiyun			wakeup-source;
39*4882a593Smuzhiyun		};
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun	};
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun	leds {
44*4882a593Smuzhiyun		compatible = "gpio-leds";
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun		gen-led0 {
47*4882a593Smuzhiyun			label = "led0";
48*4882a593Smuzhiyun			pinctrl-names = "default";
49*4882a593Smuzhiyun			pinctrl-0 = <&pinctrl_led0>;
50*4882a593Smuzhiyun			gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
51*4882a593Smuzhiyun			linux,default-trigger = "cpu0";
52*4882a593Smuzhiyun		};
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun		gen-led1 {
55*4882a593Smuzhiyun			label = "led1";
56*4882a593Smuzhiyun			gpios = <&pcf8575 8 GPIO_ACTIVE_HIGH>;
57*4882a593Smuzhiyun		};
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun		gen-led2 {
60*4882a593Smuzhiyun			label = "led2";
61*4882a593Smuzhiyun			gpios = <&pcf8575 9 GPIO_ACTIVE_HIGH>;
62*4882a593Smuzhiyun			linux,default-trigger = "heartbeat";
63*4882a593Smuzhiyun		};
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun		gen-led3 {
66*4882a593Smuzhiyun			label = "led3";
67*4882a593Smuzhiyun			gpios = <&pcf8575 10 GPIO_ACTIVE_HIGH>;
68*4882a593Smuzhiyun			linux,default-trigger = "default-on";
69*4882a593Smuzhiyun		};
70*4882a593Smuzhiyun	};
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun	reg_usb_otg_vbus: regulator-otg-vbus {
73*4882a593Smuzhiyun		pinctrl-names = "default";
74*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_reg_usb_otg>;
75*4882a593Smuzhiyun		compatible = "regulator-fixed";
76*4882a593Smuzhiyun		regulator-name = "usb_otg_vbus";
77*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
78*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
79*4882a593Smuzhiyun		gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
80*4882a593Smuzhiyun		enable-active-high;
81*4882a593Smuzhiyun	};
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun	reg_usb_h1_vbus: regulator-usb-h1-vbus {
84*4882a593Smuzhiyun		pinctrl-names = "default";
85*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_reg_usb_h1_vbus>;
86*4882a593Smuzhiyun		compatible = "regulator-fixed";
87*4882a593Smuzhiyun		regulator-name = "usb_h1_vbus";
88*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
89*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
90*4882a593Smuzhiyun		gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
91*4882a593Smuzhiyun		startup-delay-us = <70000>;
92*4882a593Smuzhiyun		enable-active-high;
93*4882a593Smuzhiyun	};
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun	reg_3v3: regulator-3v3 {
96*4882a593Smuzhiyun		pinctrl-names = "default";
97*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_reg_3v3>;
98*4882a593Smuzhiyun		compatible = "regulator-fixed";
99*4882a593Smuzhiyun		regulator-name = "reg_3v3";
100*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
101*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
102*4882a593Smuzhiyun		gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
103*4882a593Smuzhiyun		startup-delay-us = <70000>;
104*4882a593Smuzhiyun		enable-active-high;
105*4882a593Smuzhiyun		regulator-always-on;
106*4882a593Smuzhiyun	};
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun	reg_enet: regulator-ethernet {
109*4882a593Smuzhiyun		pinctrl-names = "default";
110*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_reg_enet>;
111*4882a593Smuzhiyun		compatible = "regulator-fixed";
112*4882a593Smuzhiyun		regulator-name = "ethernet-supply";
113*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
114*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
115*4882a593Smuzhiyun		gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
116*4882a593Smuzhiyun		startup-delay-us = <70000>;
117*4882a593Smuzhiyun		enable-active-high;
118*4882a593Smuzhiyun		vin-supply = <&sw4_reg>;
119*4882a593Smuzhiyun	};
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun	reg_audio: regulator-audio {
122*4882a593Smuzhiyun		pinctrl-names = "default";
123*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_reg_audio>;
124*4882a593Smuzhiyun		compatible = "regulator-fixed";
125*4882a593Smuzhiyun		regulator-name = "3v3_aud";
126*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
127*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
128*4882a593Smuzhiyun		gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
129*4882a593Smuzhiyun		enable-active-high;
130*4882a593Smuzhiyun		vin-supply = <&reg_3v3>;
131*4882a593Smuzhiyun	};
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun	reg_hdmi: regulator-hdmi {
134*4882a593Smuzhiyun		pinctrl-names = "default";
135*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_reg_hdmi>;
136*4882a593Smuzhiyun		compatible = "regulator-fixed";
137*4882a593Smuzhiyun		regulator-name = "hdmi-supply";
138*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
139*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
140*4882a593Smuzhiyun		gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
141*4882a593Smuzhiyun		enable-active-high;
142*4882a593Smuzhiyun		vin-supply = <&reg_3v3>;
143*4882a593Smuzhiyun	};
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun	reg_uart3: regulator-uart3 {
146*4882a593Smuzhiyun		pinctrl-names = "default";
147*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_reg_uart3>;
148*4882a593Smuzhiyun		compatible = "regulator-fixed";
149*4882a593Smuzhiyun		regulator-name = "uart3-supply";
150*4882a593Smuzhiyun		gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
151*4882a593Smuzhiyun		enable-active-high;
152*4882a593Smuzhiyun		regulator-always-on;
153*4882a593Smuzhiyun		vin-supply = <&reg_3v3>;
154*4882a593Smuzhiyun	};
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun	reg_1v8: regulator-1v8 {
157*4882a593Smuzhiyun		pinctrl-names = "default";
158*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_reg_1v8>;
159*4882a593Smuzhiyun		compatible = "regulator-fixed";
160*4882a593Smuzhiyun		regulator-name = "1v8-supply";
161*4882a593Smuzhiyun		gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
162*4882a593Smuzhiyun		enable-active-high;
163*4882a593Smuzhiyun		regulator-always-on;
164*4882a593Smuzhiyun		vin-supply = <&reg_3v3>;
165*4882a593Smuzhiyun	};
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun	reg_pcie: regulator-pcie {
168*4882a593Smuzhiyun		compatible = "regulator-fixed";
169*4882a593Smuzhiyun		pinctrl-names = "default";
170*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_reg_pcie>;
171*4882a593Smuzhiyun		regulator-name = "mpcie_3v3";
172*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
173*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
174*4882a593Smuzhiyun		gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
175*4882a593Smuzhiyun		enable-active-high;
176*4882a593Smuzhiyun	};
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun	reg_mipi: regulator-mipi {
179*4882a593Smuzhiyun		compatible = "regulator-fixed";
180*4882a593Smuzhiyun		pinctrl-names = "default";
181*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_reg_mipi>;
182*4882a593Smuzhiyun		regulator-name = "mipi_pwr_en";
183*4882a593Smuzhiyun		regulator-min-microvolt = <2800000>;
184*4882a593Smuzhiyun		regulator-max-microvolt = <2800000>;
185*4882a593Smuzhiyun		gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>;
186*4882a593Smuzhiyun		enable-active-high;
187*4882a593Smuzhiyun	};
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun	sound {
190*4882a593Smuzhiyun		compatible = "fsl,imx-audio-wm8962";
191*4882a593Smuzhiyun		model = "wm8962-audio";
192*4882a593Smuzhiyun		ssi-controller = <&ssi2>;
193*4882a593Smuzhiyun		audio-codec = <&wm8962>;
194*4882a593Smuzhiyun		audio-routing =
195*4882a593Smuzhiyun			"Headphone Jack", "HPOUTL",
196*4882a593Smuzhiyun			"Headphone Jack", "HPOUTR",
197*4882a593Smuzhiyun			"Ext Spk", "SPKOUTL",
198*4882a593Smuzhiyun			"Ext Spk", "SPKOUTR",
199*4882a593Smuzhiyun			"AMIC", "MICBIAS",
200*4882a593Smuzhiyun			"IN3R", "AMIC";
201*4882a593Smuzhiyun		mux-int-port = <2>;
202*4882a593Smuzhiyun		mux-ext-port = <4>;
203*4882a593Smuzhiyun	};
204*4882a593Smuzhiyun};
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun&audmux {
207*4882a593Smuzhiyun	pinctrl-names = "default";
208*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_audmux>;
209*4882a593Smuzhiyun	status = "okay";
210*4882a593Smuzhiyun};
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun&ecspi1 {
213*4882a593Smuzhiyun	pinctrl-names = "default";
214*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_ecspi1>;
215*4882a593Smuzhiyun	cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
216*4882a593Smuzhiyun	status = "disabled";
217*4882a593Smuzhiyun};
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun&fec {
220*4882a593Smuzhiyun	pinctrl-names = "default";
221*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_enet>;
222*4882a593Smuzhiyun	phy-mode = "rgmii-id";
223*4882a593Smuzhiyun	phy-reset-duration = <10>;
224*4882a593Smuzhiyun	phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
225*4882a593Smuzhiyun	phy-supply = <&reg_enet>;
226*4882a593Smuzhiyun	interrupt-parent = <&gpio1>;
227*4882a593Smuzhiyun	interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
228*4882a593Smuzhiyun	status = "okay";
229*4882a593Smuzhiyun};
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun&i2c1 {
232*4882a593Smuzhiyun	pinctrl-names = "default";
233*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c1>;
234*4882a593Smuzhiyun	clock-frequency = <400000>;
235*4882a593Smuzhiyun	status = "okay";
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun	wm8962: audio-codec@1a {
238*4882a593Smuzhiyun		compatible = "wlf,wm8962";
239*4882a593Smuzhiyun		reg = <0x1a>;
240*4882a593Smuzhiyun		clocks = <&clks IMX6QDL_CLK_CKO>;
241*4882a593Smuzhiyun		clock-names = "xclk";
242*4882a593Smuzhiyun		DCVDD-supply = <&reg_audio>;
243*4882a593Smuzhiyun		DBVDD-supply = <&reg_audio>;
244*4882a593Smuzhiyun		AVDD-supply = <&reg_audio>;
245*4882a593Smuzhiyun		CPVDD-supply = <&reg_audio>;
246*4882a593Smuzhiyun		MICVDD-supply = <&reg_audio>;
247*4882a593Smuzhiyun		PLLVDD-supply = <&reg_audio>;
248*4882a593Smuzhiyun		SPKVDD1-supply = <&reg_audio>;
249*4882a593Smuzhiyun		SPKVDD2-supply = <&reg_audio>;
250*4882a593Smuzhiyun		gpio-cfg = <
251*4882a593Smuzhiyun			0x0000 /* 0:Default */
252*4882a593Smuzhiyun			0x0000 /* 1:Default */
253*4882a593Smuzhiyun			0x0000 /* 2:FN_DMICCLK */
254*4882a593Smuzhiyun			0x0000 /* 3:Default */
255*4882a593Smuzhiyun			0x0000 /* 4:FN_DMICCDAT */
256*4882a593Smuzhiyun			0x0000 /* 5:Default */
257*4882a593Smuzhiyun		>;
258*4882a593Smuzhiyun	};
259*4882a593Smuzhiyun};
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun&i2c3 {
262*4882a593Smuzhiyun	ov5640: camera@10 {
263*4882a593Smuzhiyun		compatible = "ovti,ov5640";
264*4882a593Smuzhiyun		pinctrl-names = "default";
265*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_ov5640>;
266*4882a593Smuzhiyun		reg = <0x10>;
267*4882a593Smuzhiyun		clocks = <&clks IMX6QDL_CLK_CKO>;
268*4882a593Smuzhiyun		clock-names = "xclk";
269*4882a593Smuzhiyun		DOVDD-supply = <&reg_mipi>;
270*4882a593Smuzhiyun		AVDD-supply = <&reg_mipi>;
271*4882a593Smuzhiyun		DVDD-supply = <&reg_mipi>;
272*4882a593Smuzhiyun		reset-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
273*4882a593Smuzhiyun		powerdown-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>;
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun		port {
276*4882a593Smuzhiyun			ov5640_to_mipi_csi2: endpoint {
277*4882a593Smuzhiyun				remote-endpoint = <&mipi_csi2_in>;
278*4882a593Smuzhiyun				clock-lanes = <0>;
279*4882a593Smuzhiyun				data-lanes = <1 2>;
280*4882a593Smuzhiyun			};
281*4882a593Smuzhiyun		};
282*4882a593Smuzhiyun	};
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun	pcf8575: gpio@20 {
285*4882a593Smuzhiyun		pinctrl-names = "default";
286*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_pcf8574>;
287*4882a593Smuzhiyun		compatible = "nxp,pcf8575";
288*4882a593Smuzhiyun		reg = <0x20>;
289*4882a593Smuzhiyun		interrupt-parent = <&gpio6>;
290*4882a593Smuzhiyun		interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
291*4882a593Smuzhiyun		gpio-controller;
292*4882a593Smuzhiyun		#gpio-cells = <2>;
293*4882a593Smuzhiyun		interrupt-controller;
294*4882a593Smuzhiyun		#interrupt-cells = <2>;
295*4882a593Smuzhiyun		lines-initial-states = <0x0710>;
296*4882a593Smuzhiyun		wakeup-source;
297*4882a593Smuzhiyun	};
298*4882a593Smuzhiyun};
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun&ipu1_csi1_from_mipi_vc1 {
301*4882a593Smuzhiyun	clock-lanes = <0>;
302*4882a593Smuzhiyun	data-lanes = <1 2>;
303*4882a593Smuzhiyun};
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun&mipi_csi {
306*4882a593Smuzhiyun	status = "okay";
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun	port@0 {
309*4882a593Smuzhiyun		reg = <0>;
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun		mipi_csi2_in: endpoint {
312*4882a593Smuzhiyun			remote-endpoint = <&ov5640_to_mipi_csi2>;
313*4882a593Smuzhiyun			clock-lanes = <0>;
314*4882a593Smuzhiyun			data-lanes = <1 2>;
315*4882a593Smuzhiyun		};
316*4882a593Smuzhiyun	};
317*4882a593Smuzhiyun};
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun&pcie {
320*4882a593Smuzhiyun	pinctrl-names = "default";
321*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pcie>;
322*4882a593Smuzhiyun	reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
323*4882a593Smuzhiyun	vpcie-supply = <&reg_pcie>;
324*4882a593Smuzhiyun	status = "okay";
325*4882a593Smuzhiyun};
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun&pwm3 {
328*4882a593Smuzhiyun	pinctrl-names = "default";
329*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pwm3>;
330*4882a593Smuzhiyun};
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun&snvs_pwrkey {
333*4882a593Smuzhiyun	status = "okay";
334*4882a593Smuzhiyun};
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun&ssi2 {
337*4882a593Smuzhiyun	status = "okay";
338*4882a593Smuzhiyun};
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun&uart3 {
341*4882a593Smuzhiyun	pinctrl-names = "default";
342*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart3>;
343*4882a593Smuzhiyun	status = "okay";
344*4882a593Smuzhiyun};
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun&usbh1 {
347*4882a593Smuzhiyun	vbus-supply = <&reg_usb_h1_vbus>;
348*4882a593Smuzhiyun	status = "okay";
349*4882a593Smuzhiyun};
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun&usbotg {
352*4882a593Smuzhiyun	vbus-supply = <&reg_usb_otg_vbus>;
353*4882a593Smuzhiyun	pinctrl-names = "default";
354*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usbotg>;
355*4882a593Smuzhiyun	disable-over-current;
356*4882a593Smuzhiyun	dr_mode = "otg";
357*4882a593Smuzhiyun	status = "okay";
358*4882a593Smuzhiyun};
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun&usdhc2 {
361*4882a593Smuzhiyun	pinctrl-names = "default";
362*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc2>;
363*4882a593Smuzhiyun	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
364*4882a593Smuzhiyun	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
365*4882a593Smuzhiyun	vmmc-supply = <&reg_3v3>;
366*4882a593Smuzhiyun	no-1-8-v;
367*4882a593Smuzhiyun	keep-power-in-suspend;
368*4882a593Smuzhiyun	cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
369*4882a593Smuzhiyun	status = "okay";
370*4882a593Smuzhiyun};
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun&iomuxc {
373*4882a593Smuzhiyun	pinctrl_audmux: audmuxgrp {
374*4882a593Smuzhiyun		fsl,pins = <
375*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT20__AUD4_TXC  0x130b0
376*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT21__AUD4_TXD  0x110b0
377*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
378*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT23__AUD4_RXD  0x130b0
379*4882a593Smuzhiyun		>;
380*4882a593Smuzhiyun	};
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun	pinctrl_ecspi1: ecspi1grp {
383*4882a593Smuzhiyun		fsl,pins = <
384*4882a593Smuzhiyun			MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK	0x100b1
385*4882a593Smuzhiyun			MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI	0x100b1
386*4882a593Smuzhiyun			MX6QDL_PAD_KEY_COL1__ECSPI1_MISO	0x100b1
387*4882a593Smuzhiyun			MX6QDL_PAD_KEY_ROW1__GPIO4_IO09		0x1b0b0
388*4882a593Smuzhiyun		>;
389*4882a593Smuzhiyun	};
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun	pinctrl_enet: enetgrp {
392*4882a593Smuzhiyun		fsl,pins = <
393*4882a593Smuzhiyun			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b8b0
394*4882a593Smuzhiyun			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
395*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
396*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
397*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
398*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
399*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
400*4882a593Smuzhiyun			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x100b0
401*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
402*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
403*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
404*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x13030
405*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x13030
406*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
407*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
408*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x13030
409*4882a593Smuzhiyun			MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25	0x1b0b0	/* ENET_INT */
410*4882a593Smuzhiyun			MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24	0x1b0b0	/* ETHR_nRST */
411*4882a593Smuzhiyun		>;
412*4882a593Smuzhiyun	};
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun	pinctrl_i2c1: i2c1grp {
415*4882a593Smuzhiyun		fsl,pins = <
416*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D21__I2C1_SCL	0x4001b8b1
417*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D28__I2C1_SDA	0x4001b8b1
418*4882a593Smuzhiyun		>;
419*4882a593Smuzhiyun	};
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun	pinctrl_led0: led0grp {
422*4882a593Smuzhiyun	    fsl,pins = <
423*4882a593Smuzhiyun		MX6QDL_PAD_ENET_TXD0__GPIO1_IO30	0x1b0b0
424*4882a593Smuzhiyun	    >;
425*4882a593Smuzhiyun	};
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun	pinctrl_ov5640: ov5640grp {
428*4882a593Smuzhiyun		fsl,pins = <
429*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D26__GPIO3_IO26	0x1b0b1
430*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D27__GPIO3_IO27	0x1b0b1
431*4882a593Smuzhiyun		>;
432*4882a593Smuzhiyun	};
433*4882a593Smuzhiyun
434*4882a593Smuzhiyun	pinctrl_pcf8574: pcf8575grp {
435*4882a593Smuzhiyun		fsl,pins = <
436*4882a593Smuzhiyun			MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0
437*4882a593Smuzhiyun		>;
438*4882a593Smuzhiyun	};
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun	pinctrl_pcie: pciegrp {
441*4882a593Smuzhiyun		fsl,pins = <
442*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0
443*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
444*4882a593Smuzhiyun		>;
445*4882a593Smuzhiyun	};
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun	pinctrl_pwm3: pwm3grp {
448*4882a593Smuzhiyun	    fsl,pins = <
449*4882a593Smuzhiyun		MX6QDL_PAD_SD4_DAT1__PWM3_OUT		0x1b0b1
450*4882a593Smuzhiyun	    >;
451*4882a593Smuzhiyun	};
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun	pinctrl_reg_1v8: reg1v8grp {
454*4882a593Smuzhiyun	    fsl,pins = <
455*4882a593Smuzhiyun		MX6QDL_PAD_EIM_D30__GPIO3_IO30		0x1b0b0
456*4882a593Smuzhiyun	    >;
457*4882a593Smuzhiyun	};
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun	pinctrl_reg_3v3: reg3v3grp {
460*4882a593Smuzhiyun	    fsl,pins = <
461*4882a593Smuzhiyun		MX6QDL_PAD_ENET_RXD1__GPIO1_IO26	0x1b0b0
462*4882a593Smuzhiyun	    >;
463*4882a593Smuzhiyun	};
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun	pinctrl_reg_audio: reg-audiogrp {
466*4882a593Smuzhiyun		fsl,pins = <
467*4882a593Smuzhiyun			MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
468*4882a593Smuzhiyun		>;
469*4882a593Smuzhiyun	};
470*4882a593Smuzhiyun
471*4882a593Smuzhiyun	pinctrl_reg_enet: reg-enetgrp {
472*4882a593Smuzhiyun		fsl,pins = <
473*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D31__GPIO3_IO31	0x1b0b0
474*4882a593Smuzhiyun		>;
475*4882a593Smuzhiyun	};
476*4882a593Smuzhiyun
477*4882a593Smuzhiyun	pinctrl_reg_hdmi: reg-hdmigrp {
478*4882a593Smuzhiyun		fsl,pins = <
479*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D20__GPIO3_IO20	0x1b0b0
480*4882a593Smuzhiyun		>;
481*4882a593Smuzhiyun	};
482*4882a593Smuzhiyun
483*4882a593Smuzhiyun	pinctrl_reg_mipi: reg-mipigrp {
484*4882a593Smuzhiyun		fsl,pins = <MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b1>;
485*4882a593Smuzhiyun	};
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun	pinctrl_reg_pcie: reg-pciegrp {
488*4882a593Smuzhiyun		fsl,pins = <
489*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_2__GPIO1_IO02	0x1b0b0
490*4882a593Smuzhiyun			>;
491*4882a593Smuzhiyun	};
492*4882a593Smuzhiyun
493*4882a593Smuzhiyun	pinctrl_reg_uart3: reguart3grp {
494*4882a593Smuzhiyun	    fsl,pins = <
495*4882a593Smuzhiyun		MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28	0x1b0b0
496*4882a593Smuzhiyun	    >;
497*4882a593Smuzhiyun	};
498*4882a593Smuzhiyun
499*4882a593Smuzhiyun	pinctrl_reg_usb_h1_vbus: usbh1grp {
500*4882a593Smuzhiyun		fsl,pins = <
501*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_17__GPIO7_IO12		0x1b0b0
502*4882a593Smuzhiyun		>;
503*4882a593Smuzhiyun	};
504*4882a593Smuzhiyun
505*4882a593Smuzhiyun	pinctrl_reg_usb_otg: reg-usb-otggrp {
506*4882a593Smuzhiyun		fsl,pins = <
507*4882a593Smuzhiyun			MX6QDL_PAD_KEY_ROW4__GPIO4_IO15		0x1b0b0
508*4882a593Smuzhiyun		>;
509*4882a593Smuzhiyun	};
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun	pinctrl_uart3: uart3grp {
512*4882a593Smuzhiyun		fsl,pins = <
513*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D23__UART3_CTS_B		0x1b0b1
514*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D24__UART3_TX_DATA	0x1b0b1
515*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D25__UART3_RX_DATA	0x1b0b1
516*4882a593Smuzhiyun			MX6QDL_PAD_EIM_EB3__UART3_RTS_B		0x1b0b1
517*4882a593Smuzhiyun		>;
518*4882a593Smuzhiyun	};
519*4882a593Smuzhiyun
520*4882a593Smuzhiyun	pinctrl_usbotg: usbotggrp {
521*4882a593Smuzhiyun		fsl,pins = <
522*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_1__USB_OTG_ID	0xd17059
523*4882a593Smuzhiyun		>;
524*4882a593Smuzhiyun	};
525*4882a593Smuzhiyun
526*4882a593Smuzhiyun	pinctrl_usdhc2: usdhc2grp {
527*4882a593Smuzhiyun		fsl,pins = <
528*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_4__GPIO1_IO04		0x1b0b0	/* CD */
529*4882a593Smuzhiyun			MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17069
530*4882a593Smuzhiyun			MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10069
531*4882a593Smuzhiyun			MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17069
532*4882a593Smuzhiyun			MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17069
533*4882a593Smuzhiyun			MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17069
534*4882a593Smuzhiyun			MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17069
535*4882a593Smuzhiyun		>;
536*4882a593Smuzhiyun	};
537*4882a593Smuzhiyun
538*4882a593Smuzhiyun	pinctrl_usdhc2_100mhz: h100-usdhc2-100mhz {
539*4882a593Smuzhiyun		fsl,pins = <
540*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_4__GPIO1_IO04		0x1b0b0	/* CD */
541*4882a593Smuzhiyun			MX6QDL_PAD_SD2_CMD__SD2_CMD		0x170b9
542*4882a593Smuzhiyun			MX6QDL_PAD_SD2_CLK__SD2_CLK		0x100b9
543*4882a593Smuzhiyun			MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x170b9
544*4882a593Smuzhiyun			MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x170b9
545*4882a593Smuzhiyun			MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x170b9
546*4882a593Smuzhiyun			MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x170b9
547*4882a593Smuzhiyun		>;
548*4882a593Smuzhiyun	};
549*4882a593Smuzhiyun
550*4882a593Smuzhiyun	pinctrl_usdhc2_200mhz: h100-usdhc2-200mhz {
551*4882a593Smuzhiyun		fsl,pins = <
552*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_4__GPIO1_IO04		0x1b0b0	/* CD */
553*4882a593Smuzhiyun			MX6QDL_PAD_SD2_CMD__SD2_CMD		0x170f9
554*4882a593Smuzhiyun			MX6QDL_PAD_SD2_CLK__SD2_CLK		0x100f9
555*4882a593Smuzhiyun			MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x170f9
556*4882a593Smuzhiyun			MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x170f9
557*4882a593Smuzhiyun			MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x170f9
558*4882a593Smuzhiyun			MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x170f9
559*4882a593Smuzhiyun		>;
560*4882a593Smuzhiyun	};
561*4882a593Smuzhiyun
562*4882a593Smuzhiyun};
563