xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/imx53-tx53.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * Copyright 2012-2017 <LW@KARO-electronics.de>
3*4882a593Smuzhiyun * based on imx53-qsb.dts
4*4882a593Smuzhiyun *   Copyright 2011 Freescale Semiconductor, Inc.
5*4882a593Smuzhiyun *   Copyright 2011 Linaro Ltd.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * This file is dual-licensed: you can use it either under the terms
8*4882a593Smuzhiyun * of the GPL or the X11 license, at your option. Note that this dual
9*4882a593Smuzhiyun * licensing only applies to this file, and not this project as a
10*4882a593Smuzhiyun * whole.
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun *  a) This file is free software; you can redistribute it and/or
13*4882a593Smuzhiyun *     modify it under the terms of the GNU General Public License
14*4882a593Smuzhiyun *     version 2 as published by the Free Software Foundation.
15*4882a593Smuzhiyun *
16*4882a593Smuzhiyun *     This file is distributed in the hope that it will be useful,
17*4882a593Smuzhiyun *     but WITHOUT ANY WARRANTY; without even the implied warranty of
18*4882a593Smuzhiyun *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19*4882a593Smuzhiyun *     GNU General Public License for more details.
20*4882a593Smuzhiyun *
21*4882a593Smuzhiyun * Or, alternatively,
22*4882a593Smuzhiyun *
23*4882a593Smuzhiyun *  b) Permission is hereby granted, free of charge, to any person
24*4882a593Smuzhiyun *     obtaining a copy of this software and associated documentation
25*4882a593Smuzhiyun *     files (the "Software"), to deal in the Software without
26*4882a593Smuzhiyun *     restriction, including without limitation the rights to use,
27*4882a593Smuzhiyun *     copy, modify, merge, publish, distribute, sublicense, and/or
28*4882a593Smuzhiyun *     sell copies of the Software, and to permit persons to whom the
29*4882a593Smuzhiyun *     Software is furnished to do so, subject to the following
30*4882a593Smuzhiyun *     conditions:
31*4882a593Smuzhiyun *
32*4882a593Smuzhiyun *     The above copyright notice and this permission notice shall be
33*4882a593Smuzhiyun *     included in all copies or substantial portions of the Software.
34*4882a593Smuzhiyun *
35*4882a593Smuzhiyun *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36*4882a593Smuzhiyun *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37*4882a593Smuzhiyun *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38*4882a593Smuzhiyun *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39*4882a593Smuzhiyun *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40*4882a593Smuzhiyun *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41*4882a593Smuzhiyun *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42*4882a593Smuzhiyun *     OTHER DEALINGS IN THE SOFTWARE.
43*4882a593Smuzhiyun */
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun#include "imx53.dtsi"
46*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun/ {
49*4882a593Smuzhiyun	model = "Ka-Ro electronics TX53 module";
50*4882a593Smuzhiyun	compatible = "karo,tx53", "fsl,imx53";
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun	/* Will be filled by the bootloader */
53*4882a593Smuzhiyun	memory@70000000 {
54*4882a593Smuzhiyun		device_type = "memory";
55*4882a593Smuzhiyun		reg = <0x70000000 0>;
56*4882a593Smuzhiyun	};
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun	aliases {
59*4882a593Smuzhiyun		can0 = &can2; /* Make the can interface indices consistent with TX28/TX48 modules */
60*4882a593Smuzhiyun		can1 = &can1;
61*4882a593Smuzhiyun		ipu = &ipu;
62*4882a593Smuzhiyun		reg-can-xcvr = &reg_can_xcvr;
63*4882a593Smuzhiyun		usbh1 = &usbh1;
64*4882a593Smuzhiyun		usbotg = &usbotg;
65*4882a593Smuzhiyun	};
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun	clocks {
68*4882a593Smuzhiyun		ckih1 {
69*4882a593Smuzhiyun			clock-frequency = <0>;
70*4882a593Smuzhiyun		};
71*4882a593Smuzhiyun	};
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun	mclk: clock-mclk {
74*4882a593Smuzhiyun		compatible = "fixed-clock";
75*4882a593Smuzhiyun		#clock-cells = <0>;
76*4882a593Smuzhiyun		clock-frequency = <26000000>;
77*4882a593Smuzhiyun	};
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun	gpio-keys {
80*4882a593Smuzhiyun		compatible = "gpio-keys";
81*4882a593Smuzhiyun		pinctrl-names = "default";
82*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_gpio_key>;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun		power {
85*4882a593Smuzhiyun			label = "Power Button";
86*4882a593Smuzhiyun			gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
87*4882a593Smuzhiyun			linux,code = <116>; /* KEY_POWER */
88*4882a593Smuzhiyun			wakeup-source;
89*4882a593Smuzhiyun		};
90*4882a593Smuzhiyun	};
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun	leds {
93*4882a593Smuzhiyun		compatible = "gpio-leds";
94*4882a593Smuzhiyun		pinctrl-names = "default";
95*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_stk5led>;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun		user {
98*4882a593Smuzhiyun			label = "Heartbeat";
99*4882a593Smuzhiyun			gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
100*4882a593Smuzhiyun			linux,default-trigger = "heartbeat";
101*4882a593Smuzhiyun		};
102*4882a593Smuzhiyun	};
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun	reg_2v5: regulator-2v5 {
105*4882a593Smuzhiyun		compatible = "regulator-fixed";
106*4882a593Smuzhiyun		regulator-name = "2V5";
107*4882a593Smuzhiyun		regulator-min-microvolt = <2500000>;
108*4882a593Smuzhiyun		regulator-max-microvolt = <2500000>;
109*4882a593Smuzhiyun	};
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun	reg_3v3: regulator-3v3 {
112*4882a593Smuzhiyun		compatible = "regulator-fixed";
113*4882a593Smuzhiyun		regulator-name = "3V3";
114*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
115*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
116*4882a593Smuzhiyun	};
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun	reg_can_xcvr: regulator-can-xcvr {
119*4882a593Smuzhiyun		compatible = "regulator-fixed";
120*4882a593Smuzhiyun		regulator-name = "CAN XCVR";
121*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
122*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
123*4882a593Smuzhiyun		pinctrl-names = "default";
124*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_can_xcvr>;
125*4882a593Smuzhiyun		gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
126*4882a593Smuzhiyun	};
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun	reg_usbh1_vbus: regulator-usbh1-vbus {
129*4882a593Smuzhiyun		compatible = "regulator-fixed";
130*4882a593Smuzhiyun		regulator-name = "usbh1_vbus";
131*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
132*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
133*4882a593Smuzhiyun		pinctrl-names = "default";
134*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_usbh1_vbus>;
135*4882a593Smuzhiyun		gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
136*4882a593Smuzhiyun		enable-active-high;
137*4882a593Smuzhiyun	};
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun	reg_usbotg_vbus: regulator-usbotg-vbus {
140*4882a593Smuzhiyun		compatible = "regulator-fixed";
141*4882a593Smuzhiyun		regulator-name = "usbotg_vbus";
142*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
143*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
144*4882a593Smuzhiyun		pinctrl-names = "default";
145*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_usbotg_vbus>;
146*4882a593Smuzhiyun		gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
147*4882a593Smuzhiyun		enable-active-high;
148*4882a593Smuzhiyun	};
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun	sound {
151*4882a593Smuzhiyun		compatible = "karo,tx53-audio-sgtl5000", "fsl,imx-audio-sgtl5000";
152*4882a593Smuzhiyun		model = "tx53-audio-sgtl5000";
153*4882a593Smuzhiyun		ssi-controller = <&ssi1>;
154*4882a593Smuzhiyun		audio-codec = <&sgtl5000>;
155*4882a593Smuzhiyun		audio-routing =
156*4882a593Smuzhiyun			"MIC_IN", "Mic Jack",
157*4882a593Smuzhiyun			"Mic Jack", "Mic Bias",
158*4882a593Smuzhiyun			"Headphone Jack", "HP_OUT";
159*4882a593Smuzhiyun		/* '1' based port numbers according to datasheet names */
160*4882a593Smuzhiyun		mux-int-port = <1>;
161*4882a593Smuzhiyun		mux-ext-port = <5>;
162*4882a593Smuzhiyun	};
163*4882a593Smuzhiyun};
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun&audmux {
166*4882a593Smuzhiyun	pinctrl-names = "default";
167*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_ssi1>;
168*4882a593Smuzhiyun	status = "okay";
169*4882a593Smuzhiyun};
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun&can1 {
172*4882a593Smuzhiyun	pinctrl-names = "default";
173*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_can1>;
174*4882a593Smuzhiyun	xceiver-supply = <&reg_can_xcvr>;
175*4882a593Smuzhiyun	status = "okay";
176*4882a593Smuzhiyun};
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun&can2 {
179*4882a593Smuzhiyun	pinctrl-names = "default";
180*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_can2>;
181*4882a593Smuzhiyun	xceiver-supply = <&reg_can_xcvr>;
182*4882a593Smuzhiyun	status = "okay";
183*4882a593Smuzhiyun};
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun&ecspi1 {
186*4882a593Smuzhiyun	pinctrl-names = "default";
187*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_ecspi1>;
188*4882a593Smuzhiyun	status = "okay";
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun	cs-gpios = <
191*4882a593Smuzhiyun		&gpio2 30 GPIO_ACTIVE_HIGH
192*4882a593Smuzhiyun		&gpio3 19 GPIO_ACTIVE_HIGH
193*4882a593Smuzhiyun	>;
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun	spidev0: spi@0 {
196*4882a593Smuzhiyun		compatible = "spidev";
197*4882a593Smuzhiyun		reg = <0>;
198*4882a593Smuzhiyun		spi-max-frequency = <54000000>;
199*4882a593Smuzhiyun	};
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun	spidev1: spi@1 {
202*4882a593Smuzhiyun		compatible = "spidev";
203*4882a593Smuzhiyun		reg = <1>;
204*4882a593Smuzhiyun		spi-max-frequency = <54000000>;
205*4882a593Smuzhiyun	};
206*4882a593Smuzhiyun};
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun&esdhc1 {
209*4882a593Smuzhiyun	cd-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
210*4882a593Smuzhiyun	fsl,wp-controller;
211*4882a593Smuzhiyun	pinctrl-names = "default";
212*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_esdhc1>;
213*4882a593Smuzhiyun	status = "okay";
214*4882a593Smuzhiyun};
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun&esdhc2 {
217*4882a593Smuzhiyun	cd-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
218*4882a593Smuzhiyun	fsl,wp-controller;
219*4882a593Smuzhiyun	pinctrl-names = "default";
220*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_esdhc2>;
221*4882a593Smuzhiyun	status = "okay";
222*4882a593Smuzhiyun};
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun&fec {
225*4882a593Smuzhiyun	pinctrl-names = "default";
226*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_fec>;
227*4882a593Smuzhiyun	phy-mode = "rmii";
228*4882a593Smuzhiyun	phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
229*4882a593Smuzhiyun	phy-handle = <&phy0>;
230*4882a593Smuzhiyun	mac-address = [000000000000]; /* placeholder; will be overwritten by bootloader */
231*4882a593Smuzhiyun	status = "okay";
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun	mdio {
234*4882a593Smuzhiyun		#address-cells = <1>;
235*4882a593Smuzhiyun		#size-cells = <0>;
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun		phy0: ethernet-phy@0 {
238*4882a593Smuzhiyun			reg = <0>;
239*4882a593Smuzhiyun			interrupt-parent = <&gpio2>;
240*4882a593Smuzhiyun			interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
241*4882a593Smuzhiyun			device_type = "ethernet-phy";
242*4882a593Smuzhiyun		};
243*4882a593Smuzhiyun	};
244*4882a593Smuzhiyun};
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun&i2c1 {
247*4882a593Smuzhiyun	pinctrl-names = "default", "gpio";
248*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c1>;
249*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c1_gpio>;
250*4882a593Smuzhiyun	scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
251*4882a593Smuzhiyun	sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
252*4882a593Smuzhiyun	clock-frequency = <400000>;
253*4882a593Smuzhiyun	status = "okay";
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun	rtc1: ds1339@68 {
256*4882a593Smuzhiyun		compatible = "dallas,ds1339";
257*4882a593Smuzhiyun		reg = <0x68>;
258*4882a593Smuzhiyun		pinctrl-names = "default";
259*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_ds1339>;
260*4882a593Smuzhiyun		interrupt-parent = <&gpio4>;
261*4882a593Smuzhiyun		interrupts = <20 IRQ_TYPE_EDGE_FALLING>;
262*4882a593Smuzhiyun		trickle-resistor-ohms = <250>;
263*4882a593Smuzhiyun		trickle-diode-disable;
264*4882a593Smuzhiyun	};
265*4882a593Smuzhiyun};
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun&iomuxc {
268*4882a593Smuzhiyun	pinctrl-names = "default";
269*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_hog>;
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun	imx53-tx53 {
272*4882a593Smuzhiyun		pinctrl_hog: hoggrp {
273*4882a593Smuzhiyun			/* pins not in use by any device on the Starterkit board series */
274*4882a593Smuzhiyun			fsl,pins = <
275*4882a593Smuzhiyun				/* CMOS Sensor Interface */
276*4882a593Smuzhiyun				MX53_PAD_CSI0_DAT12__GPIO5_30 0x1f4
277*4882a593Smuzhiyun				MX53_PAD_CSI0_DAT13__GPIO5_31 0x1f4
278*4882a593Smuzhiyun				MX53_PAD_CSI0_DAT14__GPIO6_0 0x1f4
279*4882a593Smuzhiyun				MX53_PAD_CSI0_DAT15__GPIO6_1 0x1f4
280*4882a593Smuzhiyun				MX53_PAD_CSI0_DAT16__GPIO6_2 0x1f4
281*4882a593Smuzhiyun				MX53_PAD_CSI0_DAT17__GPIO6_3 0x1f4
282*4882a593Smuzhiyun				MX53_PAD_CSI0_DAT18__GPIO6_4 0x1f4
283*4882a593Smuzhiyun				MX53_PAD_CSI0_DAT19__GPIO6_5 0x1f4
284*4882a593Smuzhiyun				MX53_PAD_CSI0_MCLK__GPIO5_19 0x1f4
285*4882a593Smuzhiyun				MX53_PAD_CSI0_VSYNC__GPIO5_21 0x1f4
286*4882a593Smuzhiyun				MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x1f4
287*4882a593Smuzhiyun				MX53_PAD_GPIO_0__GPIO1_0 0x1f4
288*4882a593Smuzhiyun				/* Module Specific Signal */
289*4882a593Smuzhiyun				/* MX53_PAD_NANDF_CS2__GPIO6_15 0x1f4 maybe used by EDT-FT5x06 */
290*4882a593Smuzhiyun				/* MX53_PAD_EIM_A16__GPIO2_22 0x1f4 maybe used by EDT-FT5x06 */
291*4882a593Smuzhiyun				MX53_PAD_EIM_D29__GPIO3_29 0x1f4
292*4882a593Smuzhiyun				MX53_PAD_EIM_EB3__GPIO2_31 0x1f4
293*4882a593Smuzhiyun				/* MX53_PAD_EIM_A17__GPIO2_21 0x1f4 maybe used by EDT-FT5x06 */
294*4882a593Smuzhiyun				/* MX53_PAD_EIM_A18__GPIO2_20 0x1f4 used by LED */
295*4882a593Smuzhiyun				MX53_PAD_EIM_A19__GPIO2_19 0x1f4
296*4882a593Smuzhiyun				MX53_PAD_EIM_A20__GPIO2_18 0x1f4
297*4882a593Smuzhiyun				MX53_PAD_EIM_A21__GPIO2_17 0x1f4
298*4882a593Smuzhiyun				MX53_PAD_EIM_A22__GPIO2_16 0x1f4
299*4882a593Smuzhiyun				MX53_PAD_EIM_A23__GPIO6_6 0x1f4
300*4882a593Smuzhiyun				MX53_PAD_EIM_A24__GPIO5_4 0x1f4
301*4882a593Smuzhiyun				MX53_PAD_CSI0_DAT8__GPIO5_26 0x1f4
302*4882a593Smuzhiyun				MX53_PAD_CSI0_DAT9__GPIO5_27 0x1f4
303*4882a593Smuzhiyun				MX53_PAD_CSI0_DAT10__GPIO5_28 0x1f4
304*4882a593Smuzhiyun				MX53_PAD_CSI0_DAT11__GPIO5_29 0x1f4
305*4882a593Smuzhiyun				/* MX53_PAD_EIM_D22__GPIO3_22 0x1f4 maybe used by EETI touchpanel driver */
306*4882a593Smuzhiyun				/* MX53_PAD_EIM_D23__GPIO3_23 0x1f4 maybe used by EETI touchpanel driver */
307*4882a593Smuzhiyun				MX53_PAD_GPIO_13__GPIO4_3 0x1f4
308*4882a593Smuzhiyun				MX53_PAD_EIM_CS0__GPIO2_23 0x1f4
309*4882a593Smuzhiyun				MX53_PAD_EIM_CS1__GPIO2_24 0x1f4
310*4882a593Smuzhiyun				MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x1f4
311*4882a593Smuzhiyun				MX53_PAD_EIM_WAIT__GPIO5_0 0x1f4
312*4882a593Smuzhiyun				MX53_PAD_EIM_EB0__GPIO2_28 0x1f4
313*4882a593Smuzhiyun				MX53_PAD_EIM_EB1__GPIO2_29 0x1f4
314*4882a593Smuzhiyun				MX53_PAD_EIM_OE__GPIO2_25 0x1f4
315*4882a593Smuzhiyun				MX53_PAD_EIM_LBA__GPIO2_27 0x1f4
316*4882a593Smuzhiyun				MX53_PAD_EIM_RW__GPIO2_26 0x1f4
317*4882a593Smuzhiyun				MX53_PAD_EIM_DA8__GPIO3_8 0x1f4
318*4882a593Smuzhiyun				MX53_PAD_EIM_DA9__GPIO3_9 0x1f4
319*4882a593Smuzhiyun				MX53_PAD_EIM_DA10__GPIO3_10 0x1f4
320*4882a593Smuzhiyun				MX53_PAD_EIM_DA11__GPIO3_11 0x1f4
321*4882a593Smuzhiyun				MX53_PAD_EIM_DA12__GPIO3_12 0x1f4
322*4882a593Smuzhiyun				MX53_PAD_EIM_DA13__GPIO3_13 0x1f4
323*4882a593Smuzhiyun				MX53_PAD_EIM_DA14__GPIO3_14 0x1f4
324*4882a593Smuzhiyun				MX53_PAD_EIM_DA15__GPIO3_15 0x1f4
325*4882a593Smuzhiyun				>;
326*4882a593Smuzhiyun		};
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun		pinctrl_can1: can1grp {
329*4882a593Smuzhiyun			fsl,pins = <
330*4882a593Smuzhiyun				MX53_PAD_GPIO_7__CAN1_TXCAN		0x80000000
331*4882a593Smuzhiyun				MX53_PAD_GPIO_8__CAN1_RXCAN		0x80000000
332*4882a593Smuzhiyun			>;
333*4882a593Smuzhiyun		};
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun		pinctrl_can2: can2grp {
336*4882a593Smuzhiyun			fsl,pins = <
337*4882a593Smuzhiyun				MX53_PAD_KEY_COL4__CAN2_TXCAN		0x80000000
338*4882a593Smuzhiyun				MX53_PAD_KEY_ROW4__CAN2_RXCAN		0x80000000
339*4882a593Smuzhiyun			>;
340*4882a593Smuzhiyun		};
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun		pinctrl_can_xcvr: can-xcvrgrp {
343*4882a593Smuzhiyun			fsl,pins = <MX53_PAD_DISP0_DAT0__GPIO4_21 0xe0>; /* Flexcan XCVR enable */
344*4882a593Smuzhiyun		};
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun		pinctrl_ds1339: ds1339grp {
347*4882a593Smuzhiyun			fsl,pins = <MX53_PAD_DI0_PIN4__GPIO4_20 0xe0>;
348*4882a593Smuzhiyun		};
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun		pinctrl_ecspi1: ecspi1grp {
351*4882a593Smuzhiyun			fsl,pins = <
352*4882a593Smuzhiyun				MX53_PAD_GPIO_19__ECSPI1_RDY		0x80000000
353*4882a593Smuzhiyun				MX53_PAD_EIM_EB2__ECSPI1_SS0		0x80000000
354*4882a593Smuzhiyun				MX53_PAD_EIM_D16__ECSPI1_SCLK		0x80000000
355*4882a593Smuzhiyun				MX53_PAD_EIM_D17__ECSPI1_MISO		0x80000000
356*4882a593Smuzhiyun				MX53_PAD_EIM_D18__ECSPI1_MOSI		0x80000000
357*4882a593Smuzhiyun				MX53_PAD_EIM_D19__ECSPI1_SS1		0x80000000
358*4882a593Smuzhiyun			>;
359*4882a593Smuzhiyun		};
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun		pinctrl_esdhc1: esdhc1grp {
362*4882a593Smuzhiyun			fsl,pins = <
363*4882a593Smuzhiyun				MX53_PAD_SD1_DATA0__ESDHC1_DAT0		0x1d5
364*4882a593Smuzhiyun				MX53_PAD_SD1_DATA1__ESDHC1_DAT1		0x1d5
365*4882a593Smuzhiyun				MX53_PAD_SD1_DATA2__ESDHC1_DAT2		0x1d5
366*4882a593Smuzhiyun				MX53_PAD_SD1_DATA3__ESDHC1_DAT3		0x1d5
367*4882a593Smuzhiyun				MX53_PAD_SD1_CMD__ESDHC1_CMD		0x1d5
368*4882a593Smuzhiyun				MX53_PAD_SD1_CLK__ESDHC1_CLK		0x1d5
369*4882a593Smuzhiyun				MX53_PAD_EIM_D24__GPIO3_24 0x1f0
370*4882a593Smuzhiyun			>;
371*4882a593Smuzhiyun		};
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun		pinctrl_esdhc2: esdhc2grp {
374*4882a593Smuzhiyun			fsl,pins = <
375*4882a593Smuzhiyun				MX53_PAD_SD2_CMD__ESDHC2_CMD		0x1d5
376*4882a593Smuzhiyun				MX53_PAD_SD2_CLK__ESDHC2_CLK		0x1d5
377*4882a593Smuzhiyun				MX53_PAD_SD2_DATA0__ESDHC2_DAT0		0x1d5
378*4882a593Smuzhiyun				MX53_PAD_SD2_DATA1__ESDHC2_DAT1		0x1d5
379*4882a593Smuzhiyun				MX53_PAD_SD2_DATA2__ESDHC2_DAT2		0x1d5
380*4882a593Smuzhiyun				MX53_PAD_SD2_DATA3__ESDHC2_DAT3		0x1d5
381*4882a593Smuzhiyun				MX53_PAD_EIM_D25__GPIO3_25 0x1f0
382*4882a593Smuzhiyun			>;
383*4882a593Smuzhiyun		};
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun		pinctrl_fec: fecgrp {
386*4882a593Smuzhiyun			fsl,pins = <
387*4882a593Smuzhiyun				MX53_PAD_FEC_MDC__FEC_MDC		0x80000000
388*4882a593Smuzhiyun				MX53_PAD_FEC_MDIO__FEC_MDIO		0x80000000
389*4882a593Smuzhiyun				MX53_PAD_FEC_REF_CLK__FEC_TX_CLK	0x80000000
390*4882a593Smuzhiyun				MX53_PAD_FEC_RX_ER__FEC_RX_ER		0x80000000
391*4882a593Smuzhiyun				MX53_PAD_FEC_CRS_DV__FEC_RX_DV		0x80000000
392*4882a593Smuzhiyun				MX53_PAD_FEC_RXD1__FEC_RDATA_1		0x80000000
393*4882a593Smuzhiyun				MX53_PAD_FEC_RXD0__FEC_RDATA_0		0x80000000
394*4882a593Smuzhiyun				MX53_PAD_FEC_TX_EN__FEC_TX_EN		0x80000000
395*4882a593Smuzhiyun				MX53_PAD_FEC_TXD1__FEC_TDATA_1		0x80000000
396*4882a593Smuzhiyun				MX53_PAD_FEC_TXD0__FEC_TDATA_0		0x80000000
397*4882a593Smuzhiyun			>;
398*4882a593Smuzhiyun		};
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun		pinctrl_gpio_key: gpio-keygrp {
401*4882a593Smuzhiyun			fsl,pins = <MX53_PAD_EIM_A25__GPIO5_2 0x1f4>;
402*4882a593Smuzhiyun		};
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun		pinctrl_i2c1: i2c1grp {
405*4882a593Smuzhiyun			fsl,pins = <
406*4882a593Smuzhiyun				MX53_PAD_EIM_D21__I2C1_SCL		0x400001e4
407*4882a593Smuzhiyun				MX53_PAD_EIM_D28__I2C1_SDA		0x400001e4
408*4882a593Smuzhiyun			>;
409*4882a593Smuzhiyun		};
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun		pinctrl_i2c1_gpio: i2c1-gpiogrp {
412*4882a593Smuzhiyun			fsl,pins = <
413*4882a593Smuzhiyun				MX53_PAD_EIM_D21__GPIO3_21		0x400001e6
414*4882a593Smuzhiyun				MX53_PAD_EIM_D28__GPIO3_28		0x400001e6
415*4882a593Smuzhiyun			>;
416*4882a593Smuzhiyun		};
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun		pinctrl_i2c3: i2c3grp {
419*4882a593Smuzhiyun			fsl,pins = <
420*4882a593Smuzhiyun				MX53_PAD_GPIO_3__I2C3_SCL		0x400001e4
421*4882a593Smuzhiyun				MX53_PAD_GPIO_6__I2C3_SDA		0x400001e4
422*4882a593Smuzhiyun			>;
423*4882a593Smuzhiyun		};
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun		pinctrl_i2c3_gpio: i2c3-gpiogrp {
426*4882a593Smuzhiyun			fsl,pins = <
427*4882a593Smuzhiyun				MX53_PAD_GPIO_3__GPIO1_3		0x400001e6
428*4882a593Smuzhiyun				MX53_PAD_GPIO_6__GPIO1_6		0x400001e6
429*4882a593Smuzhiyun			>;
430*4882a593Smuzhiyun		};
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun		pinctrl_nand: nandgrp {
433*4882a593Smuzhiyun			fsl,pins = <
434*4882a593Smuzhiyun				MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B	0x4
435*4882a593Smuzhiyun				MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B	0x4
436*4882a593Smuzhiyun				MX53_PAD_NANDF_CLE__EMI_NANDF_CLE	0x4
437*4882a593Smuzhiyun				MX53_PAD_NANDF_ALE__EMI_NANDF_ALE	0x4
438*4882a593Smuzhiyun				MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B	0xe0
439*4882a593Smuzhiyun				MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0	0xe0
440*4882a593Smuzhiyun				MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0	0x4
441*4882a593Smuzhiyun				MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0	0xa4
442*4882a593Smuzhiyun				MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1	0xa4
443*4882a593Smuzhiyun				MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2	0xa4
444*4882a593Smuzhiyun				MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3	0xa4
445*4882a593Smuzhiyun				MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4	0xa4
446*4882a593Smuzhiyun				MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5	0xa4
447*4882a593Smuzhiyun				MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6	0xa4
448*4882a593Smuzhiyun				MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7	0xa4
449*4882a593Smuzhiyun			>;
450*4882a593Smuzhiyun		};
451*4882a593Smuzhiyun
452*4882a593Smuzhiyun		pinctrl_pwm2: pwm2grp {
453*4882a593Smuzhiyun			fsl,pins = <
454*4882a593Smuzhiyun				MX53_PAD_GPIO_1__PWM2_PWMO		0x80000000
455*4882a593Smuzhiyun			>;
456*4882a593Smuzhiyun		};
457*4882a593Smuzhiyun
458*4882a593Smuzhiyun		pinctrl_ssi1: ssi1grp {
459*4882a593Smuzhiyun			fsl,pins = <
460*4882a593Smuzhiyun				MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC	0x80000000
461*4882a593Smuzhiyun				MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD	0x80000000
462*4882a593Smuzhiyun				MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS	0x80000000
463*4882a593Smuzhiyun				MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD	0x80000000
464*4882a593Smuzhiyun			>;
465*4882a593Smuzhiyun		};
466*4882a593Smuzhiyun
467*4882a593Smuzhiyun		pinctrl_ssi2: ssi2grp {
468*4882a593Smuzhiyun			fsl,pins = <
469*4882a593Smuzhiyun				MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC	0x80000000
470*4882a593Smuzhiyun				MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD	0x80000000
471*4882a593Smuzhiyun				MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS	0x80000000
472*4882a593Smuzhiyun				MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD	0x80000000
473*4882a593Smuzhiyun				MX53_PAD_EIM_D27__GPIO3_27 0x1f0
474*4882a593Smuzhiyun			>;
475*4882a593Smuzhiyun		};
476*4882a593Smuzhiyun
477*4882a593Smuzhiyun		pinctrl_stk5led: stk5ledgrp {
478*4882a593Smuzhiyun			fsl,pins = <MX53_PAD_EIM_A18__GPIO2_20 0xc0>;
479*4882a593Smuzhiyun		};
480*4882a593Smuzhiyun
481*4882a593Smuzhiyun		pinctrl_uart1: uart1grp {
482*4882a593Smuzhiyun			fsl,pins = <
483*4882a593Smuzhiyun				MX53_PAD_PATA_DIOW__UART1_TXD_MUX	0x1e4
484*4882a593Smuzhiyun				MX53_PAD_PATA_DMACK__UART1_RXD_MUX	0x1e4
485*4882a593Smuzhiyun				MX53_PAD_PATA_RESET_B__UART1_CTS	0x1c5
486*4882a593Smuzhiyun				MX53_PAD_PATA_IORDY__UART1_RTS		0x1c5
487*4882a593Smuzhiyun			>;
488*4882a593Smuzhiyun		};
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun		pinctrl_uart2: uart2grp {
491*4882a593Smuzhiyun			fsl,pins = <
492*4882a593Smuzhiyun				MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX	0x1c5
493*4882a593Smuzhiyun				MX53_PAD_PATA_DMARQ__UART2_TXD_MUX	0x1c5
494*4882a593Smuzhiyun				MX53_PAD_PATA_DIOR__UART2_RTS		0x1c5
495*4882a593Smuzhiyun				MX53_PAD_PATA_INTRQ__UART2_CTS		0x1c5
496*4882a593Smuzhiyun			>;
497*4882a593Smuzhiyun		};
498*4882a593Smuzhiyun
499*4882a593Smuzhiyun		pinctrl_uart3: uart3grp {
500*4882a593Smuzhiyun			fsl,pins = <
501*4882a593Smuzhiyun				MX53_PAD_PATA_CS_0__UART3_TXD_MUX	0x1e4
502*4882a593Smuzhiyun				MX53_PAD_PATA_CS_1__UART3_RXD_MUX	0x1e4
503*4882a593Smuzhiyun				MX53_PAD_PATA_DA_1__UART3_CTS		0x1e4
504*4882a593Smuzhiyun				MX53_PAD_PATA_DA_2__UART3_RTS		0x1e4
505*4882a593Smuzhiyun			>;
506*4882a593Smuzhiyun		};
507*4882a593Smuzhiyun
508*4882a593Smuzhiyun		pinctrl_usbh1: usbh1grp {
509*4882a593Smuzhiyun			fsl,pins = <
510*4882a593Smuzhiyun				MX53_PAD_EIM_D30__GPIO3_30 0x100 /* OC */
511*4882a593Smuzhiyun			>;
512*4882a593Smuzhiyun		};
513*4882a593Smuzhiyun
514*4882a593Smuzhiyun		pinctrl_usbh1_vbus: usbh1-vbusgrp {
515*4882a593Smuzhiyun			fsl,pins = <
516*4882a593Smuzhiyun				MX53_PAD_EIM_D31__GPIO3_31 0xe0 /* VBUS ENABLE */
517*4882a593Smuzhiyun			>;
518*4882a593Smuzhiyun		};
519*4882a593Smuzhiyun
520*4882a593Smuzhiyun		pinctrl_usbotg_vbus: usbotg-vbusgrp {
521*4882a593Smuzhiyun			fsl,pins = <
522*4882a593Smuzhiyun				MX53_PAD_GPIO_7__GPIO1_7 0xe0 /* VBUS ENABLE */
523*4882a593Smuzhiyun				MX53_PAD_GPIO_8__GPIO1_8 0x100 /* OC */
524*4882a593Smuzhiyun			>;
525*4882a593Smuzhiyun		};
526*4882a593Smuzhiyun	};
527*4882a593Smuzhiyun};
528*4882a593Smuzhiyun
529*4882a593Smuzhiyun&ipu {
530*4882a593Smuzhiyun	status = "okay";
531*4882a593Smuzhiyun};
532*4882a593Smuzhiyun
533*4882a593Smuzhiyun&nfc {
534*4882a593Smuzhiyun	pinctrl-names = "default";
535*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_nand>;
536*4882a593Smuzhiyun	nand-bus-width = <8>;
537*4882a593Smuzhiyun	nand-ecc-mode = "hw";
538*4882a593Smuzhiyun	nand-on-flash-bbt;
539*4882a593Smuzhiyun	status = "okay";
540*4882a593Smuzhiyun};
541*4882a593Smuzhiyun
542*4882a593Smuzhiyun&pwm2 {
543*4882a593Smuzhiyun	pinctrl-names = "default";
544*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pwm2>;
545*4882a593Smuzhiyun};
546*4882a593Smuzhiyun
547*4882a593Smuzhiyun&sdma {
548*4882a593Smuzhiyun	fsl,sdma-ram-script-name = "sdma-imx53.bin";
549*4882a593Smuzhiyun};
550*4882a593Smuzhiyun
551*4882a593Smuzhiyun&ssi1 {
552*4882a593Smuzhiyun	status = "okay";
553*4882a593Smuzhiyun};
554*4882a593Smuzhiyun
555*4882a593Smuzhiyun&ssi2 {
556*4882a593Smuzhiyun	status = "disabled";
557*4882a593Smuzhiyun};
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun&uart1 {
560*4882a593Smuzhiyun	pinctrl-names = "default";
561*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart1>;
562*4882a593Smuzhiyun	uart-has-rtscts;
563*4882a593Smuzhiyun	status = "okay";
564*4882a593Smuzhiyun};
565*4882a593Smuzhiyun
566*4882a593Smuzhiyun&uart2 {
567*4882a593Smuzhiyun	pinctrl-names = "default";
568*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart2>;
569*4882a593Smuzhiyun	uart-has-rtscts;
570*4882a593Smuzhiyun	status = "okay";
571*4882a593Smuzhiyun};
572*4882a593Smuzhiyun
573*4882a593Smuzhiyun&uart3 {
574*4882a593Smuzhiyun	pinctrl-names = "default";
575*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart3>;
576*4882a593Smuzhiyun	uart-has-rtscts;
577*4882a593Smuzhiyun	status = "okay";
578*4882a593Smuzhiyun};
579*4882a593Smuzhiyun
580*4882a593Smuzhiyun&usbh1 {
581*4882a593Smuzhiyun	pinctrl-names = "default";
582*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usbh1>;
583*4882a593Smuzhiyun	phy_type = "utmi";
584*4882a593Smuzhiyun	disable-over-current;
585*4882a593Smuzhiyun	vbus-supply = <&reg_usbh1_vbus>;
586*4882a593Smuzhiyun	status = "okay";
587*4882a593Smuzhiyun};
588*4882a593Smuzhiyun
589*4882a593Smuzhiyun&usbotg {
590*4882a593Smuzhiyun	phy_type = "utmi";
591*4882a593Smuzhiyun	dr_mode = "peripheral";
592*4882a593Smuzhiyun	disable-over-current;
593*4882a593Smuzhiyun	vbus-supply = <&reg_usbotg_vbus>;
594*4882a593Smuzhiyun	status = "okay";
595*4882a593Smuzhiyun};
596