1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0+ 2*4882a593Smuzhiyun// 3*4882a593Smuzhiyun// Copyright 2011 Freescale Semiconductor, Inc. 4*4882a593Smuzhiyun// Copyright 2011 Linaro Ltd. 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun#include "imx53.dtsi" 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/ { 9*4882a593Smuzhiyun chosen { 10*4882a593Smuzhiyun stdout-path = &uart1; 11*4882a593Smuzhiyun }; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun memory@70000000 { 14*4882a593Smuzhiyun device_type = "memory"; 15*4882a593Smuzhiyun reg = <0x70000000 0x20000000>, 16*4882a593Smuzhiyun <0xb0000000 0x20000000>; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun display0: disp0 { 20*4882a593Smuzhiyun compatible = "fsl,imx-parallel-display"; 21*4882a593Smuzhiyun pinctrl-names = "default"; 22*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_ipu_disp0>; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #address-cells = <1>; 25*4882a593Smuzhiyun #size-cells = <0>; 26*4882a593Smuzhiyun status = "disabled"; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun port@0 { 29*4882a593Smuzhiyun reg = <0>; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun display0_in: endpoint { 32*4882a593Smuzhiyun remote-endpoint = <&ipu_di0_disp0>; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun port@1 { 37*4882a593Smuzhiyun reg = <1>; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun display_out: endpoint { 40*4882a593Smuzhiyun remote-endpoint = <&panel_in>; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun gpio-keys { 46*4882a593Smuzhiyun compatible = "gpio-keys"; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun power { 49*4882a593Smuzhiyun label = "Power Button"; 50*4882a593Smuzhiyun gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; 51*4882a593Smuzhiyun linux,code = <KEY_POWER>; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun volume-up { 55*4882a593Smuzhiyun label = "Volume Up"; 56*4882a593Smuzhiyun gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; 57*4882a593Smuzhiyun linux,code = <KEY_VOLUMEUP>; 58*4882a593Smuzhiyun wakeup-source; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun volume-down { 62*4882a593Smuzhiyun label = "Volume Down"; 63*4882a593Smuzhiyun gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; 64*4882a593Smuzhiyun linux,code = <KEY_VOLUMEDOWN>; 65*4882a593Smuzhiyun wakeup-source; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun leds { 70*4882a593Smuzhiyun compatible = "gpio-leds"; 71*4882a593Smuzhiyun pinctrl-names = "default"; 72*4882a593Smuzhiyun pinctrl-0 = <&led_pin_gpio7_7>; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun user { 75*4882a593Smuzhiyun label = "Heartbeat"; 76*4882a593Smuzhiyun gpios = <&gpio7 7 0>; 77*4882a593Smuzhiyun linux,default-trigger = "heartbeat"; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun panel { 82*4882a593Smuzhiyun compatible = "sii,43wvf1g"; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun port { 85*4882a593Smuzhiyun panel_in: endpoint { 86*4882a593Smuzhiyun remote-endpoint = <&display_out>; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun regulators { 92*4882a593Smuzhiyun compatible = "simple-bus"; 93*4882a593Smuzhiyun #address-cells = <1>; 94*4882a593Smuzhiyun #size-cells = <0>; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun reg_3p2v: regulator@0 { 97*4882a593Smuzhiyun compatible = "regulator-fixed"; 98*4882a593Smuzhiyun reg = <0>; 99*4882a593Smuzhiyun regulator-name = "3P2V"; 100*4882a593Smuzhiyun regulator-min-microvolt = <3200000>; 101*4882a593Smuzhiyun regulator-max-microvolt = <3200000>; 102*4882a593Smuzhiyun regulator-always-on; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun reg_usb_vbus: regulator@1 { 106*4882a593Smuzhiyun compatible = "regulator-fixed"; 107*4882a593Smuzhiyun reg = <1>; 108*4882a593Smuzhiyun regulator-name = "usb_vbus"; 109*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 110*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 111*4882a593Smuzhiyun gpio = <&gpio7 8 0>; 112*4882a593Smuzhiyun enable-active-high; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun }; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun sound { 117*4882a593Smuzhiyun compatible = "fsl,imx53-qsb-sgtl5000", 118*4882a593Smuzhiyun "fsl,imx-audio-sgtl5000"; 119*4882a593Smuzhiyun model = "imx53-qsb-sgtl5000"; 120*4882a593Smuzhiyun ssi-controller = <&ssi2>; 121*4882a593Smuzhiyun audio-codec = <&sgtl5000>; 122*4882a593Smuzhiyun audio-routing = 123*4882a593Smuzhiyun "MIC_IN", "Mic Jack", 124*4882a593Smuzhiyun "Mic Jack", "Mic Bias", 125*4882a593Smuzhiyun "Headphone Jack", "HP_OUT"; 126*4882a593Smuzhiyun mux-int-port = <2>; 127*4882a593Smuzhiyun mux-ext-port = <5>; 128*4882a593Smuzhiyun }; 129*4882a593Smuzhiyun}; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun&cpu0 { 132*4882a593Smuzhiyun /* CPU rated to 1GHz, not 1.2GHz as per the default settings */ 133*4882a593Smuzhiyun operating-points = < 134*4882a593Smuzhiyun /* kHz uV */ 135*4882a593Smuzhiyun 166666 850000 136*4882a593Smuzhiyun 400000 900000 137*4882a593Smuzhiyun 800000 1050000 138*4882a593Smuzhiyun 1000000 1200000 139*4882a593Smuzhiyun >; 140*4882a593Smuzhiyun}; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun&esdhc1 { 143*4882a593Smuzhiyun pinctrl-names = "default"; 144*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_esdhc1>; 145*4882a593Smuzhiyun status = "okay"; 146*4882a593Smuzhiyun}; 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun&ipu_di0_disp0 { 149*4882a593Smuzhiyun remote-endpoint = <&display0_in>; 150*4882a593Smuzhiyun}; 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun&ssi2 { 153*4882a593Smuzhiyun status = "okay"; 154*4882a593Smuzhiyun}; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun&esdhc3 { 157*4882a593Smuzhiyun pinctrl-names = "default"; 158*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_esdhc3>; 159*4882a593Smuzhiyun cd-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; 160*4882a593Smuzhiyun wp-gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>; 161*4882a593Smuzhiyun bus-width = <8>; 162*4882a593Smuzhiyun status = "okay"; 163*4882a593Smuzhiyun}; 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun&iomuxc { 166*4882a593Smuzhiyun pinctrl-names = "default"; 167*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_hog>; 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun imx53-qsb { 170*4882a593Smuzhiyun pinctrl_hog: hoggrp { 171*4882a593Smuzhiyun fsl,pins = < 172*4882a593Smuzhiyun MX53_PAD_GPIO_8__GPIO1_8 0x80000000 173*4882a593Smuzhiyun MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 174*4882a593Smuzhiyun MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 175*4882a593Smuzhiyun MX53_PAD_EIM_DA11__GPIO3_11 0x80000000 176*4882a593Smuzhiyun MX53_PAD_EIM_DA12__GPIO3_12 0x80000000 177*4882a593Smuzhiyun MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 178*4882a593Smuzhiyun MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000 179*4882a593Smuzhiyun MX53_PAD_GPIO_16__GPIO7_11 0x80000000 180*4882a593Smuzhiyun >; 181*4882a593Smuzhiyun }; 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun led_pin_gpio7_7: led_gpio7_7 { 184*4882a593Smuzhiyun fsl,pins = < 185*4882a593Smuzhiyun MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000 186*4882a593Smuzhiyun >; 187*4882a593Smuzhiyun }; 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun pinctrl_audmux: audmuxgrp { 190*4882a593Smuzhiyun fsl,pins = < 191*4882a593Smuzhiyun MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 192*4882a593Smuzhiyun MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 193*4882a593Smuzhiyun MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 194*4882a593Smuzhiyun MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 195*4882a593Smuzhiyun >; 196*4882a593Smuzhiyun }; 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun pinctrl_codec: codecgrp { 199*4882a593Smuzhiyun fsl,pins = < 200*4882a593Smuzhiyun MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4 201*4882a593Smuzhiyun >; 202*4882a593Smuzhiyun }; 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun pinctrl_esdhc1: esdhc1grp { 205*4882a593Smuzhiyun fsl,pins = < 206*4882a593Smuzhiyun MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 207*4882a593Smuzhiyun MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 208*4882a593Smuzhiyun MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 209*4882a593Smuzhiyun MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 210*4882a593Smuzhiyun MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 211*4882a593Smuzhiyun MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 212*4882a593Smuzhiyun >; 213*4882a593Smuzhiyun }; 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun pinctrl_esdhc3: esdhc3grp { 216*4882a593Smuzhiyun fsl,pins = < 217*4882a593Smuzhiyun MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 218*4882a593Smuzhiyun MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 219*4882a593Smuzhiyun MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 220*4882a593Smuzhiyun MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 221*4882a593Smuzhiyun MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5 222*4882a593Smuzhiyun MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5 223*4882a593Smuzhiyun MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5 224*4882a593Smuzhiyun MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5 225*4882a593Smuzhiyun MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 226*4882a593Smuzhiyun MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 227*4882a593Smuzhiyun >; 228*4882a593Smuzhiyun }; 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun pinctrl_fec: fecgrp { 231*4882a593Smuzhiyun fsl,pins = < 232*4882a593Smuzhiyun MX53_PAD_FEC_MDC__FEC_MDC 0x4 233*4882a593Smuzhiyun MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc 234*4882a593Smuzhiyun MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180 235*4882a593Smuzhiyun MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180 236*4882a593Smuzhiyun MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180 237*4882a593Smuzhiyun MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180 238*4882a593Smuzhiyun MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180 239*4882a593Smuzhiyun MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4 240*4882a593Smuzhiyun MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4 241*4882a593Smuzhiyun MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4 242*4882a593Smuzhiyun >; 243*4882a593Smuzhiyun }; 244*4882a593Smuzhiyun 245*4882a593Smuzhiyun /* open drain */ 246*4882a593Smuzhiyun pinctrl_i2c1: i2c1grp { 247*4882a593Smuzhiyun fsl,pins = < 248*4882a593Smuzhiyun MX53_PAD_CSI0_DAT8__I2C1_SDA 0x400001ec 249*4882a593Smuzhiyun MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec 250*4882a593Smuzhiyun >; 251*4882a593Smuzhiyun }; 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun pinctrl_i2c2: i2c2grp { 254*4882a593Smuzhiyun fsl,pins = < 255*4882a593Smuzhiyun MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 256*4882a593Smuzhiyun MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 257*4882a593Smuzhiyun >; 258*4882a593Smuzhiyun }; 259*4882a593Smuzhiyun 260*4882a593Smuzhiyun pinctrl_ipu_disp0: ipudisp0grp { 261*4882a593Smuzhiyun fsl,pins = < 262*4882a593Smuzhiyun MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5 263*4882a593Smuzhiyun MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5 264*4882a593Smuzhiyun MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5 265*4882a593Smuzhiyun MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5 266*4882a593Smuzhiyun MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5 267*4882a593Smuzhiyun MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5 268*4882a593Smuzhiyun MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5 269*4882a593Smuzhiyun MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5 270*4882a593Smuzhiyun MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5 271*4882a593Smuzhiyun MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5 272*4882a593Smuzhiyun MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5 273*4882a593Smuzhiyun MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5 274*4882a593Smuzhiyun MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5 275*4882a593Smuzhiyun MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5 276*4882a593Smuzhiyun MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5 277*4882a593Smuzhiyun MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5 278*4882a593Smuzhiyun MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5 279*4882a593Smuzhiyun MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5 280*4882a593Smuzhiyun MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5 281*4882a593Smuzhiyun MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5 282*4882a593Smuzhiyun MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5 283*4882a593Smuzhiyun MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5 284*4882a593Smuzhiyun MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5 285*4882a593Smuzhiyun MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5 286*4882a593Smuzhiyun MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5 287*4882a593Smuzhiyun MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5 288*4882a593Smuzhiyun MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5 289*4882a593Smuzhiyun MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5 290*4882a593Smuzhiyun >; 291*4882a593Smuzhiyun }; 292*4882a593Smuzhiyun 293*4882a593Smuzhiyun pinctrl_vga_sync: vgasync-grp { 294*4882a593Smuzhiyun fsl,pins = < 295*4882a593Smuzhiyun /* VGA_HSYNC, VSYNC with max drive strength */ 296*4882a593Smuzhiyun MX53_PAD_EIM_OE__IPU_DI1_PIN7 0xe6 297*4882a593Smuzhiyun MX53_PAD_EIM_RW__IPU_DI1_PIN8 0xe6 298*4882a593Smuzhiyun >; 299*4882a593Smuzhiyun }; 300*4882a593Smuzhiyun 301*4882a593Smuzhiyun pinctrl_uart1: uart1grp { 302*4882a593Smuzhiyun fsl,pins = < 303*4882a593Smuzhiyun MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4 304*4882a593Smuzhiyun MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4 305*4882a593Smuzhiyun >; 306*4882a593Smuzhiyun }; 307*4882a593Smuzhiyun }; 308*4882a593Smuzhiyun}; 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun&tve { 311*4882a593Smuzhiyun pinctrl-names = "default"; 312*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_vga_sync>; 313*4882a593Smuzhiyun ddc-i2c-bus = <&i2c2>; 314*4882a593Smuzhiyun fsl,tve-mode = "vga"; 315*4882a593Smuzhiyun fsl,hsync-pin = <7>; /* IPU DI1 PIN7 via EIM_OE */ 316*4882a593Smuzhiyun fsl,vsync-pin = <8>; /* IPU DI1 PIN8 via EIM_RW */ 317*4882a593Smuzhiyun status = "okay"; 318*4882a593Smuzhiyun}; 319*4882a593Smuzhiyun 320*4882a593Smuzhiyun&uart1 { 321*4882a593Smuzhiyun pinctrl-names = "default"; 322*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart1>; 323*4882a593Smuzhiyun status = "okay"; 324*4882a593Smuzhiyun}; 325*4882a593Smuzhiyun 326*4882a593Smuzhiyun&i2c2 { 327*4882a593Smuzhiyun pinctrl-names = "default"; 328*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c2>; 329*4882a593Smuzhiyun status = "okay"; 330*4882a593Smuzhiyun 331*4882a593Smuzhiyun sgtl5000: codec@a { 332*4882a593Smuzhiyun compatible = "fsl,sgtl5000"; 333*4882a593Smuzhiyun reg = <0x0a>; 334*4882a593Smuzhiyun pinctrl-names = "default"; 335*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_codec>; 336*4882a593Smuzhiyun #sound-dai-cells = <0>; 337*4882a593Smuzhiyun VDDA-supply = <®_3p2v>; 338*4882a593Smuzhiyun VDDIO-supply = <®_3p2v>; 339*4882a593Smuzhiyun clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>; 340*4882a593Smuzhiyun }; 341*4882a593Smuzhiyun}; 342*4882a593Smuzhiyun 343*4882a593Smuzhiyun&i2c1 { 344*4882a593Smuzhiyun pinctrl-names = "default"; 345*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c1>; 346*4882a593Smuzhiyun status = "okay"; 347*4882a593Smuzhiyun 348*4882a593Smuzhiyun accelerometer: mma8450@1c { 349*4882a593Smuzhiyun compatible = "fsl,mma8450"; 350*4882a593Smuzhiyun reg = <0x1c>; 351*4882a593Smuzhiyun }; 352*4882a593Smuzhiyun}; 353*4882a593Smuzhiyun 354*4882a593Smuzhiyun&audmux { 355*4882a593Smuzhiyun pinctrl-names = "default"; 356*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_audmux>; 357*4882a593Smuzhiyun status = "okay"; 358*4882a593Smuzhiyun}; 359*4882a593Smuzhiyun 360*4882a593Smuzhiyun&fec { 361*4882a593Smuzhiyun pinctrl-names = "default"; 362*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_fec>; 363*4882a593Smuzhiyun phy-mode = "rmii"; 364*4882a593Smuzhiyun phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; 365*4882a593Smuzhiyun status = "okay"; 366*4882a593Smuzhiyun}; 367*4882a593Smuzhiyun 368*4882a593Smuzhiyun&sata { 369*4882a593Smuzhiyun status = "okay"; 370*4882a593Smuzhiyun}; 371*4882a593Smuzhiyun 372*4882a593Smuzhiyun&vpu { 373*4882a593Smuzhiyun status = "okay"; 374*4882a593Smuzhiyun}; 375*4882a593Smuzhiyun 376*4882a593Smuzhiyun&usbh1 { 377*4882a593Smuzhiyun vbus-supply = <®_usb_vbus>; 378*4882a593Smuzhiyun phy_type = "utmi"; 379*4882a593Smuzhiyun status = "okay"; 380*4882a593Smuzhiyun}; 381*4882a593Smuzhiyun 382*4882a593Smuzhiyun&usbotg { 383*4882a593Smuzhiyun dr_mode = "peripheral"; 384*4882a593Smuzhiyun status = "okay"; 385*4882a593Smuzhiyun}; 386