xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/imx53-mba53.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
4*4882a593Smuzhiyun * Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>, Pengutronix
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun/dts-v1/;
8*4882a593Smuzhiyun#include "imx53-tqma53.dtsi"
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun/ {
11*4882a593Smuzhiyun	model = "TQ MBa53 starter kit";
12*4882a593Smuzhiyun	compatible = "tq,mba53", "tq,tqma53", "fsl,imx53";
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun	chosen {
15*4882a593Smuzhiyun		stdout-path = &uart2;
16*4882a593Smuzhiyun	};
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun	backlight {
19*4882a593Smuzhiyun		compatible = "pwm-backlight";
20*4882a593Smuzhiyun		pwms = <&pwm2 0 50000>;
21*4882a593Smuzhiyun		brightness-levels = <0 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100>;
22*4882a593Smuzhiyun		default-brightness-level = <10>;
23*4882a593Smuzhiyun		enable-gpios = <&gpio7 7 0>;
24*4882a593Smuzhiyun		power-supply = <&reg_backlight>;
25*4882a593Smuzhiyun	};
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun	disp1: disp1 {
28*4882a593Smuzhiyun		compatible = "fsl,imx-parallel-display";
29*4882a593Smuzhiyun		pinctrl-names = "default";
30*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_disp1_1>;
31*4882a593Smuzhiyun		interface-pix-fmt = "rgb24";
32*4882a593Smuzhiyun		status = "disabled";
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun		port {
35*4882a593Smuzhiyun			display1_in: endpoint {
36*4882a593Smuzhiyun				remote-endpoint = <&ipu_di1_disp1>;
37*4882a593Smuzhiyun			};
38*4882a593Smuzhiyun		};
39*4882a593Smuzhiyun	};
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun	regulators {
42*4882a593Smuzhiyun		compatible = "simple-bus";
43*4882a593Smuzhiyun		#address-cells = <1>;
44*4882a593Smuzhiyun		#size-cells = <0>;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun		reg_backlight: regulator@0 {
47*4882a593Smuzhiyun			compatible = "regulator-fixed";
48*4882a593Smuzhiyun			reg = <0>;
49*4882a593Smuzhiyun			regulator-name = "lcd-supply";
50*4882a593Smuzhiyun			gpio = <&gpio2 5 0>;
51*4882a593Smuzhiyun			startup-delay-us = <5000>;
52*4882a593Smuzhiyun		};
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun		reg_3p2v: regulator@1 {
55*4882a593Smuzhiyun			compatible = "regulator-fixed";
56*4882a593Smuzhiyun			reg = <1>;
57*4882a593Smuzhiyun			regulator-name = "3P2V";
58*4882a593Smuzhiyun			regulator-min-microvolt = <3200000>;
59*4882a593Smuzhiyun			regulator-max-microvolt = <3200000>;
60*4882a593Smuzhiyun			regulator-always-on;
61*4882a593Smuzhiyun		};
62*4882a593Smuzhiyun	};
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun	sound {
65*4882a593Smuzhiyun		compatible = "tq,imx53-mba53-sgtl5000",
66*4882a593Smuzhiyun			     "fsl,imx-audio-sgtl5000";
67*4882a593Smuzhiyun		model = "imx53-mba53-sgtl5000";
68*4882a593Smuzhiyun		ssi-controller = <&ssi2>;
69*4882a593Smuzhiyun		audio-codec = <&codec>;
70*4882a593Smuzhiyun		audio-routing =
71*4882a593Smuzhiyun			"MIC_IN", "Mic Jack",
72*4882a593Smuzhiyun			"Mic Jack", "Mic Bias",
73*4882a593Smuzhiyun			"Headphone Jack", "HP_OUT";
74*4882a593Smuzhiyun		mux-int-port = <2>;
75*4882a593Smuzhiyun		mux-ext-port = <5>;
76*4882a593Smuzhiyun	};
77*4882a593Smuzhiyun};
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun&ldb {
80*4882a593Smuzhiyun	pinctrl-names = "default";
81*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_lvds1_1>;
82*4882a593Smuzhiyun	status = "disabled";
83*4882a593Smuzhiyun};
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun&iomuxc {
86*4882a593Smuzhiyun	lvds1 {
87*4882a593Smuzhiyun		pinctrl_lvds1_1: lvds1-grp1 {
88*4882a593Smuzhiyun			fsl,pins = <
89*4882a593Smuzhiyun				MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
90*4882a593Smuzhiyun				MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
91*4882a593Smuzhiyun				MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
92*4882a593Smuzhiyun				MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
93*4882a593Smuzhiyun				MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
94*4882a593Smuzhiyun			>;
95*4882a593Smuzhiyun		};
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun		pinctrl_lvds1_2: lvds1-grp2 {
98*4882a593Smuzhiyun			fsl,pins = <
99*4882a593Smuzhiyun				MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000
100*4882a593Smuzhiyun				MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000
101*4882a593Smuzhiyun				MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000
102*4882a593Smuzhiyun				MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000
103*4882a593Smuzhiyun				MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000
104*4882a593Smuzhiyun			>;
105*4882a593Smuzhiyun		};
106*4882a593Smuzhiyun	};
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun	disp1 {
109*4882a593Smuzhiyun		pinctrl_disp1_1: disp1-grp1 {
110*4882a593Smuzhiyun			fsl,pins = <
111*4882a593Smuzhiyun				MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x80000000 /* DISP1_CLK */
112*4882a593Smuzhiyun				MX53_PAD_EIM_DA10__IPU_DI1_PIN15   0x80000000 /* DISP1_DRDY */
113*4882a593Smuzhiyun				MX53_PAD_EIM_D23__IPU_DI1_PIN2     0x80000000 /* DISP1_HSYNC */
114*4882a593Smuzhiyun				MX53_PAD_EIM_EB3__IPU_DI1_PIN3     0x80000000 /* DISP1_VSYNC */
115*4882a593Smuzhiyun				MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x80000000
116*4882a593Smuzhiyun				MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x80000000
117*4882a593Smuzhiyun				MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x80000000
118*4882a593Smuzhiyun				MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x80000000
119*4882a593Smuzhiyun				MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x80000000
120*4882a593Smuzhiyun				MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x80000000
121*4882a593Smuzhiyun				MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x80000000
122*4882a593Smuzhiyun				MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x80000000
123*4882a593Smuzhiyun				MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x80000000
124*4882a593Smuzhiyun				MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x80000000
125*4882a593Smuzhiyun				MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x80000000
126*4882a593Smuzhiyun				MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x80000000
127*4882a593Smuzhiyun				MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x80000000
128*4882a593Smuzhiyun				MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x80000000
129*4882a593Smuzhiyun				MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9  0x80000000
130*4882a593Smuzhiyun				MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8  0x80000000
131*4882a593Smuzhiyun				MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7  0x80000000
132*4882a593Smuzhiyun				MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6  0x80000000
133*4882a593Smuzhiyun				MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5  0x80000000
134*4882a593Smuzhiyun				MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4  0x80000000
135*4882a593Smuzhiyun				MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3  0x80000000
136*4882a593Smuzhiyun				MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2  0x80000000
137*4882a593Smuzhiyun				MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1  0x80000000
138*4882a593Smuzhiyun				MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0  0x80000000
139*4882a593Smuzhiyun			>;
140*4882a593Smuzhiyun		};
141*4882a593Smuzhiyun	};
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun	tve {
144*4882a593Smuzhiyun		pinctrl_vga_sync_1: vgasync-grp1 {
145*4882a593Smuzhiyun			fsl,pins = <
146*4882a593Smuzhiyun				/* VGA_VSYNC, HSYNC with max drive strength */
147*4882a593Smuzhiyun				MX53_PAD_EIM_CS1__IPU_DI1_PIN6	   0xe6
148*4882a593Smuzhiyun				MX53_PAD_EIM_DA15__IPU_DI1_PIN4	   0xe6
149*4882a593Smuzhiyun			>;
150*4882a593Smuzhiyun		};
151*4882a593Smuzhiyun	};
152*4882a593Smuzhiyun};
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun&ipu_di1_disp1 {
155*4882a593Smuzhiyun	remote-endpoint = <&display1_in>;
156*4882a593Smuzhiyun};
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun&cspi {
159*4882a593Smuzhiyun	status = "okay";
160*4882a593Smuzhiyun};
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun&audmux {
163*4882a593Smuzhiyun	status = "okay";
164*4882a593Smuzhiyun	pinctrl-names = "default";
165*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_audmux>;
166*4882a593Smuzhiyun};
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun&i2c2 {
169*4882a593Smuzhiyun	codec: sgtl5000@a {
170*4882a593Smuzhiyun		compatible = "fsl,sgtl5000";
171*4882a593Smuzhiyun		reg = <0x0a>;
172*4882a593Smuzhiyun		clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
173*4882a593Smuzhiyun		VDDA-supply = <&reg_3p2v>;
174*4882a593Smuzhiyun		VDDIO-supply = <&reg_3p2v>;
175*4882a593Smuzhiyun	};
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun	expander: pca9554@20 {
178*4882a593Smuzhiyun		compatible = "pca9554";
179*4882a593Smuzhiyun		reg = <0x20>;
180*4882a593Smuzhiyun		interrupts = <109>;
181*4882a593Smuzhiyun		#gpio-cells = <2>;
182*4882a593Smuzhiyun		gpio-controller;
183*4882a593Smuzhiyun	};
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun	sensor2: lm75@49 {
186*4882a593Smuzhiyun		compatible = "lm75";
187*4882a593Smuzhiyun		reg = <0x49>;
188*4882a593Smuzhiyun	};
189*4882a593Smuzhiyun};
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun&fec {
192*4882a593Smuzhiyun	phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
193*4882a593Smuzhiyun	status = "okay";
194*4882a593Smuzhiyun};
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun&esdhc2 {
197*4882a593Smuzhiyun	status = "okay";
198*4882a593Smuzhiyun};
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun&uart3 {
201*4882a593Smuzhiyun	status = "okay";
202*4882a593Smuzhiyun};
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun&ecspi1 {
205*4882a593Smuzhiyun	status = "okay";
206*4882a593Smuzhiyun};
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun&usbotg {
209*4882a593Smuzhiyun	dr_mode = "host";
210*4882a593Smuzhiyun	status = "okay";
211*4882a593Smuzhiyun};
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun&usbh1 {
214*4882a593Smuzhiyun	status = "okay";
215*4882a593Smuzhiyun};
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun&uart1 {
218*4882a593Smuzhiyun	status = "okay";
219*4882a593Smuzhiyun};
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun&ssi2 {
222*4882a593Smuzhiyun	status = "okay";
223*4882a593Smuzhiyun};
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun&uart2 {
226*4882a593Smuzhiyun	status = "okay";
227*4882a593Smuzhiyun};
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun&can1 {
230*4882a593Smuzhiyun	status = "okay";
231*4882a593Smuzhiyun};
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun&can2 {
234*4882a593Smuzhiyun	status = "okay";
235*4882a593Smuzhiyun};
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun&i2c3 {
238*4882a593Smuzhiyun	status = "okay";
239*4882a593Smuzhiyun};
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun&tve {
242*4882a593Smuzhiyun	pinctrl-names = "default";
243*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_vga_sync_1>;
244*4882a593Smuzhiyun	ddc-i2c-bus = <&i2c3>;
245*4882a593Smuzhiyun	fsl,tve-mode = "vga";
246*4882a593Smuzhiyun	fsl,hsync-pin = <4>;
247*4882a593Smuzhiyun	fsl,vsync-pin = <6>;
248*4882a593Smuzhiyun	status = "okay";
249*4882a593Smuzhiyun};
250