1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2019 Marek Vasut <marex@denx.de> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun#include "imx53-m53.dtsi" 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/ { 10*4882a593Smuzhiyun model = "MENLO M53 EMBEDDED DEVICE"; 11*4882a593Smuzhiyun compatible = "menlo,m53menlo", "fsl,imx53"; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun gpio-keys { 14*4882a593Smuzhiyun compatible = "gpio-keys"; 15*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_power_button>; 16*4882a593Smuzhiyun pinctrl-names = "default"; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun power-button { 19*4882a593Smuzhiyun label = "Power button"; 20*4882a593Smuzhiyun gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; 21*4882a593Smuzhiyun linux,code = <KEY_POWER>; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun gpio-poweroff { 26*4882a593Smuzhiyun compatible = "gpio-poweroff"; 27*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_power_out>; 28*4882a593Smuzhiyun pinctrl-names = "default"; 29*4882a593Smuzhiyun gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun leds { 33*4882a593Smuzhiyun compatible = "gpio-leds"; 34*4882a593Smuzhiyun pinctrl-names = "default"; 35*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_led>; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun user1 { 38*4882a593Smuzhiyun label = "TestLed601"; 39*4882a593Smuzhiyun gpios = <&gpio6 1 GPIO_ACTIVE_HIGH>; 40*4882a593Smuzhiyun linux,default-trigger = "mmc0"; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun user2 { 44*4882a593Smuzhiyun label = "TestLed602"; 45*4882a593Smuzhiyun gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; 46*4882a593Smuzhiyun linux,default-trigger = "heartbeat"; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun eth { 50*4882a593Smuzhiyun label = "EthLedYe"; 51*4882a593Smuzhiyun gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; 52*4882a593Smuzhiyun linux,default-trigger = "netdev"; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun lvds-decoder { 57*4882a593Smuzhiyun compatible = "ti,ds90cf364a", "lvds-decoder"; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun ports { 60*4882a593Smuzhiyun #address-cells = <1>; 61*4882a593Smuzhiyun #size-cells = <0>; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun port@0 { 64*4882a593Smuzhiyun reg = <0>; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun lvds_decoder_in: endpoint { 67*4882a593Smuzhiyun remote-endpoint = <&lvds0_out>; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun port@1 { 72*4882a593Smuzhiyun reg = <1>; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun lvds_decoder_out: endpoint { 75*4882a593Smuzhiyun remote-endpoint = <&panel_in>; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun panel { 82*4882a593Smuzhiyun compatible = "edt,etm0700g0dh6"; 83*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_display_gpio>; 84*4882a593Smuzhiyun pinctrl-names = "default"; 85*4882a593Smuzhiyun enable-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun port { 88*4882a593Smuzhiyun panel_in: endpoint { 89*4882a593Smuzhiyun remote-endpoint = <&lvds_decoder_out>; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun beeper { 95*4882a593Smuzhiyun compatible = "gpio-beeper"; 96*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_beeper>; 97*4882a593Smuzhiyun gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun reg_usbh1_vbus: regulator-usbh1-vbus { 101*4882a593Smuzhiyun compatible = "regulator-fixed"; 102*4882a593Smuzhiyun regulator-name = "vbus"; 103*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 104*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 105*4882a593Smuzhiyun gpio = <&gpio1 2 0>; 106*4882a593Smuzhiyun }; 107*4882a593Smuzhiyun}; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun&can1 { 110*4882a593Smuzhiyun pinctrl-names = "default"; 111*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_can1>; 112*4882a593Smuzhiyun status = "okay"; 113*4882a593Smuzhiyun}; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun&can2 { 116*4882a593Smuzhiyun pinctrl-names = "default"; 117*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_can2>; 118*4882a593Smuzhiyun status = "okay"; 119*4882a593Smuzhiyun}; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun&clks { 122*4882a593Smuzhiyun assigned-clocks = <&clks IMX5_CLK_CKO1_SEL>, 123*4882a593Smuzhiyun <&clks IMX5_CLK_CKO1_PODF>, 124*4882a593Smuzhiyun <&clks IMX5_CLK_CKO1>; 125*4882a593Smuzhiyun assigned-clock-parents = <&clks IMX5_CLK_AHB>; 126*4882a593Smuzhiyun assigned-clock-rates = <133333334>, <33333334>, <33333334>; 127*4882a593Smuzhiyun}; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun&ecspi2 { 130*4882a593Smuzhiyun pinctrl-names = "default"; 131*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_ecspi2>; 132*4882a593Smuzhiyun cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>, <&gpio2 27 GPIO_ACTIVE_LOW>; 133*4882a593Smuzhiyun status = "okay"; 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun spidev@0 { 136*4882a593Smuzhiyun compatible = "menlo,m53cpld"; 137*4882a593Smuzhiyun spi-max-frequency = <25000000>; 138*4882a593Smuzhiyun reg = <0>; 139*4882a593Smuzhiyun }; 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun spidev@1 { 142*4882a593Smuzhiyun compatible = "menlo,m53cpld"; 143*4882a593Smuzhiyun spi-max-frequency = <25000000>; 144*4882a593Smuzhiyun reg = <1>; 145*4882a593Smuzhiyun }; 146*4882a593Smuzhiyun}; 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun&esdhc1 { 149*4882a593Smuzhiyun pinctrl-names = "default"; 150*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_esdhc1>; 151*4882a593Smuzhiyun cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; 152*4882a593Smuzhiyun wp-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; 153*4882a593Smuzhiyun status = "okay"; 154*4882a593Smuzhiyun}; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun&fec { 157*4882a593Smuzhiyun pinctrl-names = "default"; 158*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_fec>; 159*4882a593Smuzhiyun phy-mode = "rmii"; 160*4882a593Smuzhiyun phy-reset-gpios = <&gpio7 7 GPIO_ACTIVE_LOW>; 161*4882a593Smuzhiyun status = "okay"; 162*4882a593Smuzhiyun}; 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun&gpio1 { 165*4882a593Smuzhiyun gpio-line-names = 166*4882a593Smuzhiyun "", "", "", "", 167*4882a593Smuzhiyun "", "", "", "", 168*4882a593Smuzhiyun "", "", "", "", 169*4882a593Smuzhiyun "", "", "", "", 170*4882a593Smuzhiyun "", "", "", "", 171*4882a593Smuzhiyun "", "", "", "", 172*4882a593Smuzhiyun "", "", "", "", 173*4882a593Smuzhiyun "", "", "", ""; 174*4882a593Smuzhiyun}; 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun&gpio2 { 177*4882a593Smuzhiyun gpio-line-names = 178*4882a593Smuzhiyun "", "", "", "", 179*4882a593Smuzhiyun "", "", "", "", 180*4882a593Smuzhiyun "TestPin_SV2_3", "", "", "", 181*4882a593Smuzhiyun "", "", "", "", 182*4882a593Smuzhiyun "", "", "", "", 183*4882a593Smuzhiyun "", "", "", "", 184*4882a593Smuzhiyun "", "", "", "", 185*4882a593Smuzhiyun "", "", "", ""; 186*4882a593Smuzhiyun}; 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun&gpio3 { 189*4882a593Smuzhiyun gpio-line-names = 190*4882a593Smuzhiyun "", "", "", "", 191*4882a593Smuzhiyun "", "", "", "", 192*4882a593Smuzhiyun "", "", "", "", 193*4882a593Smuzhiyun "", "", "", "", 194*4882a593Smuzhiyun "", "", "", "", 195*4882a593Smuzhiyun "", "", "", "", 196*4882a593Smuzhiyun "CPLD_JTAG_TDI", "CPLD_JTAG_TMS", "", "", 197*4882a593Smuzhiyun "", "CPLD_JTAG_TDO", "", ""; 198*4882a593Smuzhiyun}; 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun&gpio5 { 201*4882a593Smuzhiyun gpio-line-names = 202*4882a593Smuzhiyun "", "", "", "", 203*4882a593Smuzhiyun "", "", "", "", 204*4882a593Smuzhiyun "", "", "", "", 205*4882a593Smuzhiyun "", "", "", "", 206*4882a593Smuzhiyun "", "", "CPLD_JTAG_TCK", "KBD_intK", 207*4882a593Smuzhiyun "CPLD_int", "CPLD_JTAG_internal", "CPLD_D[0]", "CPLD_D[1]", 208*4882a593Smuzhiyun "CPLD_D[2]", "CPLD_D[3]", "CPLD_D[4]", "CPLD_D[5]", 209*4882a593Smuzhiyun "CPLD_D[6]", "CPLD_D[7]", "DISP_reset", "KBD_intI"; 210*4882a593Smuzhiyun}; 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun&gpio6 { 213*4882a593Smuzhiyun gpio-line-names = 214*4882a593Smuzhiyun "", "", "", "", 215*4882a593Smuzhiyun "CPLD_reset", "", "", "", 216*4882a593Smuzhiyun "", "", "", "", 217*4882a593Smuzhiyun "", "", "", "", 218*4882a593Smuzhiyun "", "", "", "", 219*4882a593Smuzhiyun "", "", "", "", 220*4882a593Smuzhiyun "", "", "", "", 221*4882a593Smuzhiyun "", "", "", ""; 222*4882a593Smuzhiyun}; 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun&gpio7 { 225*4882a593Smuzhiyun gpio-line-names = 226*4882a593Smuzhiyun "", "", "", "", 227*4882a593Smuzhiyun "", "", "", "", 228*4882a593Smuzhiyun "", "", "", "", 229*4882a593Smuzhiyun "", "USB-OTG_OverCurrent", "", "", 230*4882a593Smuzhiyun "", "", "", "", 231*4882a593Smuzhiyun "", "", "", "", 232*4882a593Smuzhiyun "", "", "", "", 233*4882a593Smuzhiyun "", "", "", ""; 234*4882a593Smuzhiyun}; 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun&i2c1 { 237*4882a593Smuzhiyun pinctrl-names = "default"; 238*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c1>; 239*4882a593Smuzhiyun status = "okay"; 240*4882a593Smuzhiyun 241*4882a593Smuzhiyun touchscreen@38 { 242*4882a593Smuzhiyun compatible = "edt,edt-ft5x06"; 243*4882a593Smuzhiyun reg = <0x38>; 244*4882a593Smuzhiyun pinctrl-names = "default"; 245*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_edt_ft5x06>; 246*4882a593Smuzhiyun interrupt-parent = <&gpio6>; 247*4882a593Smuzhiyun interrupts = <5 IRQ_TYPE_EDGE_FALLING>; 248*4882a593Smuzhiyun reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; 249*4882a593Smuzhiyun wake-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; 250*4882a593Smuzhiyun }; 251*4882a593Smuzhiyun 252*4882a593Smuzhiyun eeprom@50 { 253*4882a593Smuzhiyun compatible = "atmel,24c64"; 254*4882a593Smuzhiyun reg = <0x50>; 255*4882a593Smuzhiyun pagesize = <32>; 256*4882a593Smuzhiyun }; 257*4882a593Smuzhiyun 258*4882a593Smuzhiyun dac@60 { 259*4882a593Smuzhiyun compatible = "microchip,mcp4725"; 260*4882a593Smuzhiyun reg = <0x60>; 261*4882a593Smuzhiyun }; 262*4882a593Smuzhiyun}; 263*4882a593Smuzhiyun 264*4882a593Smuzhiyun&i2c2 { 265*4882a593Smuzhiyun touchscreen@41 { 266*4882a593Smuzhiyun status = "disabled"; 267*4882a593Smuzhiyun }; 268*4882a593Smuzhiyun}; 269*4882a593Smuzhiyun 270*4882a593Smuzhiyun&i2c3 { 271*4882a593Smuzhiyun pinctrl-names = "default"; 272*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c3>; 273*4882a593Smuzhiyun status = "okay"; 274*4882a593Smuzhiyun}; 275*4882a593Smuzhiyun 276*4882a593Smuzhiyun&iomuxc { 277*4882a593Smuzhiyun pinctrl-names = "default"; 278*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_hog>; 279*4882a593Smuzhiyun 280*4882a593Smuzhiyun imx53-m53evk { 281*4882a593Smuzhiyun hoggrp { 282*4882a593Smuzhiyun fsl,pins = < 283*4882a593Smuzhiyun MX53_PAD_GPIO_19__CCM_CLKO 0x1e4 284*4882a593Smuzhiyun MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x1e4 285*4882a593Smuzhiyun MX53_PAD_CSI0_DAT4__GPIO5_22 0x1e4 286*4882a593Smuzhiyun MX53_PAD_CSI0_DAT5__GPIO5_23 0x1c4 287*4882a593Smuzhiyun MX53_PAD_CSI0_DAT6__GPIO5_24 0x1e4 288*4882a593Smuzhiyun MX53_PAD_CSI0_DAT7__GPIO5_25 0x1e4 289*4882a593Smuzhiyun MX53_PAD_CSI0_DAT8__GPIO5_26 0x1e4 290*4882a593Smuzhiyun MX53_PAD_CSI0_DAT9__GPIO5_27 0x1c4 291*4882a593Smuzhiyun MX53_PAD_CSI0_DAT10__GPIO5_28 0x1e4 292*4882a593Smuzhiyun MX53_PAD_CSI0_DAT11__GPIO5_29 0x1e4 293*4882a593Smuzhiyun MX53_PAD_PATA_DATA11__GPIO2_11 0x1e4 294*4882a593Smuzhiyun MX53_PAD_EIM_D24__GPIO3_24 0x1e4 295*4882a593Smuzhiyun MX53_PAD_EIM_D25__GPIO3_25 0x1e4 296*4882a593Smuzhiyun MX53_PAD_EIM_D29__GPIO3_29 0x1e4 297*4882a593Smuzhiyun MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x1e4 298*4882a593Smuzhiyun MX53_PAD_CSI0_VSYNC__GPIO5_21 0x1e4 299*4882a593Smuzhiyun MX53_PAD_CSI0_DAT18__GPIO6_4 0x1c4 300*4882a593Smuzhiyun MX53_PAD_PATA_DATA8__GPIO2_8 0x1e4 301*4882a593Smuzhiyun >; 302*4882a593Smuzhiyun }; 303*4882a593Smuzhiyun 304*4882a593Smuzhiyun pinctrl_led: ledgrp { 305*4882a593Smuzhiyun fsl,pins = < 306*4882a593Smuzhiyun MX53_PAD_CSI0_DAT15__GPIO6_1 0x1c4 307*4882a593Smuzhiyun MX53_PAD_CSI0_DAT16__GPIO6_2 0x1c4 308*4882a593Smuzhiyun >; 309*4882a593Smuzhiyun }; 310*4882a593Smuzhiyun 311*4882a593Smuzhiyun pinctrl_beeper: beepergrp { 312*4882a593Smuzhiyun fsl,pins = < 313*4882a593Smuzhiyun MX53_PAD_CSI0_DAT17__GPIO6_3 0x1c4 314*4882a593Smuzhiyun >; 315*4882a593Smuzhiyun }; 316*4882a593Smuzhiyun 317*4882a593Smuzhiyun pinctrl_can1: can1grp { 318*4882a593Smuzhiyun fsl,pins = < 319*4882a593Smuzhiyun MX53_PAD_GPIO_7__CAN1_TXCAN 0x1c4 320*4882a593Smuzhiyun MX53_PAD_GPIO_8__CAN1_RXCAN 0x1c4 321*4882a593Smuzhiyun >; 322*4882a593Smuzhiyun }; 323*4882a593Smuzhiyun 324*4882a593Smuzhiyun pinctrl_can2: can2grp { 325*4882a593Smuzhiyun fsl,pins = < 326*4882a593Smuzhiyun MX53_PAD_KEY_COL4__CAN2_TXCAN 0x1e4 327*4882a593Smuzhiyun MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x1c4 328*4882a593Smuzhiyun >; 329*4882a593Smuzhiyun }; 330*4882a593Smuzhiyun 331*4882a593Smuzhiyun pinctrl_display_gpio: display-gpiogrp { 332*4882a593Smuzhiyun fsl,pins = < 333*4882a593Smuzhiyun MX53_PAD_CSI0_DAT12__GPIO5_30 0x1c4 /* Reset */ 334*4882a593Smuzhiyun MX53_PAD_CSI0_MCLK__GPIO5_19 0x1e4 /* Int-K */ 335*4882a593Smuzhiyun MX53_PAD_CSI0_DAT13__GPIO5_31 0x1c4 /* Int-I */ 336*4882a593Smuzhiyun 337*4882a593Smuzhiyun MX53_PAD_CSI0_DAT14__GPIO6_0 0x1c4 /* Power down */ 338*4882a593Smuzhiyun >; 339*4882a593Smuzhiyun }; 340*4882a593Smuzhiyun 341*4882a593Smuzhiyun pinctrl_edt_ft5x06: edt-ft5x06grp { 342*4882a593Smuzhiyun fsl,pins = < 343*4882a593Smuzhiyun MX53_PAD_PATA_DATA9__GPIO2_9 0x1e4 /* Reset */ 344*4882a593Smuzhiyun MX53_PAD_CSI0_DAT19__GPIO6_5 0x1c4 /* Interrupt */ 345*4882a593Smuzhiyun MX53_PAD_PATA_DATA10__GPIO2_10 0x1e4 /* Wake */ 346*4882a593Smuzhiyun >; 347*4882a593Smuzhiyun }; 348*4882a593Smuzhiyun 349*4882a593Smuzhiyun pinctrl_ecspi2: ecspi2grp { 350*4882a593Smuzhiyun fsl,pins = < 351*4882a593Smuzhiyun MX53_PAD_EIM_CS0__ECSPI2_SCLK 0xe4 352*4882a593Smuzhiyun MX53_PAD_EIM_OE__ECSPI2_MISO 0xe4 353*4882a593Smuzhiyun MX53_PAD_EIM_CS1__ECSPI2_MOSI 0xe4 354*4882a593Smuzhiyun MX53_PAD_EIM_RW__GPIO2_26 0xe4 355*4882a593Smuzhiyun MX53_PAD_EIM_LBA__GPIO2_27 0xe4 356*4882a593Smuzhiyun >; 357*4882a593Smuzhiyun }; 358*4882a593Smuzhiyun 359*4882a593Smuzhiyun pinctrl_esdhc1: esdhc1grp { 360*4882a593Smuzhiyun fsl,pins = < 361*4882a593Smuzhiyun MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1e4 362*4882a593Smuzhiyun MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1e4 363*4882a593Smuzhiyun MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1e4 364*4882a593Smuzhiyun MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1e4 365*4882a593Smuzhiyun MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1e4 366*4882a593Smuzhiyun MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1e4 367*4882a593Smuzhiyun MX53_PAD_GPIO_1__GPIO1_1 0x1c4 368*4882a593Smuzhiyun MX53_PAD_GPIO_9__GPIO1_9 0x1e4 369*4882a593Smuzhiyun >; 370*4882a593Smuzhiyun }; 371*4882a593Smuzhiyun 372*4882a593Smuzhiyun pinctrl_fec: fecgrp { 373*4882a593Smuzhiyun fsl,pins = < 374*4882a593Smuzhiyun MX53_PAD_FEC_MDC__FEC_MDC 0x1e4 375*4882a593Smuzhiyun MX53_PAD_FEC_MDIO__FEC_MDIO 0x1e4 376*4882a593Smuzhiyun MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x1e4 377*4882a593Smuzhiyun MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x1e4 378*4882a593Smuzhiyun MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x1e4 379*4882a593Smuzhiyun MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x1e4 380*4882a593Smuzhiyun MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x1e4 381*4882a593Smuzhiyun MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x1c4 382*4882a593Smuzhiyun MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x1e4 383*4882a593Smuzhiyun MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x1e4 384*4882a593Smuzhiyun MX53_PAD_PATA_DA_1__GPIO7_7 0x1e4 385*4882a593Smuzhiyun MX53_PAD_EIM_EB3__GPIO2_31 0x1e4 386*4882a593Smuzhiyun >; 387*4882a593Smuzhiyun }; 388*4882a593Smuzhiyun 389*4882a593Smuzhiyun pinctrl_i2c1: i2c1grp { 390*4882a593Smuzhiyun fsl,pins = < 391*4882a593Smuzhiyun MX53_PAD_EIM_D21__I2C1_SCL 0x400001e4 392*4882a593Smuzhiyun MX53_PAD_EIM_D28__I2C1_SDA 0x400001e4 393*4882a593Smuzhiyun >; 394*4882a593Smuzhiyun }; 395*4882a593Smuzhiyun 396*4882a593Smuzhiyun pinctrl_i2c3: i2c3grp { 397*4882a593Smuzhiyun fsl,pins = < 398*4882a593Smuzhiyun MX53_PAD_GPIO_6__I2C3_SDA 0x400001e4 399*4882a593Smuzhiyun MX53_PAD_GPIO_5__I2C3_SCL 0x400001e4 400*4882a593Smuzhiyun >; 401*4882a593Smuzhiyun }; 402*4882a593Smuzhiyun 403*4882a593Smuzhiyun pinctrl_lvds0: lvds0grp { 404*4882a593Smuzhiyun /* LVDS pins only have pin mux configuration */ 405*4882a593Smuzhiyun fsl,pins = < 406*4882a593Smuzhiyun MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000 407*4882a593Smuzhiyun MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000 408*4882a593Smuzhiyun MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000 409*4882a593Smuzhiyun MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000 410*4882a593Smuzhiyun MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 411*4882a593Smuzhiyun >; 412*4882a593Smuzhiyun }; 413*4882a593Smuzhiyun 414*4882a593Smuzhiyun pinctrl_power_button: powerbutgrp { 415*4882a593Smuzhiyun fsl,pins = < 416*4882a593Smuzhiyun MX53_PAD_SD2_DATA0__GPIO1_15 0x1e4 417*4882a593Smuzhiyun >; 418*4882a593Smuzhiyun }; 419*4882a593Smuzhiyun 420*4882a593Smuzhiyun pinctrl_power_out: poweroutgrp { 421*4882a593Smuzhiyun fsl,pins = < 422*4882a593Smuzhiyun MX53_PAD_SD2_DATA2__GPIO1_13 0x1e4 423*4882a593Smuzhiyun >; 424*4882a593Smuzhiyun }; 425*4882a593Smuzhiyun 426*4882a593Smuzhiyun pinctrl_uart1: uart1grp { 427*4882a593Smuzhiyun fsl,pins = < 428*4882a593Smuzhiyun MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 429*4882a593Smuzhiyun MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 430*4882a593Smuzhiyun MX53_PAD_PATA_IORDY__UART1_RTS 0x1e4 431*4882a593Smuzhiyun MX53_PAD_PATA_RESET_B__UART1_CTS 0x1e4 432*4882a593Smuzhiyun >; 433*4882a593Smuzhiyun }; 434*4882a593Smuzhiyun 435*4882a593Smuzhiyun pinctrl_uart2: uart2grp { 436*4882a593Smuzhiyun fsl,pins = < 437*4882a593Smuzhiyun MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 438*4882a593Smuzhiyun MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 439*4882a593Smuzhiyun MX53_PAD_PATA_DIOR__UART2_RTS 0x1e4 440*4882a593Smuzhiyun MX53_PAD_PATA_INTRQ__UART2_CTS 0x1e4 441*4882a593Smuzhiyun >; 442*4882a593Smuzhiyun }; 443*4882a593Smuzhiyun 444*4882a593Smuzhiyun pinctrl_uart3: uart3grp { 445*4882a593Smuzhiyun fsl,pins = < 446*4882a593Smuzhiyun MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 447*4882a593Smuzhiyun MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 448*4882a593Smuzhiyun MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4 449*4882a593Smuzhiyun >; 450*4882a593Smuzhiyun }; 451*4882a593Smuzhiyun 452*4882a593Smuzhiyun pinctrl_usb: usbgrp { 453*4882a593Smuzhiyun fsl,pins = < 454*4882a593Smuzhiyun MX53_PAD_GPIO_2__GPIO1_2 0x1c4 455*4882a593Smuzhiyun MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x1c4 456*4882a593Smuzhiyun MX53_PAD_GPIO_4__GPIO1_4 0x1c4 457*4882a593Smuzhiyun MX53_PAD_GPIO_18__GPIO7_13 0x1c4 458*4882a593Smuzhiyun >; 459*4882a593Smuzhiyun }; 460*4882a593Smuzhiyun }; 461*4882a593Smuzhiyun}; 462*4882a593Smuzhiyun 463*4882a593Smuzhiyun&ldb { 464*4882a593Smuzhiyun pinctrl-names = "default"; 465*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_lvds0>; 466*4882a593Smuzhiyun status = "okay"; 467*4882a593Smuzhiyun 468*4882a593Smuzhiyun lvds0: lvds-channel@0 { 469*4882a593Smuzhiyun reg = <0>; 470*4882a593Smuzhiyun fsl,data-mapping = "spwg"; 471*4882a593Smuzhiyun fsl,data-width = <18>; 472*4882a593Smuzhiyun status = "okay"; 473*4882a593Smuzhiyun 474*4882a593Smuzhiyun port@2 { 475*4882a593Smuzhiyun reg = <2>; 476*4882a593Smuzhiyun 477*4882a593Smuzhiyun lvds0_out: endpoint { 478*4882a593Smuzhiyun remote-endpoint = <&lvds_decoder_in>; 479*4882a593Smuzhiyun }; 480*4882a593Smuzhiyun }; 481*4882a593Smuzhiyun }; 482*4882a593Smuzhiyun}; 483*4882a593Smuzhiyun 484*4882a593Smuzhiyun&uart1 { 485*4882a593Smuzhiyun pinctrl-names = "default"; 486*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart1>; 487*4882a593Smuzhiyun uart-has-rtscts; 488*4882a593Smuzhiyun status = "okay"; 489*4882a593Smuzhiyun}; 490*4882a593Smuzhiyun 491*4882a593Smuzhiyun&uart2 { 492*4882a593Smuzhiyun pinctrl-names = "default"; 493*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart2>; 494*4882a593Smuzhiyun uart-has-rtscts; 495*4882a593Smuzhiyun status = "okay"; 496*4882a593Smuzhiyun}; 497*4882a593Smuzhiyun 498*4882a593Smuzhiyun&uart3 { 499*4882a593Smuzhiyun pinctrl-names = "default"; 500*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart3>; 501*4882a593Smuzhiyun linux,rs485-enabled-at-boot-time; 502*4882a593Smuzhiyun status = "okay"; 503*4882a593Smuzhiyun}; 504*4882a593Smuzhiyun 505*4882a593Smuzhiyun&usbh1 { 506*4882a593Smuzhiyun pinctrl-names = "default"; 507*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usb>; 508*4882a593Smuzhiyun vbus-supply = <®_usbh1_vbus>; 509*4882a593Smuzhiyun phy_type = "utmi"; 510*4882a593Smuzhiyun dr_mode = "host"; 511*4882a593Smuzhiyun status = "okay"; 512*4882a593Smuzhiyun}; 513*4882a593Smuzhiyun 514*4882a593Smuzhiyun&usbotg { 515*4882a593Smuzhiyun dr_mode = "peripheral"; 516*4882a593Smuzhiyun status = "okay"; 517*4882a593Smuzhiyun}; 518