1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright 2018 4*4882a593Smuzhiyun * Lukasz Majewski, DENX Software Engineering, lukma@denx.de 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/dts-v1/; 8*4882a593Smuzhiyun#include "imx53-kp.dtsi" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun model = "K+P imx53 DDC"; 12*4882a593Smuzhiyun compatible = "kiebackpeter,imx53-ddc", "fsl,imx53"; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun backlight_lcd: backlight { 15*4882a593Smuzhiyun compatible = "pwm-backlight"; 16*4882a593Smuzhiyun pwms = <&pwm2 0 50000>; 17*4882a593Smuzhiyun power-supply = <®_backlight>; 18*4882a593Smuzhiyun brightness-levels = <0 24 28 32 36 19*4882a593Smuzhiyun 40 44 48 52 56 20*4882a593Smuzhiyun 60 64 68 72 76 21*4882a593Smuzhiyun 80 84 88 92 96 100>; 22*4882a593Smuzhiyun default-brightness-level = <20>; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun lcd_display: display { 26*4882a593Smuzhiyun compatible = "fsl,imx-parallel-display"; 27*4882a593Smuzhiyun #address-cells = <1>; 28*4882a593Smuzhiyun #size-cells = <0>; 29*4882a593Smuzhiyun interface-pix-fmt = "rgb24"; 30*4882a593Smuzhiyun pinctrl-names = "default"; 31*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_disp>; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun port@0 { 34*4882a593Smuzhiyun reg = <0>; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun display1_in: endpoint { 37*4882a593Smuzhiyun remote-endpoint = <&ipu_di1_disp1>; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun port@1 { 42*4882a593Smuzhiyun reg = <1>; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun lcd_display_out: endpoint { 45*4882a593Smuzhiyun remote-endpoint = <&lcd_panel_in>; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun lcd_panel: lcd-panel { 51*4882a593Smuzhiyun compatible = "koe,tx14d24vm1bpa"; 52*4882a593Smuzhiyun backlight = <&backlight_lcd>; 53*4882a593Smuzhiyun power-supply = <®_3v3>; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun port { 56*4882a593Smuzhiyun lcd_panel_in: endpoint { 57*4882a593Smuzhiyun remote-endpoint = <&lcd_display_out>; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun reg_backlight: regulator-backlight { 63*4882a593Smuzhiyun compatible = "regulator-fixed"; 64*4882a593Smuzhiyun regulator-name = "backlight-supply"; 65*4882a593Smuzhiyun regulator-min-microvolt = <15000000>; 66*4882a593Smuzhiyun regulator-max-microvolt = <15000000>; 67*4882a593Smuzhiyun regulator-always-on; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun}; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun&fec { 72*4882a593Smuzhiyun status = "okay"; 73*4882a593Smuzhiyun}; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun&i2c3 { 76*4882a593Smuzhiyun adc@48 { 77*4882a593Smuzhiyun compatible = "ti,ads1015"; 78*4882a593Smuzhiyun reg = <0x48>; 79*4882a593Smuzhiyun #address-cells = <1>; 80*4882a593Smuzhiyun #size-cells = <0>; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun channel@4 { 83*4882a593Smuzhiyun reg = <4>; 84*4882a593Smuzhiyun ti,gain = <2>; 85*4882a593Smuzhiyun ti,datarate = <4>; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun channel@6 { 89*4882a593Smuzhiyun reg = <6>; 90*4882a593Smuzhiyun ti,gain = <2>; 91*4882a593Smuzhiyun ti,datarate = <4>; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun gpio-expander2@21 { 96*4882a593Smuzhiyun compatible = "nxp,pcf8574"; 97*4882a593Smuzhiyun reg = <0x21>; 98*4882a593Smuzhiyun interrupts = <109>; 99*4882a593Smuzhiyun #gpio-cells = <2>; 100*4882a593Smuzhiyun gpio-controller; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun}; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun&iomuxc { 105*4882a593Smuzhiyun imx53-kp-ddc { 106*4882a593Smuzhiyun pinctrl_disp: dispgrp { 107*4882a593Smuzhiyun fsl,pins = < 108*4882a593Smuzhiyun MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x4 109*4882a593Smuzhiyun MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x4 110*4882a593Smuzhiyun MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x4 111*4882a593Smuzhiyun MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x4 112*4882a593Smuzhiyun MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x4 113*4882a593Smuzhiyun MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x4 114*4882a593Smuzhiyun MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x4 115*4882a593Smuzhiyun MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x4 116*4882a593Smuzhiyun MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x4 117*4882a593Smuzhiyun MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x4 118*4882a593Smuzhiyun MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x4 119*4882a593Smuzhiyun MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x4 120*4882a593Smuzhiyun MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x4 121*4882a593Smuzhiyun MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x4 122*4882a593Smuzhiyun MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x4 123*4882a593Smuzhiyun MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x4 124*4882a593Smuzhiyun MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x4 125*4882a593Smuzhiyun MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x4 126*4882a593Smuzhiyun MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x4 127*4882a593Smuzhiyun MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x4 128*4882a593Smuzhiyun MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x4 129*4882a593Smuzhiyun MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x4 130*4882a593Smuzhiyun MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x4 131*4882a593Smuzhiyun MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x4 132*4882a593Smuzhiyun MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x4 133*4882a593Smuzhiyun MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x4 134*4882a593Smuzhiyun MX53_PAD_GPIO_1__PWM2_PWMO 0x4 135*4882a593Smuzhiyun >; 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun }; 138*4882a593Smuzhiyun}; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun&ipu_di1_disp1 { 141*4882a593Smuzhiyun remote-endpoint = <&display1_in>; 142*4882a593Smuzhiyun}; 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun&pmic { 145*4882a593Smuzhiyun fsl,mc13xxx-uses-touch; 146*4882a593Smuzhiyun}; 147