1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright 2017 Beckhoff Automation GmbH & Co. KG 4*4882a593Smuzhiyun * based on imx53-qsb.dts 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/dts-v1/; 8*4882a593Smuzhiyun#include "imx53.dtsi" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun model = "Beckhoff CX9020 Embedded PC"; 12*4882a593Smuzhiyun compatible = "bhf,cx9020", "fsl,imx53"; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun chosen { 15*4882a593Smuzhiyun stdout-path = &uart2; 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun memory@70000000 { 19*4882a593Smuzhiyun device_type = "memory"; 20*4882a593Smuzhiyun reg = <0x70000000 0x20000000>, 21*4882a593Smuzhiyun <0xb0000000 0x20000000>; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun display-0 { 25*4882a593Smuzhiyun #address-cells =<1>; 26*4882a593Smuzhiyun #size-cells = <0>; 27*4882a593Smuzhiyun compatible = "fsl,imx-parallel-display"; 28*4882a593Smuzhiyun interface-pix-fmt = "rgb24"; 29*4882a593Smuzhiyun pinctrl-names = "default"; 30*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_ipu_disp0>; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun port@0 { 33*4882a593Smuzhiyun reg = <0>; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun display0_in: endpoint { 36*4882a593Smuzhiyun remote-endpoint = <&ipu_di0_disp0>; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun port@1 { 41*4882a593Smuzhiyun reg = <1>; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun display0_out: endpoint { 44*4882a593Smuzhiyun remote-endpoint = <&tfp410_in>; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun dvi-connector { 50*4882a593Smuzhiyun compatible = "dvi-connector"; 51*4882a593Smuzhiyun ddc-i2c-bus = <&i2c2>; 52*4882a593Smuzhiyun digital; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun port { 55*4882a593Smuzhiyun dvi_connector_in: endpoint { 56*4882a593Smuzhiyun remote-endpoint = <&tfp410_out>; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun dvi-converter { 62*4882a593Smuzhiyun compatible = "ti,tfp410"; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun ports { 65*4882a593Smuzhiyun #address-cells = <1>; 66*4882a593Smuzhiyun #size-cells = <0>; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun port@0 { 69*4882a593Smuzhiyun reg = <0>; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun tfp410_in: endpoint { 72*4882a593Smuzhiyun remote-endpoint = <&display0_out>; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun port@1 { 77*4882a593Smuzhiyun reg = <1>; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun tfp410_out: endpoint { 80*4882a593Smuzhiyun remote-endpoint = <&dvi_connector_in>; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun leds { 87*4882a593Smuzhiyun compatible = "gpio-leds"; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun pwr-r { 90*4882a593Smuzhiyun gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; 91*4882a593Smuzhiyun default-state = "off"; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun pwr-g { 95*4882a593Smuzhiyun gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; 96*4882a593Smuzhiyun default-state = "on"; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun pwr-b { 100*4882a593Smuzhiyun gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; 101*4882a593Smuzhiyun default-state = "off"; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun sd1-b { 105*4882a593Smuzhiyun linux,default-trigger = "mmc0"; 106*4882a593Smuzhiyun gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun sd2-b { 110*4882a593Smuzhiyun linux,default-trigger = "mmc1"; 111*4882a593Smuzhiyun gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun regulator-3p2v { 116*4882a593Smuzhiyun compatible = "regulator-fixed"; 117*4882a593Smuzhiyun regulator-name = "3P2V"; 118*4882a593Smuzhiyun regulator-min-microvolt = <3200000>; 119*4882a593Smuzhiyun regulator-max-microvolt = <3200000>; 120*4882a593Smuzhiyun regulator-always-on; 121*4882a593Smuzhiyun }; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun reg_usb_vbus: regulator-vbus { 124*4882a593Smuzhiyun compatible = "regulator-fixed"; 125*4882a593Smuzhiyun regulator-name = "usb_vbus"; 126*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 127*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 128*4882a593Smuzhiyun gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>; 129*4882a593Smuzhiyun enable-active-high; 130*4882a593Smuzhiyun }; 131*4882a593Smuzhiyun}; 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun&esdhc1 { 134*4882a593Smuzhiyun pinctrl-names = "default"; 135*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_esdhc1>; 136*4882a593Smuzhiyun cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; 137*4882a593Smuzhiyun bus-width = <4>; 138*4882a593Smuzhiyun status = "okay"; 139*4882a593Smuzhiyun}; 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun&esdhc2 { 142*4882a593Smuzhiyun pinctrl-names = "default"; 143*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_esdhc2>; 144*4882a593Smuzhiyun cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; 145*4882a593Smuzhiyun bus-width = <4>; 146*4882a593Smuzhiyun status = "okay"; 147*4882a593Smuzhiyun}; 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun&fec { 150*4882a593Smuzhiyun pinctrl-names = "default"; 151*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_fec>; 152*4882a593Smuzhiyun phy-mode = "rmii"; 153*4882a593Smuzhiyun phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; 154*4882a593Smuzhiyun status = "okay"; 155*4882a593Smuzhiyun}; 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun&i2c2 { 158*4882a593Smuzhiyun pinctrl-names = "default"; 159*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c2>; 160*4882a593Smuzhiyun status = "okay"; 161*4882a593Smuzhiyun}; 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun&ipu_di0_disp0 { 164*4882a593Smuzhiyun remote-endpoint = <&display0_in>; 165*4882a593Smuzhiyun}; 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun&uart2 { 168*4882a593Smuzhiyun pinctrl-names = "default"; 169*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart2>; 170*4882a593Smuzhiyun fsl,dte-mode; 171*4882a593Smuzhiyun status = "okay"; 172*4882a593Smuzhiyun}; 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun&usbh1 { 175*4882a593Smuzhiyun vbus-supply = <®_usb_vbus>; 176*4882a593Smuzhiyun phy_type = "utmi"; 177*4882a593Smuzhiyun status = "okay"; 178*4882a593Smuzhiyun}; 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun&usbotg { 181*4882a593Smuzhiyun dr_mode = "peripheral"; 182*4882a593Smuzhiyun status = "okay"; 183*4882a593Smuzhiyun}; 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun&vpu { 186*4882a593Smuzhiyun status = "okay"; 187*4882a593Smuzhiyun}; 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun&iomuxc { 190*4882a593Smuzhiyun pinctrl-names = "default"; 191*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_hog>; 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun pinctrl_hog: hoggrp { 194*4882a593Smuzhiyun fsl,pins = < 195*4882a593Smuzhiyun MX53_PAD_GPIO_0__CCM_CLKO 0x1c4 196*4882a593Smuzhiyun MX53_PAD_GPIO_16__I2C3_SDA 0x1c4 197*4882a593Smuzhiyun MX53_PAD_EIM_D22__GPIO3_22 0x1c4 198*4882a593Smuzhiyun MX53_PAD_EIM_D23__GPIO3_23 0x1e4 199*4882a593Smuzhiyun MX53_PAD_EIM_D24__GPIO3_24 0x1e4 200*4882a593Smuzhiyun >; 201*4882a593Smuzhiyun }; 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun pinctrl_esdhc1: esdhc1grp { 204*4882a593Smuzhiyun fsl,pins = < 205*4882a593Smuzhiyun MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 206*4882a593Smuzhiyun MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 207*4882a593Smuzhiyun MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 208*4882a593Smuzhiyun MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 209*4882a593Smuzhiyun MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 210*4882a593Smuzhiyun MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 211*4882a593Smuzhiyun MX53_PAD_GPIO_1__ESDHC1_CD 0x1c4 212*4882a593Smuzhiyun MX53_PAD_EIM_D17__GPIO3_17 0x1e4 213*4882a593Smuzhiyun MX53_PAD_GPIO_3__GPIO1_3 0x1c4 214*4882a593Smuzhiyun >; 215*4882a593Smuzhiyun }; 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun pinctrl_esdhc2: esdhc2grp { 218*4882a593Smuzhiyun fsl,pins = < 219*4882a593Smuzhiyun MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 220*4882a593Smuzhiyun MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 221*4882a593Smuzhiyun MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 222*4882a593Smuzhiyun MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 223*4882a593Smuzhiyun MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 224*4882a593Smuzhiyun MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 225*4882a593Smuzhiyun MX53_PAD_GPIO_4__ESDHC2_CD 0x1e4 226*4882a593Smuzhiyun MX53_PAD_EIM_D20__GPIO3_20 0x1e4 227*4882a593Smuzhiyun MX53_PAD_GPIO_8__GPIO1_8 0x1c4 228*4882a593Smuzhiyun >; 229*4882a593Smuzhiyun }; 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun pinctrl_fec: fecgrp { 232*4882a593Smuzhiyun fsl,pins = < 233*4882a593Smuzhiyun MX53_PAD_FEC_MDC__FEC_MDC 0x4 234*4882a593Smuzhiyun MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc 235*4882a593Smuzhiyun MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180 236*4882a593Smuzhiyun MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180 237*4882a593Smuzhiyun MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180 238*4882a593Smuzhiyun MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180 239*4882a593Smuzhiyun MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180 240*4882a593Smuzhiyun MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4 241*4882a593Smuzhiyun MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4 242*4882a593Smuzhiyun MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4 243*4882a593Smuzhiyun >; 244*4882a593Smuzhiyun }; 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun pinctrl_i2c2: i2c2grp { 247*4882a593Smuzhiyun fsl,pins = < 248*4882a593Smuzhiyun MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 249*4882a593Smuzhiyun MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 250*4882a593Smuzhiyun >; 251*4882a593Smuzhiyun }; 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun pinctrl_ipu_disp0: ipudisp0grp { 254*4882a593Smuzhiyun fsl,pins = < 255*4882a593Smuzhiyun MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5 256*4882a593Smuzhiyun MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5 257*4882a593Smuzhiyun MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5 258*4882a593Smuzhiyun MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5 259*4882a593Smuzhiyun MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 0x5 260*4882a593Smuzhiyun MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5 261*4882a593Smuzhiyun MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5 262*4882a593Smuzhiyun MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5 263*4882a593Smuzhiyun MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5 264*4882a593Smuzhiyun MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5 265*4882a593Smuzhiyun MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5 266*4882a593Smuzhiyun MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5 267*4882a593Smuzhiyun MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5 268*4882a593Smuzhiyun MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5 269*4882a593Smuzhiyun MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5 270*4882a593Smuzhiyun MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5 271*4882a593Smuzhiyun MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5 272*4882a593Smuzhiyun MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5 273*4882a593Smuzhiyun MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5 274*4882a593Smuzhiyun MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5 275*4882a593Smuzhiyun MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5 276*4882a593Smuzhiyun MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5 277*4882a593Smuzhiyun MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5 278*4882a593Smuzhiyun MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5 279*4882a593Smuzhiyun MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5 280*4882a593Smuzhiyun MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5 281*4882a593Smuzhiyun MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5 282*4882a593Smuzhiyun MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5 283*4882a593Smuzhiyun MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5 284*4882a593Smuzhiyun >; 285*4882a593Smuzhiyun }; 286*4882a593Smuzhiyun 287*4882a593Smuzhiyun pinctrl_uart2: uart2grp { 288*4882a593Smuzhiyun fsl,pins = < 289*4882a593Smuzhiyun MX53_PAD_EIM_D26__UART2_RXD_MUX 0x1e4 290*4882a593Smuzhiyun MX53_PAD_EIM_D27__UART2_TXD_MUX 0x1e4 291*4882a593Smuzhiyun MX53_PAD_EIM_D28__UART2_RTS 0x1e4 292*4882a593Smuzhiyun MX53_PAD_EIM_D29__UART2_CTS 0x1e4 293*4882a593Smuzhiyun >; 294*4882a593Smuzhiyun }; 295*4882a593Smuzhiyun}; 296