1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun/* 4*4882a593Smuzhiyun * Copyright (C) 2018 Zodiac Inflight Innovations 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/dts-v1/; 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include "imx51.dtsi" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun model = "ZII SCU2 Mezz Board"; 13*4882a593Smuzhiyun compatible = "zii,imx51-scu2-mezz", "fsl,imx51"; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun chosen { 16*4882a593Smuzhiyun stdout-path = &uart1; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* Will be filled by the bootloader */ 20*4882a593Smuzhiyun memory@90000000 { 21*4882a593Smuzhiyun device_type = "memory"; 22*4882a593Smuzhiyun reg = <0x90000000 0>; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun aliases { 26*4882a593Smuzhiyun mdio-gpio0 = &mdio_gpio; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun usb_vbus: regulator-usb-vbus { 30*4882a593Smuzhiyun compatible = "regulator-fixed"; 31*4882a593Smuzhiyun pinctrl-names = "default"; 32*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usb_mmc_reset>; 33*4882a593Smuzhiyun gpio = <&gpio3 13 GPIO_ACTIVE_LOW>; 34*4882a593Smuzhiyun startup-delay-us = <150000>; 35*4882a593Smuzhiyun regulator-name = "usb_vbus"; 36*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 37*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun mdio_gpio: mdio-gpio { 41*4882a593Smuzhiyun compatible = "virtual,mdio-gpio"; 42*4882a593Smuzhiyun pinctrl-names = "default"; 43*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_swmdio>; 44*4882a593Smuzhiyun gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>, /* mdc */ 45*4882a593Smuzhiyun <&gpio2 6 GPIO_ACTIVE_HIGH>; /* mdio */ 46*4882a593Smuzhiyun #address-cells = <1>; 47*4882a593Smuzhiyun #size-cells = <0>; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun switch@0 { 50*4882a593Smuzhiyun compatible = "marvell,mv88e6085"; 51*4882a593Smuzhiyun reg = <0>; 52*4882a593Smuzhiyun dsa,member = <0 0>; 53*4882a593Smuzhiyun eeprom-length = <512>; 54*4882a593Smuzhiyun interrupt-parent = <&gpio1>; 55*4882a593Smuzhiyun interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 56*4882a593Smuzhiyun interrupt-controller; 57*4882a593Smuzhiyun #interrupt-cells = <2>; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun ports { 60*4882a593Smuzhiyun #address-cells = <1>; 61*4882a593Smuzhiyun #size-cells = <0>; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun port@0 { 64*4882a593Smuzhiyun reg = <0>; 65*4882a593Smuzhiyun label = "port4"; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun port@1 { 69*4882a593Smuzhiyun reg = <1>; 70*4882a593Smuzhiyun label = "port5"; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun port@2 { 74*4882a593Smuzhiyun reg = <2>; 75*4882a593Smuzhiyun label = "port6"; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun port@3 { 79*4882a593Smuzhiyun reg = <3>; 80*4882a593Smuzhiyun label = "port7"; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun port@4 { 84*4882a593Smuzhiyun reg = <4>; 85*4882a593Smuzhiyun label = "cpu"; 86*4882a593Smuzhiyun ethernet = <&fec>; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun fixed-link { 89*4882a593Smuzhiyun speed = <100>; 90*4882a593Smuzhiyun full-duplex; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun port@5 { 95*4882a593Smuzhiyun reg = <5>; 96*4882a593Smuzhiyun label = "mezz2esb"; 97*4882a593Smuzhiyun phy-mode = "sgmii"; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun fixed-link { 100*4882a593Smuzhiyun speed = <1000>; 101*4882a593Smuzhiyun full-duplex; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun }; 107*4882a593Smuzhiyun}; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun&cpu { 110*4882a593Smuzhiyun cpu-supply = <&sw1_reg>; 111*4882a593Smuzhiyun}; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun&ecspi1 { 114*4882a593Smuzhiyun pinctrl-names = "default"; 115*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_ecspi1>; 116*4882a593Smuzhiyun cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>, 117*4882a593Smuzhiyun <&gpio4 25 GPIO_ACTIVE_LOW>; 118*4882a593Smuzhiyun status = "okay"; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun pmic@0 { 121*4882a593Smuzhiyun compatible = "fsl,mc13892"; 122*4882a593Smuzhiyun pinctrl-names = "default"; 123*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pmic>; 124*4882a593Smuzhiyun spi-max-frequency = <6000000>; 125*4882a593Smuzhiyun spi-cs-high; 126*4882a593Smuzhiyun reg = <0>; 127*4882a593Smuzhiyun interrupt-parent = <&gpio1>; 128*4882a593Smuzhiyun interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 129*4882a593Smuzhiyun fsl,mc13xxx-uses-adc; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun regulators { 132*4882a593Smuzhiyun sw1_reg: sw1 { 133*4882a593Smuzhiyun regulator-min-microvolt = <600000>; 134*4882a593Smuzhiyun regulator-max-microvolt = <1375000>; 135*4882a593Smuzhiyun regulator-boot-on; 136*4882a593Smuzhiyun regulator-always-on; 137*4882a593Smuzhiyun }; 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun sw2_reg: sw2 { 140*4882a593Smuzhiyun regulator-min-microvolt = <900000>; 141*4882a593Smuzhiyun regulator-max-microvolt = <1850000>; 142*4882a593Smuzhiyun regulator-boot-on; 143*4882a593Smuzhiyun regulator-always-on; 144*4882a593Smuzhiyun }; 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun sw3_reg: sw3 { 147*4882a593Smuzhiyun regulator-min-microvolt = <1100000>; 148*4882a593Smuzhiyun regulator-max-microvolt = <1850000>; 149*4882a593Smuzhiyun regulator-boot-on; 150*4882a593Smuzhiyun regulator-always-on; 151*4882a593Smuzhiyun }; 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun sw4_reg: sw4 { 154*4882a593Smuzhiyun regulator-min-microvolt = <1100000>; 155*4882a593Smuzhiyun regulator-max-microvolt = <1850000>; 156*4882a593Smuzhiyun regulator-boot-on; 157*4882a593Smuzhiyun regulator-always-on; 158*4882a593Smuzhiyun }; 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun vpll_reg: vpll { 161*4882a593Smuzhiyun regulator-min-microvolt = <1050000>; 162*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 163*4882a593Smuzhiyun regulator-boot-on; 164*4882a593Smuzhiyun regulator-always-on; 165*4882a593Smuzhiyun }; 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun vdig_reg: vdig { 168*4882a593Smuzhiyun regulator-min-microvolt = <1650000>; 169*4882a593Smuzhiyun regulator-max-microvolt = <1650000>; 170*4882a593Smuzhiyun regulator-boot-on; 171*4882a593Smuzhiyun }; 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun vsd_reg: vsd { 174*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 175*4882a593Smuzhiyun regulator-max-microvolt = <3150000>; 176*4882a593Smuzhiyun regulator-always-on; 177*4882a593Smuzhiyun }; 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun vusb_reg: vusb { 180*4882a593Smuzhiyun regulator-always-on; 181*4882a593Smuzhiyun }; 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun vusb2_reg: vusb2 { 184*4882a593Smuzhiyun regulator-min-microvolt = <2400000>; 185*4882a593Smuzhiyun regulator-max-microvolt = <2775000>; 186*4882a593Smuzhiyun regulator-boot-on; 187*4882a593Smuzhiyun regulator-always-on; 188*4882a593Smuzhiyun }; 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun vvideo_reg: vvideo { 191*4882a593Smuzhiyun regulator-min-microvolt = <2775000>; 192*4882a593Smuzhiyun regulator-max-microvolt = <2775000>; 193*4882a593Smuzhiyun }; 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun vaudio_reg: vaudio { 196*4882a593Smuzhiyun regulator-min-microvolt = <2300000>; 197*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 198*4882a593Smuzhiyun }; 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun vcam_reg: vcam { 201*4882a593Smuzhiyun regulator-min-microvolt = <2500000>; 202*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 203*4882a593Smuzhiyun }; 204*4882a593Smuzhiyun 205*4882a593Smuzhiyun vgen1_reg: vgen1 { 206*4882a593Smuzhiyun regulator-min-microvolt = <1200000>; 207*4882a593Smuzhiyun regulator-max-microvolt = <1200000>; 208*4882a593Smuzhiyun }; 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun vgen2_reg: vgen2 { 211*4882a593Smuzhiyun regulator-min-microvolt = <1200000>; 212*4882a593Smuzhiyun regulator-max-microvolt = <3150000>; 213*4882a593Smuzhiyun regulator-always-on; 214*4882a593Smuzhiyun }; 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun vgen3_reg: vgen3 { 217*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 218*4882a593Smuzhiyun regulator-max-microvolt = <2900000>; 219*4882a593Smuzhiyun regulator-always-on; 220*4882a593Smuzhiyun }; 221*4882a593Smuzhiyun }; 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun leds { 224*4882a593Smuzhiyun #address-cells = <1>; 225*4882a593Smuzhiyun #size-cells = <0>; 226*4882a593Smuzhiyun led-control = <0x0 0x0 0x3f83f8 0x0>; 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun sysled3: led3@3 { 229*4882a593Smuzhiyun reg = <3>; 230*4882a593Smuzhiyun label = "system:red:power"; 231*4882a593Smuzhiyun linux,default-trigger = "default-on"; 232*4882a593Smuzhiyun }; 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun sysled4: led4@4 { 235*4882a593Smuzhiyun reg = <4>; 236*4882a593Smuzhiyun label = "system:green:act"; 237*4882a593Smuzhiyun linux,default-trigger = "heartbeat"; 238*4882a593Smuzhiyun }; 239*4882a593Smuzhiyun }; 240*4882a593Smuzhiyun }; 241*4882a593Smuzhiyun 242*4882a593Smuzhiyun flash@1 { 243*4882a593Smuzhiyun compatible = "atmel,at45", "atmel,dataflash"; 244*4882a593Smuzhiyun reg = <1>; 245*4882a593Smuzhiyun spi-max-frequency = <25000000>; 246*4882a593Smuzhiyun }; 247*4882a593Smuzhiyun}; 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun&esdhc1 { 250*4882a593Smuzhiyun pinctrl-names = "default"; 251*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_esdhc1>; 252*4882a593Smuzhiyun bus-width = <8>; 253*4882a593Smuzhiyun non-removable; 254*4882a593Smuzhiyun no-1-8-v; 255*4882a593Smuzhiyun no-sdio; 256*4882a593Smuzhiyun no-sd; 257*4882a593Smuzhiyun status = "okay"; 258*4882a593Smuzhiyun}; 259*4882a593Smuzhiyun 260*4882a593Smuzhiyun&esdhc4 { 261*4882a593Smuzhiyun pinctrl-names = "default"; 262*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_esdhc4>; 263*4882a593Smuzhiyun bus-width = <4>; 264*4882a593Smuzhiyun no-1-8-v; 265*4882a593Smuzhiyun no-sdio; 266*4882a593Smuzhiyun cd-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; 267*4882a593Smuzhiyun status = "okay"; 268*4882a593Smuzhiyun}; 269*4882a593Smuzhiyun 270*4882a593Smuzhiyun&fec { 271*4882a593Smuzhiyun pinctrl-names = "default"; 272*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_fec>; 273*4882a593Smuzhiyun phy-mode = "mii"; 274*4882a593Smuzhiyun status = "okay"; 275*4882a593Smuzhiyun phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; 276*4882a593Smuzhiyun phy-reset-duration = <1>; 277*4882a593Smuzhiyun phy-supply = <&vgen3_reg>; 278*4882a593Smuzhiyun phy-handle = <ðphy>; 279*4882a593Smuzhiyun 280*4882a593Smuzhiyun mdio { 281*4882a593Smuzhiyun #address-cells = <1>; 282*4882a593Smuzhiyun #size-cells = <0>; 283*4882a593Smuzhiyun 284*4882a593Smuzhiyun ethphy: ethernet-phy@0 { 285*4882a593Smuzhiyun reg = <0>; 286*4882a593Smuzhiyun max-speed = <100>; 287*4882a593Smuzhiyun }; 288*4882a593Smuzhiyun }; 289*4882a593Smuzhiyun}; 290*4882a593Smuzhiyun 291*4882a593Smuzhiyun&i2c2 { 292*4882a593Smuzhiyun pinctrl-names = "default"; 293*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c2>; 294*4882a593Smuzhiyun status = "okay"; 295*4882a593Smuzhiyun 296*4882a593Smuzhiyun eeprom@50 { 297*4882a593Smuzhiyun compatible = "atmel,24c04"; 298*4882a593Smuzhiyun pagesize = <16>; 299*4882a593Smuzhiyun reg = <0x50>; 300*4882a593Smuzhiyun }; 301*4882a593Smuzhiyun}; 302*4882a593Smuzhiyun 303*4882a593Smuzhiyun&uart1 { 304*4882a593Smuzhiyun pinctrl-names = "default"; 305*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart1>; 306*4882a593Smuzhiyun status = "okay"; 307*4882a593Smuzhiyun}; 308*4882a593Smuzhiyun 309*4882a593Smuzhiyun&uart3 { 310*4882a593Smuzhiyun pinctrl-names = "default"; 311*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart3>; 312*4882a593Smuzhiyun status = "okay"; 313*4882a593Smuzhiyun 314*4882a593Smuzhiyun rave-sp { 315*4882a593Smuzhiyun compatible = "zii,rave-sp-mezz"; 316*4882a593Smuzhiyun current-speed = <57600>; 317*4882a593Smuzhiyun #address-cells = <1>; 318*4882a593Smuzhiyun #size-cells = <1>; 319*4882a593Smuzhiyun 320*4882a593Smuzhiyun watchdog { 321*4882a593Smuzhiyun compatible = "zii,rave-sp-watchdog-legacy"; 322*4882a593Smuzhiyun }; 323*4882a593Smuzhiyun 324*4882a593Smuzhiyun eeprom@a4 { 325*4882a593Smuzhiyun compatible = "zii,rave-sp-eeprom"; 326*4882a593Smuzhiyun reg = <0xa4 0x4000>; 327*4882a593Smuzhiyun #address-cells = <1>; 328*4882a593Smuzhiyun #size-cells = <1>; 329*4882a593Smuzhiyun zii,eeprom-name = "main-eeprom"; 330*4882a593Smuzhiyun }; 331*4882a593Smuzhiyun }; 332*4882a593Smuzhiyun}; 333*4882a593Smuzhiyun 334*4882a593Smuzhiyun&usbotg { 335*4882a593Smuzhiyun dr_mode = "host"; 336*4882a593Smuzhiyun disable-over-current; 337*4882a593Smuzhiyun phy_type = "utmi_wide"; 338*4882a593Smuzhiyun vbus-supply = <&usb_vbus>; 339*4882a593Smuzhiyun status = "okay"; 340*4882a593Smuzhiyun}; 341*4882a593Smuzhiyun 342*4882a593Smuzhiyun&usbphy0 { 343*4882a593Smuzhiyun vcc-supply = <&vusb2_reg>; 344*4882a593Smuzhiyun}; 345*4882a593Smuzhiyun 346*4882a593Smuzhiyun&vpu { 347*4882a593Smuzhiyun status = "disabled"; 348*4882a593Smuzhiyun}; 349*4882a593Smuzhiyun 350*4882a593Smuzhiyun&wdog1 { 351*4882a593Smuzhiyun status = "disabled"; 352*4882a593Smuzhiyun}; 353*4882a593Smuzhiyun 354*4882a593Smuzhiyun&iomuxc { 355*4882a593Smuzhiyun pinctrl_ecspi1: ecspi1grp { 356*4882a593Smuzhiyun fsl,pins = < 357*4882a593Smuzhiyun MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 358*4882a593Smuzhiyun MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 359*4882a593Smuzhiyun MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 360*4882a593Smuzhiyun MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 361*4882a593Smuzhiyun MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 362*4882a593Smuzhiyun >; 363*4882a593Smuzhiyun }; 364*4882a593Smuzhiyun 365*4882a593Smuzhiyun pinctrl_esdhc1: esdhc1grp { 366*4882a593Smuzhiyun fsl,pins = < 367*4882a593Smuzhiyun MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 368*4882a593Smuzhiyun MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 369*4882a593Smuzhiyun MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 370*4882a593Smuzhiyun MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 371*4882a593Smuzhiyun MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 372*4882a593Smuzhiyun MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 373*4882a593Smuzhiyun MX51_PAD_SD2_DATA0__SD1_DAT4 0x20d5 374*4882a593Smuzhiyun MX51_PAD_SD2_DATA1__SD1_DAT5 0x20d5 375*4882a593Smuzhiyun MX51_PAD_SD2_DATA2__SD1_DAT6 0x20d5 376*4882a593Smuzhiyun MX51_PAD_SD2_DATA3__SD1_DAT7 0x20d5 377*4882a593Smuzhiyun >; 378*4882a593Smuzhiyun }; 379*4882a593Smuzhiyun 380*4882a593Smuzhiyun pinctrl_esdhc4: esdhc4grp { 381*4882a593Smuzhiyun fsl,pins = < 382*4882a593Smuzhiyun MX51_PAD_NANDF_RB1__SD4_CMD 0x400020d5 383*4882a593Smuzhiyun MX51_PAD_NANDF_CS2__SD4_CLK 0x20d5 384*4882a593Smuzhiyun MX51_PAD_NANDF_CS3__SD4_DAT0 0x20d5 385*4882a593Smuzhiyun MX51_PAD_NANDF_CS4__SD4_DAT1 0x20d5 386*4882a593Smuzhiyun MX51_PAD_NANDF_CS5__SD4_DAT2 0x20d5 387*4882a593Smuzhiyun MX51_PAD_NANDF_CS6__SD4_DAT3 0x20d5 388*4882a593Smuzhiyun MX51_PAD_NANDF_D0__GPIO4_8 0x100 389*4882a593Smuzhiyun >; 390*4882a593Smuzhiyun }; 391*4882a593Smuzhiyun 392*4882a593Smuzhiyun pinctrl_fec: fecgrp { 393*4882a593Smuzhiyun fsl,pins = < 394*4882a593Smuzhiyun MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x2004 395*4882a593Smuzhiyun MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x2004 396*4882a593Smuzhiyun MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x2004 397*4882a593Smuzhiyun MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x2004 398*4882a593Smuzhiyun MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x2004 399*4882a593Smuzhiyun MX51_PAD_DISP2_DAT10__FEC_COL 0x0180 400*4882a593Smuzhiyun MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x0180 401*4882a593Smuzhiyun MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x20a4 402*4882a593Smuzhiyun MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x20a4 403*4882a593Smuzhiyun MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x2180 404*4882a593Smuzhiyun MX51_PAD_DI_GP3__FEC_TX_ER 0x2004 405*4882a593Smuzhiyun MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x2180 406*4882a593Smuzhiyun MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x0085 407*4882a593Smuzhiyun MX51_PAD_DI_GP4__FEC_RDATA2 0x0085 408*4882a593Smuzhiyun MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x0085 409*4882a593Smuzhiyun MX51_PAD_DI2_PIN2__FEC_MDC 0x2004 410*4882a593Smuzhiyun MX51_PAD_DI2_PIN3__FEC_MDIO 0x01f5 411*4882a593Smuzhiyun MX51_PAD_DI2_PIN4__FEC_CRS 0x0180 412*4882a593Smuzhiyun MX51_PAD_EIM_A20__GPIO2_14 0x0085 413*4882a593Smuzhiyun MX51_PAD_EIM_A21__GPIO2_15 0x00e5 414*4882a593Smuzhiyun >; 415*4882a593Smuzhiyun }; 416*4882a593Smuzhiyun 417*4882a593Smuzhiyun pinctrl_i2c2: i2c2grp { 418*4882a593Smuzhiyun fsl,pins = < 419*4882a593Smuzhiyun MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed 420*4882a593Smuzhiyun MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed 421*4882a593Smuzhiyun >; 422*4882a593Smuzhiyun }; 423*4882a593Smuzhiyun 424*4882a593Smuzhiyun pinctrl_pmic: pmicgrp { 425*4882a593Smuzhiyun fsl,pins = < 426*4882a593Smuzhiyun MX51_PAD_GPIO1_4__GPIO1_4 0x85 427*4882a593Smuzhiyun MX51_PAD_GPIO1_8__GPIO1_8 0xe5 428*4882a593Smuzhiyun >; 429*4882a593Smuzhiyun }; 430*4882a593Smuzhiyun 431*4882a593Smuzhiyun pinctrl_swmdio: swmdiogrp { 432*4882a593Smuzhiyun fsl,pins = < 433*4882a593Smuzhiyun MX51_PAD_EIM_D22__GPIO2_6 0x100 434*4882a593Smuzhiyun MX51_PAD_EIM_D23__GPIO2_7 0x100 435*4882a593Smuzhiyun >; 436*4882a593Smuzhiyun }; 437*4882a593Smuzhiyun 438*4882a593Smuzhiyun pinctrl_uart1: uart1grp { 439*4882a593Smuzhiyun fsl,pins = < 440*4882a593Smuzhiyun MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 441*4882a593Smuzhiyun MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 442*4882a593Smuzhiyun >; 443*4882a593Smuzhiyun }; 444*4882a593Smuzhiyun 445*4882a593Smuzhiyun pinctrl_uart3: uart3grp { 446*4882a593Smuzhiyun fsl,pins = < 447*4882a593Smuzhiyun MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 448*4882a593Smuzhiyun MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 449*4882a593Smuzhiyun >; 450*4882a593Smuzhiyun }; 451*4882a593Smuzhiyun 452*4882a593Smuzhiyun pinctrl_usb_mmc_reset: usbmmcgrp { 453*4882a593Smuzhiyun fsl,pins = < 454*4882a593Smuzhiyun MX51_PAD_CSI1_D9__GPIO3_13 0x85 455*4882a593Smuzhiyun >; 456*4882a593Smuzhiyun }; 457*4882a593Smuzhiyun}; 458