xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/imx51-apf51dev.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright 2013 Armadeus Systems - <support@armadeus.com>
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun/* APF51Dev is a docking board for the APF51 SOM */
7*4882a593Smuzhiyun#include "imx51-apf51.dts"
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun/ {
10*4882a593Smuzhiyun	model = "Armadeus Systems APF51Dev docking/development board";
11*4882a593Smuzhiyun	compatible = "armadeus,imx51-apf51dev", "armadeus,imx51-apf51", "fsl,imx51";
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun	backlight {
14*4882a593Smuzhiyun		pinctrl-names = "default";
15*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_backlight>;
16*4882a593Smuzhiyun		compatible = "gpio-backlight";
17*4882a593Smuzhiyun		gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
18*4882a593Smuzhiyun		default-on;
19*4882a593Smuzhiyun	};
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun	disp1 {
22*4882a593Smuzhiyun		compatible = "fsl,imx-parallel-display";
23*4882a593Smuzhiyun		interface-pix-fmt = "bgr666";
24*4882a593Smuzhiyun		pinctrl-names = "default";
25*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_ipu_disp1>;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun		display-timings {
28*4882a593Smuzhiyun			lw700 {
29*4882a593Smuzhiyun				native-mode;
30*4882a593Smuzhiyun				clock-frequency = <33000033>;
31*4882a593Smuzhiyun				hactive = <800>;
32*4882a593Smuzhiyun				vactive = <480>;
33*4882a593Smuzhiyun				hback-porch = <96>;
34*4882a593Smuzhiyun				hfront-porch = <96>;
35*4882a593Smuzhiyun				vback-porch = <20>;
36*4882a593Smuzhiyun				vfront-porch = <21>;
37*4882a593Smuzhiyun				hsync-len = <64>;
38*4882a593Smuzhiyun				vsync-len = <4>;
39*4882a593Smuzhiyun				hsync-active = <1>;
40*4882a593Smuzhiyun				vsync-active = <1>;
41*4882a593Smuzhiyun				de-active = <1>;
42*4882a593Smuzhiyun				pixelclk-active = <0>;
43*4882a593Smuzhiyun			};
44*4882a593Smuzhiyun		};
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun		port {
47*4882a593Smuzhiyun			display_in: endpoint {
48*4882a593Smuzhiyun				remote-endpoint = <&ipu_di0_disp1>;
49*4882a593Smuzhiyun			};
50*4882a593Smuzhiyun		};
51*4882a593Smuzhiyun	};
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun	gpio-keys {
54*4882a593Smuzhiyun		compatible = "gpio-keys";
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun		user-key {
57*4882a593Smuzhiyun			label = "user";
58*4882a593Smuzhiyun			gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
59*4882a593Smuzhiyun			linux,code = <256>; /* BTN_0 */
60*4882a593Smuzhiyun		};
61*4882a593Smuzhiyun	};
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun	leds {
64*4882a593Smuzhiyun		compatible = "gpio-leds";
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun		user {
67*4882a593Smuzhiyun			label = "Heartbeat";
68*4882a593Smuzhiyun			gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
69*4882a593Smuzhiyun			linux,default-trigger = "heartbeat";
70*4882a593Smuzhiyun		};
71*4882a593Smuzhiyun	};
72*4882a593Smuzhiyun};
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun&ecspi1 {
75*4882a593Smuzhiyun	pinctrl-names = "default";
76*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_ecspi1>;
77*4882a593Smuzhiyun	cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>,
78*4882a593Smuzhiyun		   <&gpio4 25 GPIO_ACTIVE_LOW>;
79*4882a593Smuzhiyun	status = "okay";
80*4882a593Smuzhiyun};
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun&ecspi2 {
83*4882a593Smuzhiyun	pinctrl-names = "default";
84*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_ecspi2>;
85*4882a593Smuzhiyun	cs-gpios = <&gpio3 28 GPIO_ACTIVE_LOW>,
86*4882a593Smuzhiyun		   <&gpio3 27 GPIO_ACTIVE_LOW>;
87*4882a593Smuzhiyun	status = "okay";
88*4882a593Smuzhiyun};
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun&esdhc1 {
91*4882a593Smuzhiyun	pinctrl-names = "default";
92*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_esdhc1>;
93*4882a593Smuzhiyun	cd-gpios = <&gpio2 29 GPIO_ACTIVE_LOW>;
94*4882a593Smuzhiyun	bus-width = <4>;
95*4882a593Smuzhiyun	status = "okay";
96*4882a593Smuzhiyun};
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun&esdhc2 {
99*4882a593Smuzhiyun	pinctrl-names = "default";
100*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_esdhc2>;
101*4882a593Smuzhiyun	bus-width = <4>;
102*4882a593Smuzhiyun	non-removable;
103*4882a593Smuzhiyun	status = "okay";
104*4882a593Smuzhiyun};
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun&i2c2 {
107*4882a593Smuzhiyun	pinctrl-names = "default";
108*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c2>;
109*4882a593Smuzhiyun	status = "okay";
110*4882a593Smuzhiyun};
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun&iomuxc {
113*4882a593Smuzhiyun	pinctrl-names = "default";
114*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_hog>;
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun	imx51-apf51dev {
117*4882a593Smuzhiyun		pinctrl_backlight: backlightgrp {
118*4882a593Smuzhiyun			fsl,pins = <
119*4882a593Smuzhiyun				MX51_PAD_DI1_D1_CS__GPIO3_4 0x1F5
120*4882a593Smuzhiyun			>;
121*4882a593Smuzhiyun		};
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun		pinctrl_hog: hoggrp {
124*4882a593Smuzhiyun			fsl,pins = <
125*4882a593Smuzhiyun				MX51_PAD_EIM_EB2__GPIO2_22   0x0C5
126*4882a593Smuzhiyun				MX51_PAD_EIM_EB3__GPIO2_23   0x0C5
127*4882a593Smuzhiyun				MX51_PAD_EIM_CS4__GPIO2_29   0x100
128*4882a593Smuzhiyun				MX51_PAD_NANDF_D13__GPIO3_27 0x0C5
129*4882a593Smuzhiyun				MX51_PAD_NANDF_D12__GPIO3_28 0x0C5
130*4882a593Smuzhiyun				MX51_PAD_CSPI1_SS0__GPIO4_24 0x0C5
131*4882a593Smuzhiyun				MX51_PAD_CSPI1_SS1__GPIO4_25 0x0C5
132*4882a593Smuzhiyun				MX51_PAD_GPIO1_2__GPIO1_2    0x0C5
133*4882a593Smuzhiyun				MX51_PAD_GPIO1_3__GPIO1_3    0x0C5
134*4882a593Smuzhiyun			>;
135*4882a593Smuzhiyun		};
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun		pinctrl_ecspi1: ecspi1grp {
138*4882a593Smuzhiyun			fsl,pins = <
139*4882a593Smuzhiyun				MX51_PAD_CSPI1_MISO__ECSPI1_MISO	0x185
140*4882a593Smuzhiyun				MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI	0x185
141*4882a593Smuzhiyun				MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK	0x185
142*4882a593Smuzhiyun			>;
143*4882a593Smuzhiyun		};
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun		pinctrl_ecspi2: ecspi2grp {
146*4882a593Smuzhiyun			fsl,pins = <
147*4882a593Smuzhiyun				MX51_PAD_NANDF_RB3__ECSPI2_MISO		0x185
148*4882a593Smuzhiyun				MX51_PAD_NANDF_D15__ECSPI2_MOSI		0x185
149*4882a593Smuzhiyun				MX51_PAD_NANDF_RB2__ECSPI2_SCLK		0x185
150*4882a593Smuzhiyun			>;
151*4882a593Smuzhiyun		};
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun		pinctrl_esdhc1: esdhc1grp {
154*4882a593Smuzhiyun			fsl,pins = <
155*4882a593Smuzhiyun				MX51_PAD_SD1_CMD__SD1_CMD		0x400020d5
156*4882a593Smuzhiyun				MX51_PAD_SD1_CLK__SD1_CLK		0x20d5
157*4882a593Smuzhiyun				MX51_PAD_SD1_DATA0__SD1_DATA0		0x20d5
158*4882a593Smuzhiyun				MX51_PAD_SD1_DATA1__SD1_DATA1		0x20d5
159*4882a593Smuzhiyun				MX51_PAD_SD1_DATA2__SD1_DATA2		0x20d5
160*4882a593Smuzhiyun				MX51_PAD_SD1_DATA3__SD1_DATA3		0x20d5
161*4882a593Smuzhiyun			>;
162*4882a593Smuzhiyun		};
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun		pinctrl_esdhc2: esdhc2grp {
165*4882a593Smuzhiyun			fsl,pins = <
166*4882a593Smuzhiyun				MX51_PAD_SD2_CMD__SD2_CMD		0x400020d5
167*4882a593Smuzhiyun				MX51_PAD_SD2_CLK__SD2_CLK		0x20d5
168*4882a593Smuzhiyun				MX51_PAD_SD2_DATA0__SD2_DATA0		0x20d5
169*4882a593Smuzhiyun				MX51_PAD_SD2_DATA1__SD2_DATA1		0x20d5
170*4882a593Smuzhiyun				MX51_PAD_SD2_DATA2__SD2_DATA2		0x20d5
171*4882a593Smuzhiyun				MX51_PAD_SD2_DATA3__SD2_DATA3		0x20d5
172*4882a593Smuzhiyun			>;
173*4882a593Smuzhiyun		};
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun		pinctrl_i2c2: i2c2grp {
176*4882a593Smuzhiyun			fsl,pins = <
177*4882a593Smuzhiyun				MX51_PAD_EIM_D27__I2C2_SCL		0x400001ed
178*4882a593Smuzhiyun				MX51_PAD_EIM_D24__I2C2_SDA		0x400001ed
179*4882a593Smuzhiyun			>;
180*4882a593Smuzhiyun		};
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun		pinctrl_ipu_disp1: ipudisp1grp {
183*4882a593Smuzhiyun			fsl,pins = <
184*4882a593Smuzhiyun				MX51_PAD_DISP1_DAT0__DISP1_DAT0		0x5
185*4882a593Smuzhiyun				MX51_PAD_DISP1_DAT1__DISP1_DAT1		0x5
186*4882a593Smuzhiyun				MX51_PAD_DISP1_DAT2__DISP1_DAT2		0x5
187*4882a593Smuzhiyun				MX51_PAD_DISP1_DAT3__DISP1_DAT3		0x5
188*4882a593Smuzhiyun				MX51_PAD_DISP1_DAT4__DISP1_DAT4		0x5
189*4882a593Smuzhiyun				MX51_PAD_DISP1_DAT5__DISP1_DAT5		0x5
190*4882a593Smuzhiyun				MX51_PAD_DISP1_DAT6__DISP1_DAT6		0x5
191*4882a593Smuzhiyun				MX51_PAD_DISP1_DAT7__DISP1_DAT7		0x5
192*4882a593Smuzhiyun				MX51_PAD_DISP1_DAT8__DISP1_DAT8		0x5
193*4882a593Smuzhiyun				MX51_PAD_DISP1_DAT9__DISP1_DAT9		0x5
194*4882a593Smuzhiyun				MX51_PAD_DISP1_DAT10__DISP1_DAT10	0x5
195*4882a593Smuzhiyun				MX51_PAD_DISP1_DAT11__DISP1_DAT11	0x5
196*4882a593Smuzhiyun				MX51_PAD_DISP1_DAT12__DISP1_DAT12	0x5
197*4882a593Smuzhiyun				MX51_PAD_DISP1_DAT13__DISP1_DAT13	0x5
198*4882a593Smuzhiyun				MX51_PAD_DISP1_DAT14__DISP1_DAT14	0x5
199*4882a593Smuzhiyun				MX51_PAD_DISP1_DAT15__DISP1_DAT15	0x5
200*4882a593Smuzhiyun				MX51_PAD_DISP1_DAT16__DISP1_DAT16	0x5
201*4882a593Smuzhiyun				MX51_PAD_DISP1_DAT17__DISP1_DAT17	0x5
202*4882a593Smuzhiyun				MX51_PAD_DISP1_DAT18__DISP1_DAT18	0x5
203*4882a593Smuzhiyun				MX51_PAD_DISP1_DAT19__DISP1_DAT19	0x5
204*4882a593Smuzhiyun				MX51_PAD_DISP1_DAT20__DISP1_DAT20	0x5
205*4882a593Smuzhiyun				MX51_PAD_DISP1_DAT21__DISP1_DAT21	0x5
206*4882a593Smuzhiyun				MX51_PAD_DISP1_DAT22__DISP1_DAT22	0x5
207*4882a593Smuzhiyun				MX51_PAD_DISP1_DAT23__DISP1_DAT23	0x5
208*4882a593Smuzhiyun				MX51_PAD_DI1_PIN2__DI1_PIN2		0x5
209*4882a593Smuzhiyun				MX51_PAD_DI1_PIN3__DI1_PIN3		0x5
210*4882a593Smuzhiyun			>;
211*4882a593Smuzhiyun		};
212*4882a593Smuzhiyun	};
213*4882a593Smuzhiyun};
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun&ipu_di0_disp1 {
216*4882a593Smuzhiyun	remote-endpoint = <&display_in>;
217*4882a593Smuzhiyun};
218