1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright 2013 Eukréa Electromatique <denis@eukrea.com> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 9*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 10*4882a593Smuzhiyun#include "imx35-eukrea-cpuimx35.dtsi" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun model = "Eukrea CPUIMX35"; 14*4882a593Smuzhiyun compatible = "eukrea,mbimxsd35-baseboard", "eukrea,cpuimx35", "fsl,imx35"; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun gpio_keys { 17*4882a593Smuzhiyun compatible = "gpio-keys"; 18*4882a593Smuzhiyun pinctrl-names = "default"; 19*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_bp1>; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun bp1 { 22*4882a593Smuzhiyun label = "BP1"; 23*4882a593Smuzhiyun gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; 24*4882a593Smuzhiyun linux,code = <BTN_MISC>; 25*4882a593Smuzhiyun wakeup-source; 26*4882a593Smuzhiyun linux,input-type = <1>; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun leds { 31*4882a593Smuzhiyun compatible = "gpio-leds"; 32*4882a593Smuzhiyun pinctrl-names = "default"; 33*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_led1>; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun led1 { 36*4882a593Smuzhiyun label = "led1"; 37*4882a593Smuzhiyun gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; 38*4882a593Smuzhiyun linux,default-trigger = "heartbeat"; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun sound { 43*4882a593Smuzhiyun compatible = "eukrea,asoc-tlv320"; 44*4882a593Smuzhiyun eukrea,model = "imx35-eukrea-tlv320aic23"; 45*4882a593Smuzhiyun ssi-controller = <&ssi1>; 46*4882a593Smuzhiyun fsl,mux-int-port = <1>; 47*4882a593Smuzhiyun fsl,mux-ext-port = <4>; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun}; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun&audmux { 52*4882a593Smuzhiyun pinctrl-names = "default"; 53*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_audmux>; 54*4882a593Smuzhiyun status = "okay"; 55*4882a593Smuzhiyun}; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun&esdhc1 { 58*4882a593Smuzhiyun pinctrl-names = "default"; 59*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_esdhc1>; 60*4882a593Smuzhiyun cd-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; 61*4882a593Smuzhiyun status = "okay"; 62*4882a593Smuzhiyun}; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun&i2c1 { 65*4882a593Smuzhiyun tlv320aic23: codec@1a { 66*4882a593Smuzhiyun compatible = "ti,tlv320aic23"; 67*4882a593Smuzhiyun reg = <0x1a>; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun}; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun&iomuxc { 72*4882a593Smuzhiyun imx35-eukrea { 73*4882a593Smuzhiyun pinctrl_audmux: audmuxgrp { 74*4882a593Smuzhiyun fsl,pins = < 75*4882a593Smuzhiyun MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS 0x80000000 76*4882a593Smuzhiyun MX35_PAD_STXD4__AUDMUX_AUD4_TXD 0x80000000 77*4882a593Smuzhiyun MX35_PAD_SRXD4__AUDMUX_AUD4_RXD 0x80000000 78*4882a593Smuzhiyun MX35_PAD_SCK4__AUDMUX_AUD4_TXC 0x80000000 79*4882a593Smuzhiyun >; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun pinctrl_bp1: bp1grp { 83*4882a593Smuzhiyun fsl,pins = <MX35_PAD_LD19__GPIO3_25 0x80000000>; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun pinctrl_esdhc1: esdhc1grp { 87*4882a593Smuzhiyun fsl,pins = < 88*4882a593Smuzhiyun MX35_PAD_SD1_CMD__ESDHC1_CMD 0x80000000 89*4882a593Smuzhiyun MX35_PAD_SD1_CLK__ESDHC1_CLK 0x80000000 90*4882a593Smuzhiyun MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000 91*4882a593Smuzhiyun MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000 92*4882a593Smuzhiyun MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000 93*4882a593Smuzhiyun MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000 94*4882a593Smuzhiyun MX35_PAD_LD18__GPIO3_24 0x80000000 /* CD */ 95*4882a593Smuzhiyun >; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun pinctrl_led1: led1grp { 99*4882a593Smuzhiyun fsl,pins = <MX35_PAD_LD23__GPIO3_29 0x80000000>; 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun pinctrl_reg_lcd_3v3: reg-lcd-3v3 { 103*4882a593Smuzhiyun fsl,pins = <MX35_PAD_D3_CLS__GPIO1_4 0x80000000>; 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun pinctrl_uart1: uart1grp { 107*4882a593Smuzhiyun fsl,pins = < 108*4882a593Smuzhiyun MX35_PAD_TXD1__UART1_TXD_MUX 0x1c5 109*4882a593Smuzhiyun MX35_PAD_RXD1__UART1_RXD_MUX 0x1c5 110*4882a593Smuzhiyun MX35_PAD_CTS1__UART1_CTS 0x1c5 111*4882a593Smuzhiyun MX35_PAD_RTS1__UART1_RTS 0x1c5 112*4882a593Smuzhiyun >; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun pinctrl_uart2: uart2grp { 116*4882a593Smuzhiyun fsl,pins = < 117*4882a593Smuzhiyun MX35_PAD_RXD2__UART2_RXD_MUX 0x1c5 118*4882a593Smuzhiyun MX35_PAD_TXD2__UART2_TXD_MUX 0x1c5 119*4882a593Smuzhiyun MX35_PAD_RTS2__UART2_RTS 0x1c5 120*4882a593Smuzhiyun MX35_PAD_CTS2__UART2_CTS 0x1c5 121*4882a593Smuzhiyun >; 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun }; 124*4882a593Smuzhiyun}; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun&ssi1 { 127*4882a593Smuzhiyun codec-handle = <&tlv320aic23>; 128*4882a593Smuzhiyun status = "okay"; 129*4882a593Smuzhiyun}; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun&uart1 { 132*4882a593Smuzhiyun pinctrl-names = "default"; 133*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart1>; 134*4882a593Smuzhiyun uart-has-rtscts; 135*4882a593Smuzhiyun status = "okay"; 136*4882a593Smuzhiyun}; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun&uart2 { 139*4882a593Smuzhiyun pinctrl-names = "default"; 140*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart2>; 141*4882a593Smuzhiyun uart-has-rtscts; 142*4882a593Smuzhiyun status = "okay"; 143*4882a593Smuzhiyun}; 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun&usbhost1 { 146*4882a593Smuzhiyun phy_type = "serial"; 147*4882a593Smuzhiyun dr_mode = "host"; 148*4882a593Smuzhiyun status = "okay"; 149*4882a593Smuzhiyun}; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun&usbotg { 152*4882a593Smuzhiyun phy_type = "utmi"; 153*4882a593Smuzhiyun dr_mode = "otg"; 154*4882a593Smuzhiyun external-vbus-divider; 155*4882a593Smuzhiyun status = "okay"; 156*4882a593Smuzhiyun}; 157