1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright 2013 Eukréa Electromatique <denis@eukrea.com> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun#include "imx35.dtsi" 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/ { 9*4882a593Smuzhiyun model = "Eukrea CPUIMX35"; 10*4882a593Smuzhiyun compatible = "eukrea,cpuimx35", "fsl,imx35"; 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun memory@80000000 { 13*4882a593Smuzhiyun device_type = "memory"; 14*4882a593Smuzhiyun reg = <0x80000000 0x8000000>; /* 128M */ 15*4882a593Smuzhiyun }; 16*4882a593Smuzhiyun}; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun&fec { 19*4882a593Smuzhiyun pinctrl-names = "default"; 20*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_fec>; 21*4882a593Smuzhiyun status = "okay"; 22*4882a593Smuzhiyun}; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun&i2c1 { 25*4882a593Smuzhiyun pinctrl-names = "default"; 26*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c1>; 27*4882a593Smuzhiyun status = "okay"; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun pcf8563@51 { 30*4882a593Smuzhiyun compatible = "nxp,pcf8563"; 31*4882a593Smuzhiyun reg = <0x51>; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun tsc2007: tsc2007@48 { 35*4882a593Smuzhiyun compatible = "ti,tsc2007"; 36*4882a593Smuzhiyun gpios = <&gpio3 2 0>; 37*4882a593Smuzhiyun interrupt-parent = <&gpio3>; 38*4882a593Smuzhiyun interrupts = <0x2 0x8>; 39*4882a593Smuzhiyun pinctrl-names = "default"; 40*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_tsc2007_1>; 41*4882a593Smuzhiyun reg = <0x48>; 42*4882a593Smuzhiyun ti,x-plate-ohms = <180>; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun}; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun&iomuxc { 47*4882a593Smuzhiyun imx35-eukrea { 48*4882a593Smuzhiyun pinctrl_fec: fecgrp { 49*4882a593Smuzhiyun fsl,pins = < 50*4882a593Smuzhiyun MX35_PAD_FEC_TX_CLK__FEC_TX_CLK 0x80000000 51*4882a593Smuzhiyun MX35_PAD_FEC_RX_CLK__FEC_RX_CLK 0x80000000 52*4882a593Smuzhiyun MX35_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 53*4882a593Smuzhiyun MX35_PAD_FEC_COL__FEC_COL 0x80000000 54*4882a593Smuzhiyun MX35_PAD_FEC_RDATA0__FEC_RDATA_0 0x80000000 55*4882a593Smuzhiyun MX35_PAD_FEC_TDATA0__FEC_TDATA_0 0x80000000 56*4882a593Smuzhiyun MX35_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 57*4882a593Smuzhiyun MX35_PAD_FEC_MDC__FEC_MDC 0x80000000 58*4882a593Smuzhiyun MX35_PAD_FEC_MDIO__FEC_MDIO 0x80000000 59*4882a593Smuzhiyun MX35_PAD_FEC_TX_ERR__FEC_TX_ERR 0x80000000 60*4882a593Smuzhiyun MX35_PAD_FEC_RX_ERR__FEC_RX_ERR 0x80000000 61*4882a593Smuzhiyun MX35_PAD_FEC_CRS__FEC_CRS 0x80000000 62*4882a593Smuzhiyun MX35_PAD_FEC_RDATA1__FEC_RDATA_1 0x80000000 63*4882a593Smuzhiyun MX35_PAD_FEC_TDATA1__FEC_TDATA_1 0x80000000 64*4882a593Smuzhiyun MX35_PAD_FEC_RDATA2__FEC_RDATA_2 0x80000000 65*4882a593Smuzhiyun MX35_PAD_FEC_TDATA2__FEC_TDATA_2 0x80000000 66*4882a593Smuzhiyun MX35_PAD_FEC_RDATA3__FEC_RDATA_3 0x80000000 67*4882a593Smuzhiyun MX35_PAD_FEC_TDATA3__FEC_TDATA_3 0x80000000 68*4882a593Smuzhiyun >; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun pinctrl_i2c1: i2c1grp { 72*4882a593Smuzhiyun fsl,pins = < 73*4882a593Smuzhiyun MX35_PAD_I2C1_CLK__I2C1_SCL 0x80000000 74*4882a593Smuzhiyun MX35_PAD_I2C1_DAT__I2C1_SDA 0x80000000 75*4882a593Smuzhiyun >; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun pinctrl_tsc2007_1: tsc2007grp-1 { 79*4882a593Smuzhiyun fsl,pins = <MX35_PAD_ATA_DA2__GPIO3_2 0x80000000>; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun}; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun&nfc { 85*4882a593Smuzhiyun nand-bus-width = <8>; 86*4882a593Smuzhiyun nand-ecc-mode = "hw"; 87*4882a593Smuzhiyun nand-on-flash-bbt; 88*4882a593Smuzhiyun status = "okay"; 89*4882a593Smuzhiyun}; 90