xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/imx28-cfa10056.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright 2013 Free Electrons
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun/*
7*4882a593Smuzhiyun * The CFA-10055 is an expansion board for the CFA-10036 module and
8*4882a593Smuzhiyun * CFA-10037, thus we need to include the CFA-10037 DTS.
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun#include "imx28-cfa10037.dts"
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun/ {
13*4882a593Smuzhiyun	model = "Crystalfontz CFA-10056 Board";
14*4882a593Smuzhiyun	compatible = "crystalfontz,cfa10056", "crystalfontz,cfa10037", "crystalfontz,cfa10036", "fsl,imx28";
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun	apb@80000000 {
17*4882a593Smuzhiyun		apbh@80000000 {
18*4882a593Smuzhiyun			pinctrl@80018000 {
19*4882a593Smuzhiyun				spi2_pins_cfa10056: spi2-cfa10056@0 {
20*4882a593Smuzhiyun					reg = <0>;
21*4882a593Smuzhiyun					fsl,pinmux-ids = <
22*4882a593Smuzhiyun						MX28_PAD_SSP2_SCK__GPIO_2_16
23*4882a593Smuzhiyun						MX28_PAD_SSP2_MOSI__GPIO_2_17
24*4882a593Smuzhiyun						MX28_PAD_SSP2_MISO__GPIO_2_18
25*4882a593Smuzhiyun						MX28_PAD_AUART1_TX__GPIO_3_5
26*4882a593Smuzhiyun					>;
27*4882a593Smuzhiyun					fsl,drive-strength = <MXS_DRIVE_8mA>;
28*4882a593Smuzhiyun					fsl,voltage = <MXS_VOLTAGE_HIGH>;
29*4882a593Smuzhiyun					fsl,pull-up = <MXS_PULL_ENABLE>;
30*4882a593Smuzhiyun				};
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun				lcdif_pins_cfa10056: lcdif-10056@0 {
33*4882a593Smuzhiyun					reg = <0>;
34*4882a593Smuzhiyun					fsl,pinmux-ids = <
35*4882a593Smuzhiyun						MX28_PAD_LCD_RD_E__LCD_VSYNC
36*4882a593Smuzhiyun						MX28_PAD_LCD_WR_RWN__LCD_HSYNC
37*4882a593Smuzhiyun						MX28_PAD_LCD_RS__LCD_DOTCLK
38*4882a593Smuzhiyun						MX28_PAD_LCD_CS__LCD_ENABLE
39*4882a593Smuzhiyun					>;
40*4882a593Smuzhiyun					fsl,drive-strength = <MXS_DRIVE_4mA>;
41*4882a593Smuzhiyun					fsl,voltage = <MXS_VOLTAGE_HIGH>;
42*4882a593Smuzhiyun					fsl,pull-up = <MXS_PULL_DISABLE>;
43*4882a593Smuzhiyun				};
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun				lcdif_pins_cfa10056_pullup: lcdif-10056-pullup@0 {
46*4882a593Smuzhiyun					reg = <0>;
47*4882a593Smuzhiyun					fsl,pinmux-ids = <
48*4882a593Smuzhiyun						MX28_PAD_LCD_RESET__GPIO_3_30
49*4882a593Smuzhiyun					>;
50*4882a593Smuzhiyun					fsl,drive-strength = <MXS_DRIVE_4mA>;
51*4882a593Smuzhiyun					fsl,voltage = <MXS_VOLTAGE_HIGH>;
52*4882a593Smuzhiyun					fsl,pull-up = <MXS_PULL_ENABLE>;
53*4882a593Smuzhiyun				};
54*4882a593Smuzhiyun			};
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun			lcdif@80030000 {
57*4882a593Smuzhiyun				pinctrl-names = "default";
58*4882a593Smuzhiyun				pinctrl-0 = <&lcdif_24bit_pins_a
59*4882a593Smuzhiyun						&lcdif_pins_cfa10056
60*4882a593Smuzhiyun						&lcdif_pins_cfa10056_pullup >;
61*4882a593Smuzhiyun				display = <&display0>;
62*4882a593Smuzhiyun				status = "okay";
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun				display0: display0 {
65*4882a593Smuzhiyun					bits-per-pixel = <32>;
66*4882a593Smuzhiyun					bus-width = <24>;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun					display-timings {
69*4882a593Smuzhiyun						native-mode = <&timing0>;
70*4882a593Smuzhiyun						timing0: timing0 {
71*4882a593Smuzhiyun							clock-frequency = <32000000>;
72*4882a593Smuzhiyun							hactive = <480>;
73*4882a593Smuzhiyun							vactive = <800>;
74*4882a593Smuzhiyun							hback-porch = <2>;
75*4882a593Smuzhiyun							hfront-porch = <2>;
76*4882a593Smuzhiyun							vback-porch = <2>;
77*4882a593Smuzhiyun							vfront-porch = <2>;
78*4882a593Smuzhiyun							hsync-len = <5>;
79*4882a593Smuzhiyun							vsync-len = <5>;
80*4882a593Smuzhiyun							hsync-active = <0>;
81*4882a593Smuzhiyun							vsync-active = <0>;
82*4882a593Smuzhiyun							de-active = <1>;
83*4882a593Smuzhiyun							pixelclk-active = <1>;
84*4882a593Smuzhiyun						};
85*4882a593Smuzhiyun					};
86*4882a593Smuzhiyun				};
87*4882a593Smuzhiyun			};
88*4882a593Smuzhiyun		};
89*4882a593Smuzhiyun	};
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun	spi2 {
92*4882a593Smuzhiyun		compatible = "spi-gpio";
93*4882a593Smuzhiyun		pinctrl-names = "default";
94*4882a593Smuzhiyun		pinctrl-0 = <&spi2_pins_cfa10056>;
95*4882a593Smuzhiyun		status = "okay";
96*4882a593Smuzhiyun		gpio-sck = <&gpio2 16 0>;
97*4882a593Smuzhiyun		gpio-mosi = <&gpio2 17 0>;
98*4882a593Smuzhiyun		gpio-miso = <&gpio2 18 0>;
99*4882a593Smuzhiyun		cs-gpios = <&gpio3 5 0>;
100*4882a593Smuzhiyun		num-chipselects = <1>;
101*4882a593Smuzhiyun		#address-cells = <1>;
102*4882a593Smuzhiyun		#size-cells = <0>;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun		hx8369: hx8369@0 {
105*4882a593Smuzhiyun			compatible = "himax,hx8369a", "himax,hx8369";
106*4882a593Smuzhiyun			reg = <0>;
107*4882a593Smuzhiyun			spi-max-frequency = <100000>;
108*4882a593Smuzhiyun			spi-cpol;
109*4882a593Smuzhiyun			spi-cpha;
110*4882a593Smuzhiyun			gpios-reset = <&gpio3 30 0>;
111*4882a593Smuzhiyun		};
112*4882a593Smuzhiyun	};
113*4882a593Smuzhiyun};
114