1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright 2012 Sascha Hauer, Uwe Kleine-König, Steffen Trumtrar 4*4882a593Smuzhiyun * and Markus Pargmann, Pengutronix 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/dts-v1/; 8*4882a593Smuzhiyun#include "imx27.dtsi" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun model = "Phytec pca100"; 12*4882a593Smuzhiyun compatible = "phytec,imx27-pca100", "fsl,imx27"; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun memory@a0000000 { 15*4882a593Smuzhiyun device_type = "memory"; 16*4882a593Smuzhiyun reg = <0xa0000000 0x08000000>; /* 128MB */ 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun}; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun&cspi1 { 21*4882a593Smuzhiyun cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>, 22*4882a593Smuzhiyun <&gpio4 27 GPIO_ACTIVE_LOW>; 23*4882a593Smuzhiyun status = "okay"; 24*4882a593Smuzhiyun}; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun&fec { 27*4882a593Smuzhiyun pinctrl-names = "default"; 28*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_fec1>; 29*4882a593Smuzhiyun status = "okay"; 30*4882a593Smuzhiyun}; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun&i2c2 { 33*4882a593Smuzhiyun pinctrl-names = "default"; 34*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c2>; 35*4882a593Smuzhiyun status = "okay"; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun at24@52 { 38*4882a593Smuzhiyun compatible = "atmel,24c32"; 39*4882a593Smuzhiyun pagesize = <32>; 40*4882a593Smuzhiyun reg = <0x52>; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun}; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun&iomuxc { 45*4882a593Smuzhiyun imx27-phycard-s-som { 46*4882a593Smuzhiyun pinctrl_fec1: fec1grp { 47*4882a593Smuzhiyun fsl,pins = < 48*4882a593Smuzhiyun MX27_PAD_SD3_CMD__FEC_TXD0 0x0 49*4882a593Smuzhiyun MX27_PAD_SD3_CLK__FEC_TXD1 0x0 50*4882a593Smuzhiyun MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 51*4882a593Smuzhiyun MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 52*4882a593Smuzhiyun MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 53*4882a593Smuzhiyun MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 54*4882a593Smuzhiyun MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 55*4882a593Smuzhiyun MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 56*4882a593Smuzhiyun MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 57*4882a593Smuzhiyun MX27_PAD_ATA_DATA7__FEC_MDC 0x0 58*4882a593Smuzhiyun MX27_PAD_ATA_DATA8__FEC_CRS 0x0 59*4882a593Smuzhiyun MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 60*4882a593Smuzhiyun MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 61*4882a593Smuzhiyun MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 62*4882a593Smuzhiyun MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 63*4882a593Smuzhiyun MX27_PAD_ATA_DATA13__FEC_COL 0x0 64*4882a593Smuzhiyun MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 65*4882a593Smuzhiyun MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 66*4882a593Smuzhiyun >; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun pinctrl_i2c2: i2c2grp { 70*4882a593Smuzhiyun fsl,pins = < 71*4882a593Smuzhiyun MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 72*4882a593Smuzhiyun MX27_PAD_I2C2_SCL__I2C2_SCL 0x0 73*4882a593Smuzhiyun >; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun pinctrl_nfc: nfcgrp { 77*4882a593Smuzhiyun fsl,pins = < 78*4882a593Smuzhiyun MX27_PAD_NFRB__NFRB 0x0 79*4882a593Smuzhiyun MX27_PAD_NFCLE__NFCLE 0x0 80*4882a593Smuzhiyun MX27_PAD_NFWP_B__NFWP_B 0x0 81*4882a593Smuzhiyun MX27_PAD_NFCE_B__NFCE_B 0x0 82*4882a593Smuzhiyun MX27_PAD_NFALE__NFALE 0x0 83*4882a593Smuzhiyun MX27_PAD_NFRE_B__NFRE_B 0x0 84*4882a593Smuzhiyun MX27_PAD_NFWE_B__NFWE_B 0x0 85*4882a593Smuzhiyun >; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun}; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun&nfc { 91*4882a593Smuzhiyun pinctrl-names = "default"; 92*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_nfc>; 93*4882a593Smuzhiyun nand-bus-width = <8>; 94*4882a593Smuzhiyun nand-ecc-mode = "hw"; 95*4882a593Smuzhiyun nand-on-flash-bbt; 96*4882a593Smuzhiyun status = "okay"; 97*4882a593Smuzhiyun}; 98