xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright 2012 Markus Pargmann, Pengutronix
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun#include "imx27-phytec-phycard-s-som.dtsi"
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun/ {
9*4882a593Smuzhiyun	model = "Phytec pca100 rapid development kit";
10*4882a593Smuzhiyun	compatible = "phytec,imx27-pca100-rdk", "phytec,imx27-pca100", "fsl,imx27";
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun	chosen {
13*4882a593Smuzhiyun		stdout-path = &uart1;
14*4882a593Smuzhiyun	};
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun	display: display {
17*4882a593Smuzhiyun		model = "Primeview-PD050VL1";
18*4882a593Smuzhiyun		bits-per-pixel = <16>;  /* non-standard but required */
19*4882a593Smuzhiyun		fsl,pcr = <0xf0c88080>;	/* non-standard but required */
20*4882a593Smuzhiyun		display-timings {
21*4882a593Smuzhiyun			native-mode = <&timing0>;
22*4882a593Smuzhiyun			timing0: 640x480 {
23*4882a593Smuzhiyun				hactive = <640>;
24*4882a593Smuzhiyun				vactive = <480>;
25*4882a593Smuzhiyun				hback-porch = <112>;
26*4882a593Smuzhiyun				hfront-porch = <36>;
27*4882a593Smuzhiyun				hsync-len = <32>;
28*4882a593Smuzhiyun				vback-porch = <33>;
29*4882a593Smuzhiyun				vfront-porch = <33>;
30*4882a593Smuzhiyun				vsync-len = <2>;
31*4882a593Smuzhiyun				clock-frequency = <25000000>;
32*4882a593Smuzhiyun			};
33*4882a593Smuzhiyun		};
34*4882a593Smuzhiyun	};
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun	regulators {
37*4882a593Smuzhiyun		compatible = "simple-bus";
38*4882a593Smuzhiyun		#address-cells = <1>;
39*4882a593Smuzhiyun		#size-cells = <0>;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun		reg_3v3: regulator@0 {
42*4882a593Smuzhiyun			compatible = "regulator-fixed";
43*4882a593Smuzhiyun			reg = <0>;
44*4882a593Smuzhiyun			regulator-name = "3V3";
45*4882a593Smuzhiyun			regulator-min-microvolt = <3300000>;
46*4882a593Smuzhiyun			regulator-max-microvolt = <3300000>;
47*4882a593Smuzhiyun			regulator-always-on;
48*4882a593Smuzhiyun		};
49*4882a593Smuzhiyun	};
50*4882a593Smuzhiyun};
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun&fb {
53*4882a593Smuzhiyun	display = <&display>;
54*4882a593Smuzhiyun	status = "okay";
55*4882a593Smuzhiyun};
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun&i2c1 {
58*4882a593Smuzhiyun	pinctrl-names = "default";
59*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c1>;
60*4882a593Smuzhiyun	status = "okay";
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun	rtc@51 {
63*4882a593Smuzhiyun		compatible = "nxp,pcf8563";
64*4882a593Smuzhiyun		reg = <0x51>;
65*4882a593Smuzhiyun	};
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun	adc@64 {
68*4882a593Smuzhiyun		compatible = "maxim,max1037";
69*4882a593Smuzhiyun		vcc-supply = <&reg_3v3>;
70*4882a593Smuzhiyun		reg = <0x64>;
71*4882a593Smuzhiyun	};
72*4882a593Smuzhiyun};
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun&iomuxc {
75*4882a593Smuzhiyun	imx27-phycard-s-rdk {
76*4882a593Smuzhiyun		pinctrl_i2c1: i2c1grp {
77*4882a593Smuzhiyun			fsl,pins = <
78*4882a593Smuzhiyun				MX27_PAD_I2C_DATA__I2C_DATA 0x0
79*4882a593Smuzhiyun				MX27_PAD_I2C_CLK__I2C_CLK 0x0
80*4882a593Smuzhiyun			>;
81*4882a593Smuzhiyun		};
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun		pinctrl_owire1: owire1grp {
84*4882a593Smuzhiyun			fsl,pins = <
85*4882a593Smuzhiyun				MX27_PAD_RTCK__OWIRE 0x0
86*4882a593Smuzhiyun			>;
87*4882a593Smuzhiyun		};
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun		pinctrl_sdhc2: sdhc2grp {
90*4882a593Smuzhiyun			fsl,pins = <
91*4882a593Smuzhiyun				MX27_PAD_SD2_CLK__SD2_CLK 0x0
92*4882a593Smuzhiyun				MX27_PAD_SD2_CMD__SD2_CMD 0x0
93*4882a593Smuzhiyun				MX27_PAD_SD2_D0__SD2_D0 0x0
94*4882a593Smuzhiyun				MX27_PAD_SD2_D1__SD2_D1 0x0
95*4882a593Smuzhiyun				MX27_PAD_SD2_D2__SD2_D2 0x0
96*4882a593Smuzhiyun				MX27_PAD_SD2_D3__SD2_D3 0x0
97*4882a593Smuzhiyun				MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */
98*4882a593Smuzhiyun			>;
99*4882a593Smuzhiyun		};
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun		pinctrl_uart1: uart1grp {
102*4882a593Smuzhiyun			fsl,pins = <
103*4882a593Smuzhiyun				MX27_PAD_UART1_TXD__UART1_TXD 0x0
104*4882a593Smuzhiyun				MX27_PAD_UART1_RXD__UART1_RXD 0x0
105*4882a593Smuzhiyun				MX27_PAD_UART1_CTS__UART1_CTS 0x0
106*4882a593Smuzhiyun				MX27_PAD_UART1_RTS__UART1_RTS 0x0
107*4882a593Smuzhiyun			>;
108*4882a593Smuzhiyun		};
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun		pinctrl_uart2: uart2grp {
111*4882a593Smuzhiyun			fsl,pins = <
112*4882a593Smuzhiyun				MX27_PAD_UART2_TXD__UART2_TXD 0x0
113*4882a593Smuzhiyun				MX27_PAD_UART2_RXD__UART2_RXD 0x0
114*4882a593Smuzhiyun				MX27_PAD_UART2_CTS__UART2_CTS 0x0
115*4882a593Smuzhiyun				MX27_PAD_UART2_RTS__UART2_RTS 0x0
116*4882a593Smuzhiyun			>;
117*4882a593Smuzhiyun		};
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun		pinctrl_uart3: uart3grp {
120*4882a593Smuzhiyun			fsl,pins = <
121*4882a593Smuzhiyun				MX27_PAD_UART3_TXD__UART3_TXD 0x0
122*4882a593Smuzhiyun				MX27_PAD_UART3_RXD__UART3_RXD 0x0
123*4882a593Smuzhiyun				MX27_PAD_UART3_CTS__UART3_CTS 0x0
124*4882a593Smuzhiyun				MX27_PAD_UART3_RTS__UART3_RTS 0x0
125*4882a593Smuzhiyun			>;
126*4882a593Smuzhiyun		};
127*4882a593Smuzhiyun	};
128*4882a593Smuzhiyun};
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun&owire {
131*4882a593Smuzhiyun	pinctrl-names = "default";
132*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_owire1>;
133*4882a593Smuzhiyun	status = "okay";
134*4882a593Smuzhiyun};
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun&sdhci2 {
137*4882a593Smuzhiyun	pinctrl-names = "default";
138*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_sdhc2>;
139*4882a593Smuzhiyun	cd-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
140*4882a593Smuzhiyun	status = "okay";
141*4882a593Smuzhiyun};
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun&uart1 {
144*4882a593Smuzhiyun	uart-has-rtscts;
145*4882a593Smuzhiyun	pinctrl-names = "default";
146*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart1>;
147*4882a593Smuzhiyun	status = "okay";
148*4882a593Smuzhiyun};
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun&uart2 {
151*4882a593Smuzhiyun	uart-has-rtscts;
152*4882a593Smuzhiyun	pinctrl-names = "default";
153*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart2>;
154*4882a593Smuzhiyun	status = "okay";
155*4882a593Smuzhiyun};
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun&uart3 {
158*4882a593Smuzhiyun	uart-has-rtscts;
159*4882a593Smuzhiyun	pinctrl-names = "default";
160*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart3>;
161*4882a593Smuzhiyun	status = "okay";
162*4882a593Smuzhiyun};
163