xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun#include "imx27-eukrea-cpuimx27.dtsi"
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun/ {
9*4882a593Smuzhiyun	model = "Eukrea MBIMXSD27";
10*4882a593Smuzhiyun	compatible = "eukrea,mbimxsd27-baseboard", "eukrea,cpuimx27", "fsl,imx27";
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun	display0: CMO-QVGA {
13*4882a593Smuzhiyun		model = "CMO-QVGA";
14*4882a593Smuzhiyun		bits-per-pixel = <16>;
15*4882a593Smuzhiyun		fsl,pcr = <0xfad08b80>;
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun		display-timings {
18*4882a593Smuzhiyun			native-mode = <&timing0>;
19*4882a593Smuzhiyun			timing0: 320x240 {
20*4882a593Smuzhiyun				clock-frequency = <6500000>;
21*4882a593Smuzhiyun				hactive = <320>;
22*4882a593Smuzhiyun				vactive = <240>;
23*4882a593Smuzhiyun				hback-porch = <20>;
24*4882a593Smuzhiyun				hsync-len = <30>;
25*4882a593Smuzhiyun				hfront-porch = <38>;
26*4882a593Smuzhiyun				vback-porch = <4>;
27*4882a593Smuzhiyun				vsync-len = <3>;
28*4882a593Smuzhiyun				vfront-porch = <15>;
29*4882a593Smuzhiyun			};
30*4882a593Smuzhiyun		};
31*4882a593Smuzhiyun	};
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun	backlight {
34*4882a593Smuzhiyun		compatible = "gpio-backlight";
35*4882a593Smuzhiyun		pinctrl-names = "default";
36*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_backlight>;
37*4882a593Smuzhiyun		gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
38*4882a593Smuzhiyun	};
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun	leds {
41*4882a593Smuzhiyun		compatible = "gpio-leds";
42*4882a593Smuzhiyun		pinctrl-names = "default";
43*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_gpioleds>;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun		led1 {
46*4882a593Smuzhiyun			label = "system::live";
47*4882a593Smuzhiyun			gpios = <&gpio6 16 GPIO_ACTIVE_LOW>;
48*4882a593Smuzhiyun			linux,default-trigger = "heartbeat";
49*4882a593Smuzhiyun		};
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun		led2 {
52*4882a593Smuzhiyun			label = "system::user";
53*4882a593Smuzhiyun			gpios = <&gpio6 19 GPIO_ACTIVE_LOW>;
54*4882a593Smuzhiyun		};
55*4882a593Smuzhiyun	};
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun	regulators {
58*4882a593Smuzhiyun		#address-cells = <1>;
59*4882a593Smuzhiyun		#size-cells = <0>;
60*4882a593Smuzhiyun		compatible = "simple-bus";
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun		reg_lcd: regulator@0 {
63*4882a593Smuzhiyun			pinctrl-names = "default";
64*4882a593Smuzhiyun			pinctrl-0 = <&pinctrl_lcdreg>;
65*4882a593Smuzhiyun			compatible = "regulator-fixed";
66*4882a593Smuzhiyun			reg = <0>;
67*4882a593Smuzhiyun			regulator-name = "LCD";
68*4882a593Smuzhiyun			regulator-min-microvolt = <5000000>;
69*4882a593Smuzhiyun			regulator-max-microvolt = <5000000>;
70*4882a593Smuzhiyun			gpio = <&gpio1 25 GPIO_ACTIVE_HIGH>;
71*4882a593Smuzhiyun			enable-active-high;
72*4882a593Smuzhiyun		};
73*4882a593Smuzhiyun	};
74*4882a593Smuzhiyun};
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun&cspi1 {
77*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_cspi1>;
78*4882a593Smuzhiyun	cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
79*4882a593Smuzhiyun	status = "okay";
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun	ads7846@0 {
82*4882a593Smuzhiyun		compatible = "ti,ads7846";
83*4882a593Smuzhiyun		pinctrl-names = "default";
84*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_touch>;
85*4882a593Smuzhiyun		reg = <0>;
86*4882a593Smuzhiyun		interrupts = <&gpio4 25 IRQ_TYPE_LEVEL_LOW>;
87*4882a593Smuzhiyun		spi-cpol;
88*4882a593Smuzhiyun		spi-max-frequency = <1500000>;
89*4882a593Smuzhiyun		ti,keep-vref-on;
90*4882a593Smuzhiyun	};
91*4882a593Smuzhiyun};
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun&fb {
94*4882a593Smuzhiyun	pinctrl-names = "default";
95*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_imxfb>;
96*4882a593Smuzhiyun	display = <&display0>;
97*4882a593Smuzhiyun	lcd-supply = <&reg_lcd>;
98*4882a593Smuzhiyun	fsl,dmacr = <0x00040060>;
99*4882a593Smuzhiyun	fsl,lscr1 = <0x00120300>;
100*4882a593Smuzhiyun	fsl,lpccr = <0x00a903ff>;
101*4882a593Smuzhiyun	status = "okay";
102*4882a593Smuzhiyun};
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun&i2c1 {
105*4882a593Smuzhiyun	codec: codec@1a {
106*4882a593Smuzhiyun		compatible = "ti,tlv320aic23";
107*4882a593Smuzhiyun		reg = <0x1a>;
108*4882a593Smuzhiyun	};
109*4882a593Smuzhiyun};
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun&kpp {
112*4882a593Smuzhiyun	linux,keymap = <
113*4882a593Smuzhiyun		MATRIX_KEY(0, 0, KEY_UP)
114*4882a593Smuzhiyun		MATRIX_KEY(0, 1, KEY_DOWN)
115*4882a593Smuzhiyun		MATRIX_KEY(1, 0, KEY_RIGHT)
116*4882a593Smuzhiyun		MATRIX_KEY(1, 1, KEY_LEFT)
117*4882a593Smuzhiyun	>;
118*4882a593Smuzhiyun	status = "okay";
119*4882a593Smuzhiyun};
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun&sdhci1 {
122*4882a593Smuzhiyun	pinctrl-names = "default";
123*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_sdhc1>;
124*4882a593Smuzhiyun	bus-width = <4>;
125*4882a593Smuzhiyun	status = "okay";
126*4882a593Smuzhiyun};
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun&ssi1 {
129*4882a593Smuzhiyun	pinctrl-names = "default";
130*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_ssi1>;
131*4882a593Smuzhiyun	codec-handle = <&codec>;
132*4882a593Smuzhiyun	status = "okay";
133*4882a593Smuzhiyun};
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun&uart1 {
136*4882a593Smuzhiyun	uart-has-rtscts;
137*4882a593Smuzhiyun	pinctrl-names = "default";
138*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart1>;
139*4882a593Smuzhiyun	status = "okay";
140*4882a593Smuzhiyun};
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun&uart2 {
143*4882a593Smuzhiyun	uart-has-rtscts;
144*4882a593Smuzhiyun	pinctrl-names = "default";
145*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart2>;
146*4882a593Smuzhiyun	status = "okay";
147*4882a593Smuzhiyun};
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun&uart3 {
150*4882a593Smuzhiyun	uart-has-rtscts;
151*4882a593Smuzhiyun	pinctrl-names = "default";
152*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart3>;
153*4882a593Smuzhiyun	status = "okay";
154*4882a593Smuzhiyun};
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun&iomuxc {
157*4882a593Smuzhiyun	imx27-eukrea-cpuimx27-baseboard {
158*4882a593Smuzhiyun		pinctrl_cspi1: cspi1grp {
159*4882a593Smuzhiyun			fsl,pins = <
160*4882a593Smuzhiyun				MX27_PAD_CSPI1_MISO__CSPI1_MISO	0x0
161*4882a593Smuzhiyun				MX27_PAD_CSPI1_MOSI__CSPI1_MOSI	0x0
162*4882a593Smuzhiyun				MX27_PAD_CSPI1_SCLK__CSPI1_SCLK	0x0
163*4882a593Smuzhiyun				MX27_PAD_CSPI1_SS0__GPIO4_28	0x0 /* CS0 */
164*4882a593Smuzhiyun			>;
165*4882a593Smuzhiyun		};
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun		pinctrl_backlight: backlightgrp {
168*4882a593Smuzhiyun			fsl,pins = <
169*4882a593Smuzhiyun				MX27_PAD_PWMO__GPIO5_5		0x0
170*4882a593Smuzhiyun			>;
171*4882a593Smuzhiyun		};
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun		pinctrl_gpioleds: gpioledsgrp {
174*4882a593Smuzhiyun			fsl,pins = <
175*4882a593Smuzhiyun				MX27_PAD_PC_PWRON__GPIO6_16	0x0
176*4882a593Smuzhiyun				MX27_PAD_PC_CD2_B__GPIO6_19	0x0
177*4882a593Smuzhiyun			>;
178*4882a593Smuzhiyun		};
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun		pinctrl_imxfb: imxfbgrp {
181*4882a593Smuzhiyun			fsl,pins = <
182*4882a593Smuzhiyun				MX27_PAD_LD0__LD0		0x0
183*4882a593Smuzhiyun				MX27_PAD_LD1__LD1		0x0
184*4882a593Smuzhiyun				MX27_PAD_LD2__LD2		0x0
185*4882a593Smuzhiyun				MX27_PAD_LD3__LD3		0x0
186*4882a593Smuzhiyun				MX27_PAD_LD4__LD4		0x0
187*4882a593Smuzhiyun				MX27_PAD_LD5__LD5		0x0
188*4882a593Smuzhiyun				MX27_PAD_LD6__LD6		0x0
189*4882a593Smuzhiyun				MX27_PAD_LD7__LD7		0x0
190*4882a593Smuzhiyun				MX27_PAD_LD8__LD8		0x0
191*4882a593Smuzhiyun				MX27_PAD_LD9__LD9		0x0
192*4882a593Smuzhiyun				MX27_PAD_LD10__LD10		0x0
193*4882a593Smuzhiyun				MX27_PAD_LD11__LD11		0x0
194*4882a593Smuzhiyun				MX27_PAD_LD12__LD12		0x0
195*4882a593Smuzhiyun				MX27_PAD_LD13__LD13		0x0
196*4882a593Smuzhiyun				MX27_PAD_LD14__LD14		0x0
197*4882a593Smuzhiyun				MX27_PAD_LD15__LD15		0x0
198*4882a593Smuzhiyun				MX27_PAD_LD16__LD16		0x0
199*4882a593Smuzhiyun				MX27_PAD_LD17__LD17		0x0
200*4882a593Smuzhiyun				MX27_PAD_CONTRAST__CONTRAST	0x0
201*4882a593Smuzhiyun				MX27_PAD_OE_ACD__OE_ACD		0x0
202*4882a593Smuzhiyun				MX27_PAD_HSYNC__HSYNC		0x0
203*4882a593Smuzhiyun				MX27_PAD_VSYNC__VSYNC		0x0
204*4882a593Smuzhiyun			>;
205*4882a593Smuzhiyun		};
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun		pinctrl_lcdreg: lcdreggrp {
208*4882a593Smuzhiyun			fsl,pins = <
209*4882a593Smuzhiyun				MX27_PAD_CLS__GPIO1_25		0x0
210*4882a593Smuzhiyun			>;
211*4882a593Smuzhiyun		};
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun		pinctrl_sdhc1: sdhc1grp {
214*4882a593Smuzhiyun			fsl,pins = <
215*4882a593Smuzhiyun				MX27_PAD_SD1_CLK__SD1_CLK	0x0
216*4882a593Smuzhiyun				MX27_PAD_SD1_CMD__SD1_CMD	0x0
217*4882a593Smuzhiyun				MX27_PAD_SD1_D0__SD1_D0		0x0
218*4882a593Smuzhiyun				MX27_PAD_SD1_D1__SD1_D1		0x0
219*4882a593Smuzhiyun				MX27_PAD_SD1_D2__SD1_D2		0x0
220*4882a593Smuzhiyun				MX27_PAD_SD1_D3__SD1_D3		0x0
221*4882a593Smuzhiyun			>;
222*4882a593Smuzhiyun		};
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun		pinctrl_ssi1: ssi1grp {
225*4882a593Smuzhiyun			fsl,pins = <
226*4882a593Smuzhiyun				MX27_PAD_SSI4_CLK__SSI4_CLK	0x0
227*4882a593Smuzhiyun				MX27_PAD_SSI4_FS__SSI4_FS	0x0
228*4882a593Smuzhiyun				MX27_PAD_SSI4_RXDAT__SSI4_RXDAT	0x1
229*4882a593Smuzhiyun				MX27_PAD_SSI4_TXDAT__SSI4_TXDAT	0x1
230*4882a593Smuzhiyun			>;
231*4882a593Smuzhiyun		};
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun		pinctrl_touch: touchgrp {
234*4882a593Smuzhiyun			fsl,pins = <
235*4882a593Smuzhiyun				MX27_PAD_CSPI1_RDY__GPIO4_25	0x0 /* IRQ */
236*4882a593Smuzhiyun			>;
237*4882a593Smuzhiyun		};
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun		pinctrl_uart1: uart1grp {
240*4882a593Smuzhiyun			fsl,pins = <
241*4882a593Smuzhiyun				MX27_PAD_UART1_TXD__UART1_TXD	0x0
242*4882a593Smuzhiyun				MX27_PAD_UART1_RXD__UART1_RXD	0x0
243*4882a593Smuzhiyun				MX27_PAD_UART1_CTS__UART1_CTS	0x0
244*4882a593Smuzhiyun				MX27_PAD_UART1_RTS__UART1_RTS	0x0
245*4882a593Smuzhiyun			>;
246*4882a593Smuzhiyun		};
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun		pinctrl_uart2: uart2grp {
249*4882a593Smuzhiyun			fsl,pins = <
250*4882a593Smuzhiyun				MX27_PAD_UART2_TXD__UART2_TXD	0x0
251*4882a593Smuzhiyun				MX27_PAD_UART2_RXD__UART2_RXD	0x0
252*4882a593Smuzhiyun				MX27_PAD_UART2_CTS__UART2_CTS	0x0
253*4882a593Smuzhiyun				MX27_PAD_UART2_RTS__UART2_RTS	0x0
254*4882a593Smuzhiyun			>;
255*4882a593Smuzhiyun		};
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun		pinctrl_uart3: uart3grp {
258*4882a593Smuzhiyun			fsl,pins = <
259*4882a593Smuzhiyun				MX27_PAD_UART3_TXD__UART3_TXD	0x0
260*4882a593Smuzhiyun				MX27_PAD_UART3_RXD__UART3_RXD	0x0
261*4882a593Smuzhiyun				MX27_PAD_UART3_CTS__UART3_CTS	0x0
262*4882a593Smuzhiyun				MX27_PAD_UART3_RTS__UART3_RTS	0x0
263*4882a593Smuzhiyun			>;
264*4882a593Smuzhiyun		};
265*4882a593Smuzhiyun	};
266*4882a593Smuzhiyun};
267