xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun/dts-v1/;
7*4882a593Smuzhiyun#include "imx27.dtsi"
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun/ {
10*4882a593Smuzhiyun	model = "Eukrea CPUIMX27";
11*4882a593Smuzhiyun	compatible = "eukrea,cpuimx27", "fsl,imx27";
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun	memory@a0000000 {
14*4882a593Smuzhiyun		device_type = "memory";
15*4882a593Smuzhiyun		reg = <0xa0000000 0x04000000>;
16*4882a593Smuzhiyun	};
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun	clk14745600: clk-uart {
19*4882a593Smuzhiyun		compatible = "fixed-clock";
20*4882a593Smuzhiyun		#clock-cells = <0>;
21*4882a593Smuzhiyun		clock-frequency = <14745600>;
22*4882a593Smuzhiyun	};
23*4882a593Smuzhiyun};
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun&fec {
26*4882a593Smuzhiyun	pinctrl-names = "default";
27*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_fec>;
28*4882a593Smuzhiyun	status = "okay";
29*4882a593Smuzhiyun};
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun&i2c1 {
32*4882a593Smuzhiyun	pinctrl-names = "default";
33*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c1>;
34*4882a593Smuzhiyun	status = "okay";
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun	pcf8563@51 {
37*4882a593Smuzhiyun		compatible = "nxp,pcf8563";
38*4882a593Smuzhiyun		reg = <0x51>;
39*4882a593Smuzhiyun	};
40*4882a593Smuzhiyun};
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun&nfc {
43*4882a593Smuzhiyun	pinctrl-names = "default";
44*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_nfc>;
45*4882a593Smuzhiyun	nand-bus-width = <8>;
46*4882a593Smuzhiyun	nand-ecc-mode = "hw";
47*4882a593Smuzhiyun	nand-on-flash-bbt;
48*4882a593Smuzhiyun	status = "okay";
49*4882a593Smuzhiyun};
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun&owire {
52*4882a593Smuzhiyun	pinctrl-names = "default";
53*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_owire>;
54*4882a593Smuzhiyun	status = "okay";
55*4882a593Smuzhiyun};
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun&sdhci2 {
58*4882a593Smuzhiyun	pinctrl-names = "default";
59*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_sdhc2>;
60*4882a593Smuzhiyun	bus-width = <4>;
61*4882a593Smuzhiyun	non-removable;
62*4882a593Smuzhiyun	status = "okay";
63*4882a593Smuzhiyun};
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun&uart4 {
66*4882a593Smuzhiyun	pinctrl-names = "default";
67*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart4>;
68*4882a593Smuzhiyun	uart-has-rtscts;
69*4882a593Smuzhiyun	status = "okay";
70*4882a593Smuzhiyun};
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun&usbh2 {
73*4882a593Smuzhiyun	pinctrl-names = "default";
74*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usbh2>;
75*4882a593Smuzhiyun	dr_mode = "host";
76*4882a593Smuzhiyun	phy_type = "ulpi";
77*4882a593Smuzhiyun	disable-over-current;
78*4882a593Smuzhiyun	status = "okay";
79*4882a593Smuzhiyun};
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun&usbotg {
82*4882a593Smuzhiyun	pinctrl-names = "default";
83*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usbotg>;
84*4882a593Smuzhiyun	dr_mode = "otg";
85*4882a593Smuzhiyun	phy_type = "ulpi";
86*4882a593Smuzhiyun	disable-over-current;
87*4882a593Smuzhiyun	status = "okay";
88*4882a593Smuzhiyun};
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun&weim {
91*4882a593Smuzhiyun	status = "okay";
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun	nor: nor@0,0 {
94*4882a593Smuzhiyun		#address-cells = <1>;
95*4882a593Smuzhiyun		#size-cells = <1>;
96*4882a593Smuzhiyun		compatible = "cfi-flash";
97*4882a593Smuzhiyun		reg = <0 0x00000000 0x04000000>;
98*4882a593Smuzhiyun		bank-width = <2>;
99*4882a593Smuzhiyun		linux,mtd-name = "physmap-flash.0";
100*4882a593Smuzhiyun		fsl,weim-cs-timing = <0x00008f03 0xa0330d01 0x002208c0>;
101*4882a593Smuzhiyun	};
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun	uart8250@3,200000 {
104*4882a593Smuzhiyun		pinctrl-names = "default";
105*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_uart8250_1>;
106*4882a593Smuzhiyun		compatible = "ns8250";
107*4882a593Smuzhiyun		clocks = <&clk14745600>;
108*4882a593Smuzhiyun		fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
109*4882a593Smuzhiyun		interrupts = <&gpio2 23 IRQ_TYPE_LEVEL_LOW>;
110*4882a593Smuzhiyun		reg = <3 0x200000 0x1000>;
111*4882a593Smuzhiyun		reg-shift = <1>;
112*4882a593Smuzhiyun		reg-io-width = <1>;
113*4882a593Smuzhiyun		no-loopback-test;
114*4882a593Smuzhiyun	};
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun	uart8250@3,400000 {
117*4882a593Smuzhiyun		pinctrl-names = "default";
118*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_uart8250_2>;
119*4882a593Smuzhiyun		compatible = "ns8250";
120*4882a593Smuzhiyun		clocks = <&clk14745600>;
121*4882a593Smuzhiyun		fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
122*4882a593Smuzhiyun		interrupts = <&gpio2 22 IRQ_TYPE_LEVEL_LOW>;
123*4882a593Smuzhiyun		reg = <3 0x400000 0x1000>;
124*4882a593Smuzhiyun		reg-shift = <1>;
125*4882a593Smuzhiyun		reg-io-width = <1>;
126*4882a593Smuzhiyun		no-loopback-test;
127*4882a593Smuzhiyun	};
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun	uart8250@3,800000 {
130*4882a593Smuzhiyun		pinctrl-names = "default";
131*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_uart8250_3>;
132*4882a593Smuzhiyun		compatible = "ns8250";
133*4882a593Smuzhiyun		clocks = <&clk14745600>;
134*4882a593Smuzhiyun		fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
135*4882a593Smuzhiyun		interrupts = <&gpio2 27 IRQ_TYPE_LEVEL_LOW>;
136*4882a593Smuzhiyun		reg = <3 0x800000 0x1000>;
137*4882a593Smuzhiyun		reg-shift = <1>;
138*4882a593Smuzhiyun		reg-io-width = <1>;
139*4882a593Smuzhiyun		no-loopback-test;
140*4882a593Smuzhiyun	};
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun	uart8250@3,1000000 {
143*4882a593Smuzhiyun		pinctrl-names = "default";
144*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_uart8250_4>;
145*4882a593Smuzhiyun		compatible = "ns8250";
146*4882a593Smuzhiyun		clocks = <&clk14745600>;
147*4882a593Smuzhiyun		fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
148*4882a593Smuzhiyun		interrupts = <&gpio2 30 IRQ_TYPE_LEVEL_LOW>;
149*4882a593Smuzhiyun		reg = <3 0x1000000 0x1000>;
150*4882a593Smuzhiyun		reg-shift = <1>;
151*4882a593Smuzhiyun		reg-io-width = <1>;
152*4882a593Smuzhiyun		no-loopback-test;
153*4882a593Smuzhiyun	};
154*4882a593Smuzhiyun};
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun&iomuxc {
157*4882a593Smuzhiyun	imx27-eukrea-cpuimx27 {
158*4882a593Smuzhiyun		pinctrl_fec: fecgrp {
159*4882a593Smuzhiyun			fsl,pins = <
160*4882a593Smuzhiyun				MX27_PAD_SD3_CMD__FEC_TXD0		0x0
161*4882a593Smuzhiyun				MX27_PAD_SD3_CLK__FEC_TXD1		0x0
162*4882a593Smuzhiyun				MX27_PAD_ATA_DATA0__FEC_TXD2		0x0
163*4882a593Smuzhiyun				MX27_PAD_ATA_DATA1__FEC_TXD3		0x0
164*4882a593Smuzhiyun				MX27_PAD_ATA_DATA2__FEC_RX_ER		0x0
165*4882a593Smuzhiyun				MX27_PAD_ATA_DATA3__FEC_RXD1		0x0
166*4882a593Smuzhiyun				MX27_PAD_ATA_DATA4__FEC_RXD2		0x0
167*4882a593Smuzhiyun				MX27_PAD_ATA_DATA5__FEC_RXD3		0x0
168*4882a593Smuzhiyun				MX27_PAD_ATA_DATA6__FEC_MDIO		0x0
169*4882a593Smuzhiyun				MX27_PAD_ATA_DATA7__FEC_MDC		0x0
170*4882a593Smuzhiyun				MX27_PAD_ATA_DATA8__FEC_CRS		0x0
171*4882a593Smuzhiyun				MX27_PAD_ATA_DATA9__FEC_TX_CLK		0x0
172*4882a593Smuzhiyun				MX27_PAD_ATA_DATA10__FEC_RXD0		0x0
173*4882a593Smuzhiyun				MX27_PAD_ATA_DATA11__FEC_RX_DV		0x0
174*4882a593Smuzhiyun				MX27_PAD_ATA_DATA12__FEC_RX_CLK		0x0
175*4882a593Smuzhiyun				MX27_PAD_ATA_DATA13__FEC_COL		0x0
176*4882a593Smuzhiyun				MX27_PAD_ATA_DATA14__FEC_TX_ER		0x0
177*4882a593Smuzhiyun				MX27_PAD_ATA_DATA15__FEC_TX_EN		0x0
178*4882a593Smuzhiyun			>;
179*4882a593Smuzhiyun		};
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun		pinctrl_i2c1: i2c1grp {
182*4882a593Smuzhiyun			fsl,pins = <
183*4882a593Smuzhiyun				MX27_PAD_I2C_DATA__I2C_DATA		0x0
184*4882a593Smuzhiyun				MX27_PAD_I2C_CLK__I2C_CLK		0x0
185*4882a593Smuzhiyun			>;
186*4882a593Smuzhiyun		};
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun		pinctrl_nfc: nfcgrp {
189*4882a593Smuzhiyun			fsl,pins = <
190*4882a593Smuzhiyun				MX27_PAD_NFRB__NFRB			0x0
191*4882a593Smuzhiyun				MX27_PAD_NFCLE__NFCLE			0x0
192*4882a593Smuzhiyun				MX27_PAD_NFWP_B__NFWP_B			0x0
193*4882a593Smuzhiyun				MX27_PAD_NFCE_B__NFCE_B			0x0
194*4882a593Smuzhiyun				MX27_PAD_NFALE__NFALE			0x0
195*4882a593Smuzhiyun				MX27_PAD_NFRE_B__NFRE_B			0x0
196*4882a593Smuzhiyun				MX27_PAD_NFWE_B__NFWE_B			0x0
197*4882a593Smuzhiyun			>;
198*4882a593Smuzhiyun		};
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun		pinctrl_owire: owiregrp {
201*4882a593Smuzhiyun			fsl,pins = <
202*4882a593Smuzhiyun				MX27_PAD_RTCK__OWIRE			0x0
203*4882a593Smuzhiyun			>;
204*4882a593Smuzhiyun		};
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun		pinctrl_sdhc2: sdhc2grp {
207*4882a593Smuzhiyun			fsl,pins = <
208*4882a593Smuzhiyun				MX27_PAD_SD2_CLK__SD2_CLK		0x0
209*4882a593Smuzhiyun				MX27_PAD_SD2_CMD__SD2_CMD		0x0
210*4882a593Smuzhiyun				MX27_PAD_SD2_D0__SD2_D0			0x0
211*4882a593Smuzhiyun				MX27_PAD_SD2_D1__SD2_D1			0x0
212*4882a593Smuzhiyun				MX27_PAD_SD2_D2__SD2_D2			0x0
213*4882a593Smuzhiyun				MX27_PAD_SD2_D3__SD2_D3			0x0
214*4882a593Smuzhiyun			>;
215*4882a593Smuzhiyun		};
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun		pinctrl_uart4: uart4grp {
218*4882a593Smuzhiyun			fsl,pins = <
219*4882a593Smuzhiyun				MX27_PAD_USBH1_TXDM__UART4_TXD		0x0
220*4882a593Smuzhiyun				MX27_PAD_USBH1_RXDP__UART4_RXD		0x0
221*4882a593Smuzhiyun				MX27_PAD_USBH1_TXDP__UART4_CTS		0x0
222*4882a593Smuzhiyun				MX27_PAD_USBH1_FS__UART4_RTS		0x0
223*4882a593Smuzhiyun			>;
224*4882a593Smuzhiyun		};
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun		pinctrl_uart8250_1: uart82501grp {
227*4882a593Smuzhiyun			fsl,pins = <
228*4882a593Smuzhiyun				MX27_PAD_USB_PWR__GPIO2_23		0x0
229*4882a593Smuzhiyun			>;
230*4882a593Smuzhiyun		};
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun		pinctrl_uart8250_2: uart82502grp {
233*4882a593Smuzhiyun			fsl,pins = <
234*4882a593Smuzhiyun				MX27_PAD_USBH1_SUSP__GPIO2_22		0x0
235*4882a593Smuzhiyun			>;
236*4882a593Smuzhiyun		};
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun		pinctrl_uart8250_3: uart82503grp {
239*4882a593Smuzhiyun			fsl,pins = <
240*4882a593Smuzhiyun				MX27_PAD_USBH1_OE_B__GPIO2_27		0x0
241*4882a593Smuzhiyun			>;
242*4882a593Smuzhiyun		};
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun		pinctrl_uart8250_4: uart82504grp {
245*4882a593Smuzhiyun			fsl,pins = <
246*4882a593Smuzhiyun				MX27_PAD_USBH1_RXDM__GPIO2_30		0x0
247*4882a593Smuzhiyun			>;
248*4882a593Smuzhiyun		};
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun		pinctrl_usbh2: usbh2grp {
251*4882a593Smuzhiyun			fsl,pins = <
252*4882a593Smuzhiyun				MX27_PAD_USBH2_CLK__USBH2_CLK		0x0
253*4882a593Smuzhiyun				MX27_PAD_USBH2_DIR__USBH2_DIR		0x0
254*4882a593Smuzhiyun				MX27_PAD_USBH2_NXT__USBH2_NXT		0x0
255*4882a593Smuzhiyun				MX27_PAD_USBH2_STP__USBH2_STP		0x0
256*4882a593Smuzhiyun				MX27_PAD_CSPI2_SCLK__USBH2_DATA0	0x0
257*4882a593Smuzhiyun				MX27_PAD_CSPI2_MOSI__USBH2_DATA1	0x0
258*4882a593Smuzhiyun				MX27_PAD_CSPI2_MISO__USBH2_DATA2	0x0
259*4882a593Smuzhiyun				MX27_PAD_CSPI2_SS1__USBH2_DATA3		0x0
260*4882a593Smuzhiyun				MX27_PAD_CSPI2_SS2__USBH2_DATA4		0x0
261*4882a593Smuzhiyun				MX27_PAD_CSPI1_SS2__USBH2_DATA5		0x0
262*4882a593Smuzhiyun				MX27_PAD_CSPI2_SS0__USBH2_DATA6		0x0
263*4882a593Smuzhiyun				MX27_PAD_USBH2_DATA7__USBH2_DATA7	0x0
264*4882a593Smuzhiyun			>;
265*4882a593Smuzhiyun		};
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun		pinctrl_usbotg: usbotggrp {
268*4882a593Smuzhiyun			fsl,pins = <
269*4882a593Smuzhiyun				MX27_PAD_USBOTG_CLK__USBOTG_CLK		0x0
270*4882a593Smuzhiyun				MX27_PAD_USBOTG_DIR__USBOTG_DIR		0x0
271*4882a593Smuzhiyun				MX27_PAD_USBOTG_NXT__USBOTG_NXT		0x0
272*4882a593Smuzhiyun				MX27_PAD_USBOTG_STP__USBOTG_STP		0x0
273*4882a593Smuzhiyun				MX27_PAD_USBOTG_DATA0__USBOTG_DATA0	0x0
274*4882a593Smuzhiyun				MX27_PAD_USBOTG_DATA1__USBOTG_DATA1	0x0
275*4882a593Smuzhiyun				MX27_PAD_USBOTG_DATA2__USBOTG_DATA2	0x0
276*4882a593Smuzhiyun				MX27_PAD_USBOTG_DATA3__USBOTG_DATA3	0x0
277*4882a593Smuzhiyun				MX27_PAD_USBOTG_DATA4__USBOTG_DATA4	0x0
278*4882a593Smuzhiyun				MX27_PAD_USBOTG_DATA5__USBOTG_DATA5	0x0
279*4882a593Smuzhiyun				MX27_PAD_USBOTG_DATA6__USBOTG_DATA6	0x0
280*4882a593Smuzhiyun				MX27_PAD_USBOTG_DATA7__USBOTG_DATA7	0x0
281*4882a593Smuzhiyun			>;
282*4882a593Smuzhiyun		};
283*4882a593Smuzhiyun	};
284*4882a593Smuzhiyun};
285