1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright 2013 Armadeus Systems - <support@armadeus.com> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/* APF27Dev is a docking board for the APF27 SOM */ 7*4882a593Smuzhiyun#include "imx27-apf27.dts" 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/ { 10*4882a593Smuzhiyun model = "Armadeus Systems APF27Dev docking/development board"; 11*4882a593Smuzhiyun compatible = "armadeus,imx27-apf27dev", "armadeus,imx27-apf27", "fsl,imx27"; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun display: display { 14*4882a593Smuzhiyun model = "Chimei-LW700AT9003"; 15*4882a593Smuzhiyun bits-per-pixel = <16>; /* non-standard but required */ 16*4882a593Smuzhiyun fsl,pcr = <0xfae80083>; /* non-standard but required */ 17*4882a593Smuzhiyun display-timings { 18*4882a593Smuzhiyun native-mode = <&timing0>; 19*4882a593Smuzhiyun timing0: 800x480 { 20*4882a593Smuzhiyun clock-frequency = <33000033>; 21*4882a593Smuzhiyun hactive = <800>; 22*4882a593Smuzhiyun vactive = <480>; 23*4882a593Smuzhiyun hback-porch = <96>; 24*4882a593Smuzhiyun hfront-porch = <96>; 25*4882a593Smuzhiyun vback-porch = <20>; 26*4882a593Smuzhiyun vfront-porch = <21>; 27*4882a593Smuzhiyun hsync-len = <64>; 28*4882a593Smuzhiyun vsync-len = <4>; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun gpio-keys { 34*4882a593Smuzhiyun compatible = "gpio-keys"; 35*4882a593Smuzhiyun pinctrl-names = "default"; 36*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_gpio_keys>; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun user-key { 39*4882a593Smuzhiyun label = "user"; 40*4882a593Smuzhiyun gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; 41*4882a593Smuzhiyun linux,code = <276>; /* BTN_EXTRA */ 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun leds { 46*4882a593Smuzhiyun compatible = "gpio-leds"; 47*4882a593Smuzhiyun pinctrl-names = "default"; 48*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_gpio_leds>; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun user { 51*4882a593Smuzhiyun label = "Heartbeat"; 52*4882a593Smuzhiyun gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>; 53*4882a593Smuzhiyun linux,default-trigger = "heartbeat"; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun regulators { 58*4882a593Smuzhiyun compatible = "simple-bus"; 59*4882a593Smuzhiyun #address-cells = <1>; 60*4882a593Smuzhiyun #size-cells = <0>; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun reg_max5821: regulator@0 { 63*4882a593Smuzhiyun compatible = "regulator-fixed"; 64*4882a593Smuzhiyun reg = <0>; 65*4882a593Smuzhiyun regulator-name = "max5821-reg"; 66*4882a593Smuzhiyun regulator-min-microvolt = <2500000>; 67*4882a593Smuzhiyun regulator-max-microvolt = <2500000>; 68*4882a593Smuzhiyun regulator-always-on; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun}; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun&cspi1 { 74*4882a593Smuzhiyun cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; 75*4882a593Smuzhiyun pinctrl-names = "default"; 76*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_cspi1 &pinctrl_cspi1_cs>; 77*4882a593Smuzhiyun status = "okay"; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun adc@0 { 80*4882a593Smuzhiyun compatible = "maxim,max1027"; 81*4882a593Smuzhiyun reg = <0>; 82*4882a593Smuzhiyun interrupt-parent = <&gpio5>; 83*4882a593Smuzhiyun interrupts = <15 IRQ_TYPE_EDGE_FALLING>; 84*4882a593Smuzhiyun pinctrl-names = "default"; 85*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_max1027>; 86*4882a593Smuzhiyun spi-max-frequency = <10000000>; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun}; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun&cspi2 { 91*4882a593Smuzhiyun cs-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>, 92*4882a593Smuzhiyun <&gpio4 27 GPIO_ACTIVE_LOW>, 93*4882a593Smuzhiyun <&gpio2 17 GPIO_ACTIVE_LOW>; 94*4882a593Smuzhiyun pinctrl-names = "default"; 95*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_cspi2 &pinctrl_cspi2_cs>; 96*4882a593Smuzhiyun status = "okay"; 97*4882a593Smuzhiyun}; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun&fb { 100*4882a593Smuzhiyun display = <&display>; 101*4882a593Smuzhiyun fsl,dmacr = <0x00020010>; 102*4882a593Smuzhiyun pinctrl-names = "default"; 103*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_imxfb1>; 104*4882a593Smuzhiyun status = "okay"; 105*4882a593Smuzhiyun}; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun&i2c1 { 108*4882a593Smuzhiyun clock-frequency = <400000>; 109*4882a593Smuzhiyun pinctrl-names = "default"; 110*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c1>; 111*4882a593Smuzhiyun status = "okay"; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun rtc@68 { 114*4882a593Smuzhiyun compatible = "dallas,ds1374"; 115*4882a593Smuzhiyun reg = <0x68>; 116*4882a593Smuzhiyun }; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun max5821@38 { 119*4882a593Smuzhiyun compatible = "maxim,max5821"; 120*4882a593Smuzhiyun reg = <0x38>; 121*4882a593Smuzhiyun vref-supply = <®_max5821>; 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun}; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun&i2c2 { 126*4882a593Smuzhiyun pinctrl-names = "default"; 127*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c2>; 128*4882a593Smuzhiyun status = "okay"; 129*4882a593Smuzhiyun}; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun&iomuxc { 132*4882a593Smuzhiyun imx27-apf27dev { 133*4882a593Smuzhiyun pinctrl_cspi1: cspi1grp { 134*4882a593Smuzhiyun fsl,pins = < 135*4882a593Smuzhiyun MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0 136*4882a593Smuzhiyun MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 137*4882a593Smuzhiyun MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0 138*4882a593Smuzhiyun >; 139*4882a593Smuzhiyun }; 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun pinctrl_cspi1_cs: cspi1csgrp { 142*4882a593Smuzhiyun fsl,pins = <MX27_PAD_CSPI1_SS0__GPIO4_28 0x0>; 143*4882a593Smuzhiyun }; 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun pinctrl_cspi2: cspi2grp { 146*4882a593Smuzhiyun fsl,pins = < 147*4882a593Smuzhiyun MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0 148*4882a593Smuzhiyun MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0 149*4882a593Smuzhiyun MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0 150*4882a593Smuzhiyun >; 151*4882a593Smuzhiyun }; 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun pinctrl_cspi2_cs: cspi2csgrp { 154*4882a593Smuzhiyun fsl,pins = < 155*4882a593Smuzhiyun MX27_PAD_CSI_D5__GPIO2_17 0x0 156*4882a593Smuzhiyun MX27_PAD_CSPI2_SS0__GPIO4_21 0x0 157*4882a593Smuzhiyun MX27_PAD_CSPI1_SS1__GPIO4_27 0x0 158*4882a593Smuzhiyun >; 159*4882a593Smuzhiyun }; 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun pinctrl_gpio_leds: gpioledsgrp { 162*4882a593Smuzhiyun fsl,pins = <MX27_PAD_PC_VS1__GPIO6_14 0x0>; 163*4882a593Smuzhiyun }; 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun pinctrl_gpio_keys: gpiokeysgrp { 166*4882a593Smuzhiyun fsl,pins = <MX27_PAD_PC_VS2__GPIO6_13 0x0>; 167*4882a593Smuzhiyun }; 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun pinctrl_imxfb1: imxfbgrp { 170*4882a593Smuzhiyun fsl,pins = < 171*4882a593Smuzhiyun MX27_PAD_CLS__CLS 0x0 172*4882a593Smuzhiyun MX27_PAD_CONTRAST__CONTRAST 0x0 173*4882a593Smuzhiyun MX27_PAD_LD0__LD0 0x0 174*4882a593Smuzhiyun MX27_PAD_LD1__LD1 0x0 175*4882a593Smuzhiyun MX27_PAD_LD2__LD2 0x0 176*4882a593Smuzhiyun MX27_PAD_LD3__LD3 0x0 177*4882a593Smuzhiyun MX27_PAD_LD4__LD4 0x0 178*4882a593Smuzhiyun MX27_PAD_LD5__LD5 0x0 179*4882a593Smuzhiyun MX27_PAD_LD6__LD6 0x0 180*4882a593Smuzhiyun MX27_PAD_LD7__LD7 0x0 181*4882a593Smuzhiyun MX27_PAD_LD8__LD8 0x0 182*4882a593Smuzhiyun MX27_PAD_LD9__LD9 0x0 183*4882a593Smuzhiyun MX27_PAD_LD10__LD10 0x0 184*4882a593Smuzhiyun MX27_PAD_LD11__LD11 0x0 185*4882a593Smuzhiyun MX27_PAD_LD12__LD12 0x0 186*4882a593Smuzhiyun MX27_PAD_LD13__LD13 0x0 187*4882a593Smuzhiyun MX27_PAD_LD14__LD14 0x0 188*4882a593Smuzhiyun MX27_PAD_LD15__LD15 0x0 189*4882a593Smuzhiyun MX27_PAD_LD16__LD16 0x0 190*4882a593Smuzhiyun MX27_PAD_LD17__LD17 0x0 191*4882a593Smuzhiyun MX27_PAD_LSCLK__LSCLK 0x0 192*4882a593Smuzhiyun MX27_PAD_OE_ACD__OE_ACD 0x0 193*4882a593Smuzhiyun MX27_PAD_PS__PS 0x0 194*4882a593Smuzhiyun MX27_PAD_REV__REV 0x0 195*4882a593Smuzhiyun MX27_PAD_SPL_SPR__SPL_SPR 0x0 196*4882a593Smuzhiyun MX27_PAD_HSYNC__HSYNC 0x0 197*4882a593Smuzhiyun MX27_PAD_VSYNC__VSYNC 0x0 198*4882a593Smuzhiyun >; 199*4882a593Smuzhiyun }; 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun pinctrl_i2c1: i2c1grp { 202*4882a593Smuzhiyun fsl,pins = < 203*4882a593Smuzhiyun MX27_PAD_I2C_DATA__I2C_DATA 0x0 204*4882a593Smuzhiyun MX27_PAD_I2C_CLK__I2C_CLK 0x0 205*4882a593Smuzhiyun >; 206*4882a593Smuzhiyun }; 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun pinctrl_i2c2: i2c2grp { 209*4882a593Smuzhiyun fsl,pins = < 210*4882a593Smuzhiyun MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 211*4882a593Smuzhiyun MX27_PAD_I2C2_SCL__I2C2_SCL 0x0 212*4882a593Smuzhiyun >; 213*4882a593Smuzhiyun }; 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun pinctrl_max1027: max1027 { 216*4882a593Smuzhiyun fsl,pins = < 217*4882a593Smuzhiyun MX27_PAD_UART1_CTS__GPIO5_14 0x0 /* CNVST */ 218*4882a593Smuzhiyun MX27_PAD_UART1_RTS__GPIO5_15 0x0 /* EOC */ 219*4882a593Smuzhiyun >; 220*4882a593Smuzhiyun }; 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun pinctrl_pwm: pwmgrp { 223*4882a593Smuzhiyun fsl,pins = < 224*4882a593Smuzhiyun MX27_PAD_PWMO__PWMO 0x0 225*4882a593Smuzhiyun >; 226*4882a593Smuzhiyun }; 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun pinctrl_sdhc2: sdhc2grp { 229*4882a593Smuzhiyun fsl,pins = < 230*4882a593Smuzhiyun MX27_PAD_SD2_CLK__SD2_CLK 0x0 231*4882a593Smuzhiyun MX27_PAD_SD2_CMD__SD2_CMD 0x0 232*4882a593Smuzhiyun MX27_PAD_SD2_D0__SD2_D0 0x0 233*4882a593Smuzhiyun MX27_PAD_SD2_D1__SD2_D1 0x0 234*4882a593Smuzhiyun MX27_PAD_SD2_D2__SD2_D2 0x0 235*4882a593Smuzhiyun MX27_PAD_SD2_D3__SD2_D3 0x0 236*4882a593Smuzhiyun >; 237*4882a593Smuzhiyun }; 238*4882a593Smuzhiyun 239*4882a593Smuzhiyun pinctrl_sdhc2_cd: sdhc2cdgrp { 240*4882a593Smuzhiyun fsl,pins = <MX27_PAD_TOUT__GPIO3_14 0x0>; 241*4882a593Smuzhiyun }; 242*4882a593Smuzhiyun }; 243*4882a593Smuzhiyun}; 244*4882a593Smuzhiyun 245*4882a593Smuzhiyun&sdhci2 { 246*4882a593Smuzhiyun bus-width = <4>; 247*4882a593Smuzhiyun cd-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; 248*4882a593Smuzhiyun pinctrl-names = "default"; 249*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_sdhc2 &pinctrl_sdhc2_cd>; 250*4882a593Smuzhiyun status = "okay"; 251*4882a593Smuzhiyun}; 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun&pwm { 254*4882a593Smuzhiyun pinctrl-names = "default"; 255*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pwm>; 256*4882a593Smuzhiyun}; 257