1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0+ 2*4882a593Smuzhiyun// 3*4882a593Smuzhiyun// Copyright 2013 Freescale Semiconductor, Inc. 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun/dts-v1/; 6*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 7*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 8*4882a593Smuzhiyun#include "imx25.dtsi" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun model = "Freescale i.MX25 Product Development Kit"; 12*4882a593Smuzhiyun compatible = "fsl,imx25-pdk", "fsl,imx25"; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun memory@80000000 { 15*4882a593Smuzhiyun device_type = "memory"; 16*4882a593Smuzhiyun reg = <0x80000000 0x4000000>; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun regulators { 20*4882a593Smuzhiyun compatible = "simple-bus"; 21*4882a593Smuzhiyun #address-cells = <1>; 22*4882a593Smuzhiyun #size-cells = <0>; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun reg_fec_3v3: regulator@0 { 25*4882a593Smuzhiyun compatible = "regulator-fixed"; 26*4882a593Smuzhiyun reg = <0>; 27*4882a593Smuzhiyun regulator-name = "fec-3v3"; 28*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 29*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 30*4882a593Smuzhiyun gpio = <&gpio2 3 0>; 31*4882a593Smuzhiyun enable-active-high; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun reg_2p5v: regulator@1 { 35*4882a593Smuzhiyun compatible = "regulator-fixed"; 36*4882a593Smuzhiyun reg = <1>; 37*4882a593Smuzhiyun regulator-name = "2P5V"; 38*4882a593Smuzhiyun regulator-min-microvolt = <2500000>; 39*4882a593Smuzhiyun regulator-max-microvolt = <2500000>; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun reg_3p3v: regulator@2 { 43*4882a593Smuzhiyun compatible = "regulator-fixed"; 44*4882a593Smuzhiyun reg = <2>; 45*4882a593Smuzhiyun regulator-name = "3P3V"; 46*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 47*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun reg_can_3v3: regulator@3 { 51*4882a593Smuzhiyun compatible = "regulator-fixed"; 52*4882a593Smuzhiyun reg = <3>; 53*4882a593Smuzhiyun regulator-name = "can-3v3"; 54*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 55*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 56*4882a593Smuzhiyun gpio = <&gpio4 6 0>; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun sound { 61*4882a593Smuzhiyun compatible = "fsl,imx25-pdk-sgtl5000", 62*4882a593Smuzhiyun "fsl,imx-audio-sgtl5000"; 63*4882a593Smuzhiyun model = "imx25-pdk-sgtl5000"; 64*4882a593Smuzhiyun ssi-controller = <&ssi1>; 65*4882a593Smuzhiyun audio-codec = <&codec>; 66*4882a593Smuzhiyun audio-routing = 67*4882a593Smuzhiyun "MIC_IN", "Mic Jack", 68*4882a593Smuzhiyun "Mic Jack", "Mic Bias", 69*4882a593Smuzhiyun "Headphone Jack", "HP_OUT"; 70*4882a593Smuzhiyun mux-int-port = <1>; 71*4882a593Smuzhiyun mux-ext-port = <4>; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun wvga: display { 75*4882a593Smuzhiyun model = "CLAA057VC01CW"; 76*4882a593Smuzhiyun bits-per-pixel = <16>; 77*4882a593Smuzhiyun fsl,pcr = <0xfa208b80>; 78*4882a593Smuzhiyun bus-width = <18>; 79*4882a593Smuzhiyun display-timings { 80*4882a593Smuzhiyun native-mode = <&wvga_timings>; 81*4882a593Smuzhiyun wvga_timings: 640x480 { 82*4882a593Smuzhiyun hactive = <640>; 83*4882a593Smuzhiyun vactive = <480>; 84*4882a593Smuzhiyun hback-porch = <45>; 85*4882a593Smuzhiyun hfront-porch = <114>; 86*4882a593Smuzhiyun hsync-len = <1>; 87*4882a593Smuzhiyun vback-porch = <33>; 88*4882a593Smuzhiyun vfront-porch = <11>; 89*4882a593Smuzhiyun vsync-len = <1>; 90*4882a593Smuzhiyun clock-frequency = <25200000>; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun}; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun&audmux { 97*4882a593Smuzhiyun pinctrl-names = "default"; 98*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_audmux>; 99*4882a593Smuzhiyun status = "okay"; 100*4882a593Smuzhiyun}; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun&can1 { 103*4882a593Smuzhiyun pinctrl-names = "default"; 104*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_can1>; 105*4882a593Smuzhiyun xceiver-supply = <®_can_3v3>; 106*4882a593Smuzhiyun status = "okay"; 107*4882a593Smuzhiyun}; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun&esdhc1 { 110*4882a593Smuzhiyun pinctrl-names = "default"; 111*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_esdhc1>; 112*4882a593Smuzhiyun cd-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; 113*4882a593Smuzhiyun wp-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>; 114*4882a593Smuzhiyun status = "okay"; 115*4882a593Smuzhiyun}; 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun&fec { 118*4882a593Smuzhiyun phy-mode = "rmii"; 119*4882a593Smuzhiyun pinctrl-names = "default"; 120*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_fec>; 121*4882a593Smuzhiyun phy-supply = <®_fec_3v3>; 122*4882a593Smuzhiyun phy-reset-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; 123*4882a593Smuzhiyun status = "okay"; 124*4882a593Smuzhiyun}; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun&i2c1 { 127*4882a593Smuzhiyun clock-frequency = <100000>; 128*4882a593Smuzhiyun pinctrl-names = "default"; 129*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c1>; 130*4882a593Smuzhiyun status = "okay"; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun codec: sgtl5000@a { 133*4882a593Smuzhiyun compatible = "fsl,sgtl5000"; 134*4882a593Smuzhiyun reg = <0x0a>; 135*4882a593Smuzhiyun clocks = <&clks 129>; 136*4882a593Smuzhiyun VDDA-supply = <®_2p5v>; 137*4882a593Smuzhiyun VDDIO-supply = <®_3p3v>; 138*4882a593Smuzhiyun }; 139*4882a593Smuzhiyun}; 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun&iomuxc { 142*4882a593Smuzhiyun imx25-pdk { 143*4882a593Smuzhiyun pinctrl_audmux: audmuxgrp { 144*4882a593Smuzhiyun fsl,pins = < 145*4882a593Smuzhiyun MX25_PAD_RW__AUD4_TXFS 0xe0 146*4882a593Smuzhiyun MX25_PAD_OE__AUD4_TXC 0xe0 147*4882a593Smuzhiyun MX25_PAD_EB0__AUD4_TXD 0xe0 148*4882a593Smuzhiyun MX25_PAD_EB1__AUD4_RXD 0xe0 149*4882a593Smuzhiyun >; 150*4882a593Smuzhiyun }; 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun pinctrl_can1: can1grp { 153*4882a593Smuzhiyun fsl,pins = < 154*4882a593Smuzhiyun MX25_PAD_GPIO_A__CAN1_TX 0x0 155*4882a593Smuzhiyun MX25_PAD_GPIO_B__CAN1_RX 0x0 156*4882a593Smuzhiyun MX25_PAD_D14__GPIO_4_6 0x80000000 157*4882a593Smuzhiyun >; 158*4882a593Smuzhiyun }; 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun pinctrl_esdhc1: esdhc1grp { 161*4882a593Smuzhiyun fsl,pins = < 162*4882a593Smuzhiyun MX25_PAD_SD1_CMD__ESDHC1_CMD 0x80000000 163*4882a593Smuzhiyun MX25_PAD_SD1_CLK__ESDHC1_CLK 0x80000000 164*4882a593Smuzhiyun MX25_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000 165*4882a593Smuzhiyun MX25_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000 166*4882a593Smuzhiyun MX25_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000 167*4882a593Smuzhiyun MX25_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000 168*4882a593Smuzhiyun MX25_PAD_A14__GPIO_2_0 0x80000000 169*4882a593Smuzhiyun MX25_PAD_A15__GPIO_2_1 0x80000000 170*4882a593Smuzhiyun >; 171*4882a593Smuzhiyun }; 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun pinctrl_fec: fecgrp { 174*4882a593Smuzhiyun fsl,pins = < 175*4882a593Smuzhiyun MX25_PAD_FEC_MDC__FEC_MDC 0x80000000 176*4882a593Smuzhiyun MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0 177*4882a593Smuzhiyun MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000 178*4882a593Smuzhiyun MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000 179*4882a593Smuzhiyun MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 180*4882a593Smuzhiyun MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000 181*4882a593Smuzhiyun MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000 182*4882a593Smuzhiyun MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 183*4882a593Smuzhiyun MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0 184*4882a593Smuzhiyun MX25_PAD_A17__GPIO_2_3 0x80000000 185*4882a593Smuzhiyun MX25_PAD_D12__GPIO_4_8 0x80000000 186*4882a593Smuzhiyun >; 187*4882a593Smuzhiyun }; 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun pinctrl_i2c1: i2c1grp { 190*4882a593Smuzhiyun fsl,pins = < 191*4882a593Smuzhiyun MX25_PAD_I2C1_CLK__I2C1_CLK 0x80000000 192*4882a593Smuzhiyun MX25_PAD_I2C1_DAT__I2C1_DAT 0x80000000 193*4882a593Smuzhiyun >; 194*4882a593Smuzhiyun }; 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun pinctrl_kpp: kppgrp { 197*4882a593Smuzhiyun fsl,pins = < 198*4882a593Smuzhiyun MX25_PAD_KPP_ROW0__KPP_ROW0 0x80000000 199*4882a593Smuzhiyun MX25_PAD_KPP_ROW1__KPP_ROW1 0x80000000 200*4882a593Smuzhiyun MX25_PAD_KPP_ROW2__KPP_ROW2 0x80000000 201*4882a593Smuzhiyun MX25_PAD_KPP_ROW3__KPP_ROW3 0x80000000 202*4882a593Smuzhiyun MX25_PAD_KPP_COL0__KPP_COL0 0x80000000 203*4882a593Smuzhiyun MX25_PAD_KPP_COL1__KPP_COL1 0x80000000 204*4882a593Smuzhiyun MX25_PAD_KPP_COL2__KPP_COL2 0x80000000 205*4882a593Smuzhiyun MX25_PAD_KPP_COL3__KPP_COL3 0x80000000 206*4882a593Smuzhiyun >; 207*4882a593Smuzhiyun }; 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun pinctrl_lcd: lcdgrp { 210*4882a593Smuzhiyun fsl,pins = < 211*4882a593Smuzhiyun MX25_PAD_LD0__LD0 0xe0 212*4882a593Smuzhiyun MX25_PAD_LD1__LD1 0xe0 213*4882a593Smuzhiyun MX25_PAD_LD2__LD2 0xe0 214*4882a593Smuzhiyun MX25_PAD_LD3__LD3 0xe0 215*4882a593Smuzhiyun MX25_PAD_LD4__LD4 0xe0 216*4882a593Smuzhiyun MX25_PAD_LD5__LD5 0xe0 217*4882a593Smuzhiyun MX25_PAD_LD6__LD6 0xe0 218*4882a593Smuzhiyun MX25_PAD_LD7__LD7 0xe0 219*4882a593Smuzhiyun MX25_PAD_LD8__LD8 0xe0 220*4882a593Smuzhiyun MX25_PAD_LD9__LD9 0xe0 221*4882a593Smuzhiyun MX25_PAD_LD10__LD10 0xe0 222*4882a593Smuzhiyun MX25_PAD_LD11__LD11 0xe0 223*4882a593Smuzhiyun MX25_PAD_LD12__LD12 0xe0 224*4882a593Smuzhiyun MX25_PAD_LD13__LD13 0xe0 225*4882a593Smuzhiyun MX25_PAD_LD14__LD14 0xe0 226*4882a593Smuzhiyun MX25_PAD_LD15__LD15 0xe0 227*4882a593Smuzhiyun MX25_PAD_GPIO_E__LD16 0xe0 228*4882a593Smuzhiyun MX25_PAD_GPIO_F__LD17 0xe0 229*4882a593Smuzhiyun MX25_PAD_HSYNC__HSYNC 0xe0 230*4882a593Smuzhiyun MX25_PAD_VSYNC__VSYNC 0xe0 231*4882a593Smuzhiyun MX25_PAD_LSCLK__LSCLK 0xe0 232*4882a593Smuzhiyun MX25_PAD_OE_ACD__OE_ACD 0xe0 233*4882a593Smuzhiyun MX25_PAD_CONTRAST__CONTRAST 0xe0 234*4882a593Smuzhiyun >; 235*4882a593Smuzhiyun }; 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun pinctrl_uart1: uart1grp { 238*4882a593Smuzhiyun fsl,pins = < 239*4882a593Smuzhiyun MX25_PAD_UART1_RTS__UART1_RTS 0xe0 240*4882a593Smuzhiyun MX25_PAD_UART1_CTS__UART1_CTS 0xe0 241*4882a593Smuzhiyun MX25_PAD_UART1_TXD__UART1_TXD 0x80000000 242*4882a593Smuzhiyun MX25_PAD_UART1_RXD__UART1_RXD 0xc0 243*4882a593Smuzhiyun >; 244*4882a593Smuzhiyun }; 245*4882a593Smuzhiyun }; 246*4882a593Smuzhiyun}; 247*4882a593Smuzhiyun 248*4882a593Smuzhiyun&lcdc { 249*4882a593Smuzhiyun display = <&wvga>; 250*4882a593Smuzhiyun fsl,lpccr = <0x00a903ff>; 251*4882a593Smuzhiyun fsl,lscr1 = <0x00120300>; 252*4882a593Smuzhiyun fsl,dmacr = <0x00020010>; 253*4882a593Smuzhiyun pinctrl-names = "default"; 254*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_lcd>; 255*4882a593Smuzhiyun status = "okay"; 256*4882a593Smuzhiyun}; 257*4882a593Smuzhiyun 258*4882a593Smuzhiyun&nfc { 259*4882a593Smuzhiyun nand-on-flash-bbt; 260*4882a593Smuzhiyun status = "okay"; 261*4882a593Smuzhiyun}; 262*4882a593Smuzhiyun 263*4882a593Smuzhiyun&kpp { 264*4882a593Smuzhiyun pinctrl-names = "default"; 265*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_kpp>; 266*4882a593Smuzhiyun linux,keymap = < 267*4882a593Smuzhiyun MATRIX_KEY(0x0, 0x0, KEY_UP) 268*4882a593Smuzhiyun MATRIX_KEY(0x0, 0x1, KEY_DOWN) 269*4882a593Smuzhiyun MATRIX_KEY(0x0, 0x2, KEY_VOLUMEDOWN) 270*4882a593Smuzhiyun MATRIX_KEY(0x0, 0x3, KEY_HOME) 271*4882a593Smuzhiyun MATRIX_KEY(0x1, 0x0, KEY_RIGHT) 272*4882a593Smuzhiyun MATRIX_KEY(0x1, 0x1, KEY_LEFT) 273*4882a593Smuzhiyun MATRIX_KEY(0x1, 0x2, KEY_ENTER) 274*4882a593Smuzhiyun MATRIX_KEY(0x1, 0x3, KEY_VOLUMEUP) 275*4882a593Smuzhiyun MATRIX_KEY(0x2, 0x0, KEY_F6) 276*4882a593Smuzhiyun MATRIX_KEY(0x2, 0x1, KEY_F8) 277*4882a593Smuzhiyun MATRIX_KEY(0x2, 0x2, KEY_F9) 278*4882a593Smuzhiyun MATRIX_KEY(0x2, 0x3, KEY_F10) 279*4882a593Smuzhiyun MATRIX_KEY(0x3, 0x0, KEY_F1) 280*4882a593Smuzhiyun MATRIX_KEY(0x3, 0x1, KEY_F2) 281*4882a593Smuzhiyun MATRIX_KEY(0x3, 0x2, KEY_F3) 282*4882a593Smuzhiyun MATRIX_KEY(0x3, 0x2, KEY_POWER) 283*4882a593Smuzhiyun >; 284*4882a593Smuzhiyun status = "okay"; 285*4882a593Smuzhiyun}; 286*4882a593Smuzhiyun 287*4882a593Smuzhiyun&ssi1 { 288*4882a593Smuzhiyun status = "okay"; 289*4882a593Smuzhiyun}; 290*4882a593Smuzhiyun 291*4882a593Smuzhiyun&tsc { 292*4882a593Smuzhiyun status = "okay"; 293*4882a593Smuzhiyun}; 294*4882a593Smuzhiyun 295*4882a593Smuzhiyun&tscadc { 296*4882a593Smuzhiyun status = "okay"; 297*4882a593Smuzhiyun}; 298*4882a593Smuzhiyun 299*4882a593Smuzhiyun&uart1 { 300*4882a593Smuzhiyun pinctrl-names = "default"; 301*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart1>; 302*4882a593Smuzhiyun uart-has-rtscts; 303*4882a593Smuzhiyun status = "okay"; 304*4882a593Smuzhiyun}; 305*4882a593Smuzhiyun 306*4882a593Smuzhiyun&usbhost1 { 307*4882a593Smuzhiyun status = "okay"; 308*4882a593Smuzhiyun}; 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun&usbotg { 311*4882a593Smuzhiyun external-vbus-divider; 312*4882a593Smuzhiyun status = "okay"; 313*4882a593Smuzhiyun}; 314