1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright 2012 Sascha Hauer, Pengutronix 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun#include "imx25.dtsi" 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/ { 10*4882a593Smuzhiyun model = "Ka-Ro TX25"; 11*4882a593Smuzhiyun compatible = "karo,imx25-tx25", "fsl,imx25"; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun chosen { 14*4882a593Smuzhiyun stdout-path = &uart1; 15*4882a593Smuzhiyun }; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun regulators { 18*4882a593Smuzhiyun compatible = "simple-bus"; 19*4882a593Smuzhiyun #address-cells = <1>; 20*4882a593Smuzhiyun #size-cells = <0>; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun reg_fec_phy: regulator@0 { 23*4882a593Smuzhiyun compatible = "regulator-fixed"; 24*4882a593Smuzhiyun reg = <0>; 25*4882a593Smuzhiyun regulator-name = "fec-phy"; 26*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 27*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 28*4882a593Smuzhiyun gpio = <&gpio4 9 0>; 29*4882a593Smuzhiyun enable-active-high; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun memory@80000000 { 34*4882a593Smuzhiyun device_type = "memory"; 35*4882a593Smuzhiyun reg = <0x80000000 0x02000000 0x90000000 0x02000000>; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun}; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun&iomuxc { 40*4882a593Smuzhiyun pinctrl_uart1: uart1grp { 41*4882a593Smuzhiyun fsl,pins = < 42*4882a593Smuzhiyun MX25_PAD_UART1_TXD__UART1_TXD 0x80000000 43*4882a593Smuzhiyun MX25_PAD_UART1_RXD__UART1_RXD 0x80000000 44*4882a593Smuzhiyun MX25_PAD_UART1_CTS__UART1_CTS 0x80000000 45*4882a593Smuzhiyun MX25_PAD_UART1_RTS__UART1_RTS 0x80000000 46*4882a593Smuzhiyun >; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun pinctrl_fec: fecgrp { 50*4882a593Smuzhiyun fsl,pins = < 51*4882a593Smuzhiyun MX25_PAD_D11__GPIO_4_9 0x80000000 /* FEC PHY power on pin */ 52*4882a593Smuzhiyun MX25_PAD_D13__GPIO_4_7 0x80000000 /* FEC reset */ 53*4882a593Smuzhiyun MX25_PAD_FEC_MDC__FEC_MDC 0x80000000 54*4882a593Smuzhiyun MX25_PAD_FEC_MDIO__FEC_MDIO 0x80000000 55*4882a593Smuzhiyun MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000 56*4882a593Smuzhiyun MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000 57*4882a593Smuzhiyun MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 58*4882a593Smuzhiyun MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000 59*4882a593Smuzhiyun MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000 60*4882a593Smuzhiyun MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 61*4882a593Smuzhiyun MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x80000000 62*4882a593Smuzhiyun >; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun pinctrl_nfc: nfcgrp { 66*4882a593Smuzhiyun fsl,pins = < 67*4882a593Smuzhiyun MX25_PAD_NF_CE0__NF_CE0 0x80000000 68*4882a593Smuzhiyun MX25_PAD_NFWE_B__NFWE_B 0x80000000 69*4882a593Smuzhiyun MX25_PAD_NFRE_B__NFRE_B 0x80000000 70*4882a593Smuzhiyun MX25_PAD_NFALE__NFALE 0x80000000 71*4882a593Smuzhiyun MX25_PAD_NFCLE__NFCLE 0x80000000 72*4882a593Smuzhiyun MX25_PAD_NFWP_B__NFWP_B 0x80000000 73*4882a593Smuzhiyun MX25_PAD_NFRB__NFRB 0x80000000 74*4882a593Smuzhiyun MX25_PAD_D7__D7 0x80000000 75*4882a593Smuzhiyun MX25_PAD_D6__D6 0x80000000 76*4882a593Smuzhiyun MX25_PAD_D5__D5 0x80000000 77*4882a593Smuzhiyun MX25_PAD_D4__D4 0x80000000 78*4882a593Smuzhiyun MX25_PAD_D3__D3 0x80000000 79*4882a593Smuzhiyun MX25_PAD_D2__D2 0x80000000 80*4882a593Smuzhiyun MX25_PAD_D1__D1 0x80000000 81*4882a593Smuzhiyun MX25_PAD_D0__D0 0x80000000 82*4882a593Smuzhiyun >; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun}; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun&uart1 { 87*4882a593Smuzhiyun pinctrl-names = "default"; 88*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart1>; 89*4882a593Smuzhiyun status = "okay"; 90*4882a593Smuzhiyun}; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun&fec { 93*4882a593Smuzhiyun pinctrl-names = "default"; 94*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_fec>; 95*4882a593Smuzhiyun phy-reset-gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; 96*4882a593Smuzhiyun phy-mode = "rmii"; 97*4882a593Smuzhiyun phy-supply = <®_fec_phy>; 98*4882a593Smuzhiyun status = "okay"; 99*4882a593Smuzhiyun}; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun&nfc { 102*4882a593Smuzhiyun pinctrl-names = "default"; 103*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_nfc>; 104*4882a593Smuzhiyun nand-on-flash-bbt; 105*4882a593Smuzhiyun nand-ecc-mode = "hw"; 106*4882a593Smuzhiyun nand-bus-width = <8>; 107*4882a593Smuzhiyun status = "okay"; 108*4882a593Smuzhiyun}; 109