1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright 2013 Eukréa Electromatique <denis@eukrea.com> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 9*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 10*4882a593Smuzhiyun#include "imx25-eukrea-cpuimx25.dtsi" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun model = "Eukrea MBIMXSD25"; 14*4882a593Smuzhiyun compatible = "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25"; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun gpio_keys { 17*4882a593Smuzhiyun compatible = "gpio-keys"; 18*4882a593Smuzhiyun pinctrl-names = "default"; 19*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_gpiokeys>; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun bp1 { 22*4882a593Smuzhiyun label = "BP1"; 23*4882a593Smuzhiyun gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; 24*4882a593Smuzhiyun linux,code = <BTN_MISC>; 25*4882a593Smuzhiyun wakeup-source; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun leds { 30*4882a593Smuzhiyun compatible = "gpio-leds"; 31*4882a593Smuzhiyun pinctrl-names = "default"; 32*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_gpioled>; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun led1 { 35*4882a593Smuzhiyun label = "led1"; 36*4882a593Smuzhiyun gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; 37*4882a593Smuzhiyun linux,default-trigger = "heartbeat"; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun sound { 42*4882a593Smuzhiyun compatible = "eukrea,asoc-tlv320"; 43*4882a593Smuzhiyun eukrea,model = "imx25-eukrea-tlv320aic23"; 44*4882a593Smuzhiyun ssi-controller = <&ssi1>; 45*4882a593Smuzhiyun fsl,mux-int-port = <1>; 46*4882a593Smuzhiyun fsl,mux-ext-port = <5>; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun}; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun&audmux { 51*4882a593Smuzhiyun pinctrl-names = "default"; 52*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_audmux>; 53*4882a593Smuzhiyun status = "okay"; 54*4882a593Smuzhiyun}; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun&esdhc1 { 57*4882a593Smuzhiyun pinctrl-names = "default"; 58*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_esdhc1>; 59*4882a593Smuzhiyun cd-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; 60*4882a593Smuzhiyun status = "okay"; 61*4882a593Smuzhiyun}; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun&i2c1 { 64*4882a593Smuzhiyun tlv320aic23: codec@1a { 65*4882a593Smuzhiyun compatible = "ti,tlv320aic23"; 66*4882a593Smuzhiyun reg = <0x1a>; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun}; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun&iomuxc { 71*4882a593Smuzhiyun imx25-eukrea-mbimxsd25-baseboard { 72*4882a593Smuzhiyun pinctrl_audmux: audmuxgrp { 73*4882a593Smuzhiyun fsl,pins = < 74*4882a593Smuzhiyun MX25_PAD_KPP_COL3__AUD5_TXFS 0xe0 75*4882a593Smuzhiyun MX25_PAD_KPP_COL2__AUD5_TXC 0xe0 76*4882a593Smuzhiyun MX25_PAD_KPP_COL1__AUD5_RXD 0xe0 77*4882a593Smuzhiyun MX25_PAD_KPP_COL0__AUD5_TXD 0xe0 78*4882a593Smuzhiyun >; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun pinctrl_esdhc1: esdhc1grp { 82*4882a593Smuzhiyun fsl,pins = < 83*4882a593Smuzhiyun MX25_PAD_SD1_CMD__ESDHC1_CMD 0x400000c0 84*4882a593Smuzhiyun MX25_PAD_SD1_CLK__ESDHC1_CLK 0x400000c0 85*4882a593Smuzhiyun MX25_PAD_SD1_DATA0__ESDHC1_DAT0 0x400000c0 86*4882a593Smuzhiyun MX25_PAD_SD1_DATA1__ESDHC1_DAT1 0x400000c0 87*4882a593Smuzhiyun MX25_PAD_SD1_DATA2__ESDHC1_DAT2 0x400000c0 88*4882a593Smuzhiyun MX25_PAD_SD1_DATA3__ESDHC1_DAT3 0x400000c0 89*4882a593Smuzhiyun >; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun pinctrl_gpiokeys: gpiokeysgrp { 93*4882a593Smuzhiyun fsl,pins = <MX25_PAD_VSTBY_ACK__GPIO_3_18 0x80000000>; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun pinctrl_gpioled: gpioledgrp { 97*4882a593Smuzhiyun fsl,pins = <MX25_PAD_POWER_FAIL__GPIO_3_19 0x80000000>; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun pinctrl_lcdc: lcdcgrp { 101*4882a593Smuzhiyun fsl,pins = < 102*4882a593Smuzhiyun MX25_PAD_LD0__LD0 0x1 103*4882a593Smuzhiyun MX25_PAD_LD1__LD1 0x1 104*4882a593Smuzhiyun MX25_PAD_LD2__LD2 0x1 105*4882a593Smuzhiyun MX25_PAD_LD3__LD3 0x1 106*4882a593Smuzhiyun MX25_PAD_LD4__LD4 0x1 107*4882a593Smuzhiyun MX25_PAD_LD5__LD5 0x1 108*4882a593Smuzhiyun MX25_PAD_LD6__LD6 0x1 109*4882a593Smuzhiyun MX25_PAD_LD7__LD7 0x1 110*4882a593Smuzhiyun MX25_PAD_LD8__LD8 0x1 111*4882a593Smuzhiyun MX25_PAD_LD9__LD9 0x1 112*4882a593Smuzhiyun MX25_PAD_LD10__LD10 0x1 113*4882a593Smuzhiyun MX25_PAD_LD11__LD11 0x1 114*4882a593Smuzhiyun MX25_PAD_LD12__LD12 0x1 115*4882a593Smuzhiyun MX25_PAD_LD13__LD13 0x1 116*4882a593Smuzhiyun MX25_PAD_LD14__LD14 0x1 117*4882a593Smuzhiyun MX25_PAD_LD15__LD15 0x1 118*4882a593Smuzhiyun MX25_PAD_GPIO_E__LD16 0x1 119*4882a593Smuzhiyun MX25_PAD_GPIO_F__LD17 0x1 120*4882a593Smuzhiyun MX25_PAD_HSYNC__HSYNC 0x80000000 121*4882a593Smuzhiyun MX25_PAD_VSYNC__VSYNC 0x80000000 122*4882a593Smuzhiyun MX25_PAD_LSCLK__LSCLK 0x80000000 123*4882a593Smuzhiyun MX25_PAD_OE_ACD__OE_ACD 0x80000000 124*4882a593Smuzhiyun MX25_PAD_CONTRAST__CONTRAST 0x80000000 125*4882a593Smuzhiyun >; 126*4882a593Smuzhiyun }; 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun pinctrl_uart1: uart1grp { 129*4882a593Smuzhiyun fsl,pins = < 130*4882a593Smuzhiyun MX25_PAD_UART1_RTS__UART1_RTS 0xe0 131*4882a593Smuzhiyun MX25_PAD_UART1_CTS__UART1_CTS 0xe0 132*4882a593Smuzhiyun MX25_PAD_UART1_TXD__UART1_TXD 0x80000000 133*4882a593Smuzhiyun MX25_PAD_UART1_RXD__UART1_RXD 0xc0 134*4882a593Smuzhiyun >; 135*4882a593Smuzhiyun }; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun pinctrl_uart2: uart2grp { 138*4882a593Smuzhiyun fsl,pins = < 139*4882a593Smuzhiyun MX25_PAD_UART2_RXD__UART2_RXD 0x80000000 140*4882a593Smuzhiyun MX25_PAD_UART2_TXD__UART2_TXD 0x80000000 141*4882a593Smuzhiyun MX25_PAD_UART2_RTS__UART2_RTS 0x80000000 142*4882a593Smuzhiyun MX25_PAD_UART2_CTS__UART2_CTS 0x80000000 143*4882a593Smuzhiyun >; 144*4882a593Smuzhiyun }; 145*4882a593Smuzhiyun }; 146*4882a593Smuzhiyun}; 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun&ssi1 { 149*4882a593Smuzhiyun codec-handle = <&tlv320aic23>; 150*4882a593Smuzhiyun status = "okay"; 151*4882a593Smuzhiyun}; 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun&uart1 { 154*4882a593Smuzhiyun pinctrl-names = "default"; 155*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart1>; 156*4882a593Smuzhiyun uart-has-rtscts; 157*4882a593Smuzhiyun status = "okay"; 158*4882a593Smuzhiyun}; 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun&uart2 { 161*4882a593Smuzhiyun pinctrl-names = "default"; 162*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart2>; 163*4882a593Smuzhiyun uart-has-rtscts; 164*4882a593Smuzhiyun status = "okay"; 165*4882a593Smuzhiyun}; 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun&usbhost1 { 168*4882a593Smuzhiyun status = "okay"; 169*4882a593Smuzhiyun}; 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun&usbotg { 172*4882a593Smuzhiyun external-vbus-divider; 173*4882a593Smuzhiyun status = "okay"; 174*4882a593Smuzhiyun}; 175