1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright 2013 Eukréa Electromatique <denis@eukrea.com> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun#include "imx25.dtsi" 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/ { 9*4882a593Smuzhiyun model = "Eukrea CPUIMX25"; 10*4882a593Smuzhiyun compatible = "eukrea,cpuimx25", "fsl,imx25"; 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun memory@80000000 { 13*4882a593Smuzhiyun device_type = "memory"; 14*4882a593Smuzhiyun reg = <0x80000000 0x4000000>; /* 64M */ 15*4882a593Smuzhiyun }; 16*4882a593Smuzhiyun}; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun&fec { 19*4882a593Smuzhiyun phy-mode = "rmii"; 20*4882a593Smuzhiyun pinctrl-names = "default"; 21*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_fec>; 22*4882a593Smuzhiyun status = "okay"; 23*4882a593Smuzhiyun}; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun&i2c1 { 26*4882a593Smuzhiyun pinctrl-names = "default"; 27*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c1>; 28*4882a593Smuzhiyun status = "okay"; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun pcf8563@51 { 31*4882a593Smuzhiyun compatible = "nxp,pcf8563"; 32*4882a593Smuzhiyun reg = <0x51>; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun}; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun&iomuxc { 37*4882a593Smuzhiyun imx25-eukrea-cpuimx25 { 38*4882a593Smuzhiyun pinctrl_fec: fecgrp { 39*4882a593Smuzhiyun fsl,pins = < 40*4882a593Smuzhiyun MX25_PAD_FEC_MDC__FEC_MDC 0x80000000 41*4882a593Smuzhiyun MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0 42*4882a593Smuzhiyun MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000 43*4882a593Smuzhiyun MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000 44*4882a593Smuzhiyun MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 45*4882a593Smuzhiyun MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000 46*4882a593Smuzhiyun MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000 47*4882a593Smuzhiyun MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 48*4882a593Smuzhiyun MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0 49*4882a593Smuzhiyun >; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun pinctrl_i2c1: i2c1grp { 53*4882a593Smuzhiyun fsl,pins = < 54*4882a593Smuzhiyun MX25_PAD_I2C1_CLK__I2C1_CLK 0x80000000 55*4882a593Smuzhiyun MX25_PAD_I2C1_DAT__I2C1_DAT 0x80000000 56*4882a593Smuzhiyun >; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun}; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun&nfc { 62*4882a593Smuzhiyun nand-bus-width = <8>; 63*4882a593Smuzhiyun nand-ecc-mode = "hw"; 64*4882a593Smuzhiyun nand-on-flash-bbt; 65*4882a593Smuzhiyun status = "okay"; 66*4882a593Smuzhiyun}; 67