1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun#include "imx1.dtsi" 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/ { 10*4882a593Smuzhiyun model = "Armadeus APF9328"; 11*4882a593Smuzhiyun compatible = "armadeus,imx1-apf9328", "fsl,imx1"; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun chosen { 14*4882a593Smuzhiyun stdout-path = &uart1; 15*4882a593Smuzhiyun }; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun memory@8000000 { 18*4882a593Smuzhiyun device_type = "memory"; 19*4882a593Smuzhiyun reg = <0x08000000 0x00800000>; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun}; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun&i2c { 24*4882a593Smuzhiyun pinctrl-names = "default"; 25*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c>; 26*4882a593Smuzhiyun status = "okay"; 27*4882a593Smuzhiyun}; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun&uart1 { 30*4882a593Smuzhiyun pinctrl-names = "default"; 31*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart1>; 32*4882a593Smuzhiyun uart-has-rtscts; 33*4882a593Smuzhiyun status = "okay"; 34*4882a593Smuzhiyun}; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun&uart2 { 37*4882a593Smuzhiyun pinctrl-names = "default"; 38*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart2>; 39*4882a593Smuzhiyun uart-has-rtscts; 40*4882a593Smuzhiyun status = "okay"; 41*4882a593Smuzhiyun}; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun&weim { 44*4882a593Smuzhiyun pinctrl-names = "default"; 45*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_weim>; 46*4882a593Smuzhiyun status = "okay"; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun nor: nor@0,0 { 49*4882a593Smuzhiyun compatible = "cfi-flash"; 50*4882a593Smuzhiyun reg = <0 0x00000000 0x02000000>; 51*4882a593Smuzhiyun bank-width = <2>; 52*4882a593Smuzhiyun fsl,weim-cs-timing = <0x00330e04 0x00000d01>; 53*4882a593Smuzhiyun #address-cells = <1>; 54*4882a593Smuzhiyun #size-cells = <1>; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun eth: eth@4,c00000 { 58*4882a593Smuzhiyun pinctrl-names = "default"; 59*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_eth>; 60*4882a593Smuzhiyun compatible = "davicom,dm9000"; 61*4882a593Smuzhiyun reg = < 62*4882a593Smuzhiyun 4 0x00c00000 0x2 63*4882a593Smuzhiyun 4 0x00c00002 0x2 64*4882a593Smuzhiyun >; 65*4882a593Smuzhiyun interrupt-parent = <&gpio2>; 66*4882a593Smuzhiyun interrupts = <14 IRQ_TYPE_LEVEL_LOW>; 67*4882a593Smuzhiyun fsl,weim-cs-timing = <0x0000c700 0x19190d01>; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun}; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun&iomuxc { 72*4882a593Smuzhiyun imx1-apf9328 { 73*4882a593Smuzhiyun pinctrl_eth: ethgrp { 74*4882a593Smuzhiyun fsl,pins = < 75*4882a593Smuzhiyun MX1_PAD_SIM_SVEN__GPIO2_14 0x0 76*4882a593Smuzhiyun >; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun pinctrl_i2c: i2cgrp { 80*4882a593Smuzhiyun fsl,pins = < 81*4882a593Smuzhiyun MX1_PAD_I2C_SCL__I2C_SCL 0x0 82*4882a593Smuzhiyun MX1_PAD_I2C_SDA__I2C_SDA 0x0 83*4882a593Smuzhiyun >; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun pinctrl_uart1: uart1grp { 87*4882a593Smuzhiyun fsl,pins = < 88*4882a593Smuzhiyun MX1_PAD_UART1_TXD__UART1_TXD 0x0 89*4882a593Smuzhiyun MX1_PAD_UART1_RXD__UART1_RXD 0x0 90*4882a593Smuzhiyun MX1_PAD_UART1_CTS__UART1_CTS 0x0 91*4882a593Smuzhiyun MX1_PAD_UART1_RTS__UART1_RTS 0x0 92*4882a593Smuzhiyun >; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun pinctrl_uart2: uart2grp { 96*4882a593Smuzhiyun fsl,pins = < 97*4882a593Smuzhiyun MX1_PAD_UART2_TXD__UART2_TXD 0x0 98*4882a593Smuzhiyun MX1_PAD_UART2_RXD__UART2_RXD 0x0 99*4882a593Smuzhiyun MX1_PAD_UART2_CTS__UART2_CTS 0x0 100*4882a593Smuzhiyun MX1_PAD_UART2_RTS__UART2_RTS 0x0 101*4882a593Smuzhiyun >; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun pinctrl_weim: weimgrp { 105*4882a593Smuzhiyun fsl,pins = < 106*4882a593Smuzhiyun MX1_PAD_A0__A0 0x0 107*4882a593Smuzhiyun MX1_PAD_A16__A16 0x0 108*4882a593Smuzhiyun MX1_PAD_A17__A17 0x0 109*4882a593Smuzhiyun MX1_PAD_A18__A18 0x0 110*4882a593Smuzhiyun MX1_PAD_A19__A19 0x0 111*4882a593Smuzhiyun MX1_PAD_A20__A20 0x0 112*4882a593Smuzhiyun MX1_PAD_A21__A21 0x0 113*4882a593Smuzhiyun MX1_PAD_A22__A22 0x0 114*4882a593Smuzhiyun MX1_PAD_A23__A23 0x0 115*4882a593Smuzhiyun MX1_PAD_A24__A24 0x0 116*4882a593Smuzhiyun MX1_PAD_BCLK__BCLK 0x0 117*4882a593Smuzhiyun MX1_PAD_CS4__CS4 0x0 118*4882a593Smuzhiyun MX1_PAD_DTACK__DTACK 0x0 119*4882a593Smuzhiyun MX1_PAD_ECB__ECB 0x0 120*4882a593Smuzhiyun MX1_PAD_LBA__LBA 0x0 121*4882a593Smuzhiyun >; 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun }; 124*4882a593Smuzhiyun}; 125