1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Hisilicon Ltd. HiP01 SoC 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2014 Hisilicon Ltd. 6*4882a593Smuzhiyun * Copyright (C) 2014 Huawei Ltd. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Author: Wang Long <long.wanglong@huawei.com> 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/dts-v1/; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun/* First 8KB reserved for secondary core boot */ 14*4882a593Smuzhiyun/memreserve/ 0x80000000 0x00002000; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun#include "hip01.dtsi" 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun/ { 19*4882a593Smuzhiyun model = "Hisilicon HIP01 Development Board"; 20*4882a593Smuzhiyun compatible = "hisilicon,hip01-ca9x2", "hisilicon,hip01"; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun cpus { 23*4882a593Smuzhiyun #address-cells = <1>; 24*4882a593Smuzhiyun #size-cells = <0>; 25*4882a593Smuzhiyun enable-method = "hisilicon,hip01-smp"; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun cpu@0 { 28*4882a593Smuzhiyun device_type = "cpu"; 29*4882a593Smuzhiyun compatible = "arm,cortex-a9"; 30*4882a593Smuzhiyun reg = <0>; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun cpu@1 { 34*4882a593Smuzhiyun device_type = "cpu"; 35*4882a593Smuzhiyun compatible = "arm,cortex-a9"; 36*4882a593Smuzhiyun reg = <1>; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun memory { 41*4882a593Smuzhiyun device_type = "memory"; 42*4882a593Smuzhiyun reg = <0x80000000 0x80000000>; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun}; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun&uart0 { 47*4882a593Smuzhiyun status = "okay"; 48*4882a593Smuzhiyun}; 49