xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/gr-peach-audiocamerashield.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Device Tree Source for the GR-Peach audiocamera shield expansion board
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2017 Jacopo Mondi <jacopo+renesas@jmondi.org>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun#include "r7s72100.dtsi"
9*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
10*4882a593Smuzhiyun#include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun/ {
13*4882a593Smuzhiyun	/* On-board camera clock. */
14*4882a593Smuzhiyun	camera_clk: camera_clk {
15*4882a593Smuzhiyun		compatible = "fixed-clock";
16*4882a593Smuzhiyun		#clock-cells = <0>;
17*4882a593Smuzhiyun		clock-frequency = <27000000>;
18*4882a593Smuzhiyun	};
19*4882a593Smuzhiyun};
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun&pinctrl {
22*4882a593Smuzhiyun	i2c1_pins: i2c1 {
23*4882a593Smuzhiyun		/* P1_2 as SCL; P1_3 as SDA */
24*4882a593Smuzhiyun		pinmux = <RZA1_PINMUX(1, 2, 1)>, <RZA1_PINMUX(1, 3, 1)>;
25*4882a593Smuzhiyun	};
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun	vio_pins: vio {
28*4882a593Smuzhiyun		/* CEU pins: VIO_D[0-10], VIO_VD, VIO_HD, VIO_CLK */
29*4882a593Smuzhiyun		pinmux = <RZA1_PINMUX(1, 0, 5)>, /* VIO_VD */
30*4882a593Smuzhiyun			 <RZA1_PINMUX(1, 1, 5)>, /* VIO_HD */
31*4882a593Smuzhiyun			 <RZA1_PINMUX(2, 0, 7)>, /* VIO_D0 */
32*4882a593Smuzhiyun			 <RZA1_PINMUX(2, 1, 7)>, /* VIO_D1 */
33*4882a593Smuzhiyun			 <RZA1_PINMUX(2, 2, 7)>, /* VIO_D2 */
34*4882a593Smuzhiyun			 <RZA1_PINMUX(2, 3, 7)>, /* VIO_D3 */
35*4882a593Smuzhiyun			 <RZA1_PINMUX(2, 4, 7)>, /* VIO_D4 */
36*4882a593Smuzhiyun			 <RZA1_PINMUX(2, 5, 7)>, /* VIO_D5 */
37*4882a593Smuzhiyun			 <RZA1_PINMUX(2, 6, 7)>, /* VIO_D6 */
38*4882a593Smuzhiyun			 <RZA1_PINMUX(2, 7, 7)>, /* VIO_D7 */
39*4882a593Smuzhiyun			 <RZA1_PINMUX(10, 0, 6)>; /* VIO_CLK */
40*4882a593Smuzhiyun	};
41*4882a593Smuzhiyun};
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun&i2c1 {
44*4882a593Smuzhiyun	pinctrl-names = "default";
45*4882a593Smuzhiyun	pinctrl-0 = <&i2c1_pins>;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun	status = "okay";
48*4882a593Smuzhiyun	clock-frequency = <100000>;
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun	camera@48 {
51*4882a593Smuzhiyun		compatible = "aptina,mt9v111";
52*4882a593Smuzhiyun		reg = <0x48>;
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun		clocks = <&camera_clk>;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun		port {
57*4882a593Smuzhiyun			mt9v111_out: endpoint {
58*4882a593Smuzhiyun				remote-endpoint = <&ceu_in>;
59*4882a593Smuzhiyun			};
60*4882a593Smuzhiyun		};
61*4882a593Smuzhiyun	};
62*4882a593Smuzhiyun};
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun&ceu {
65*4882a593Smuzhiyun	pinctrl-names = "default";
66*4882a593Smuzhiyun	pinctrl-0 = <&vio_pins>;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun	status = "okay";
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun	port {
71*4882a593Smuzhiyun		ceu_in: endpoint {
72*4882a593Smuzhiyun			remote-endpoint = <&mt9v111_out>;
73*4882a593Smuzhiyun		};
74*4882a593Smuzhiyun	};
75*4882a593Smuzhiyun};
76