xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/gemini-sq201.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Device Tree file for ITian Square One SQ201 NAS
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun/dts-v1/;
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun#include "gemini.dtsi"
9*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun/ {
12*4882a593Smuzhiyun	model = "ITian Square One SQ201";
13*4882a593Smuzhiyun	compatible = "itian,sq201", "cortina,gemini";
14*4882a593Smuzhiyun	#address-cells = <1>;
15*4882a593Smuzhiyun	#size-cells = <1>;
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun	memory@0 { /* 128 MB */
18*4882a593Smuzhiyun		device_type = "memory";
19*4882a593Smuzhiyun		reg = <0x00000000 0x8000000>;
20*4882a593Smuzhiyun	};
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun	chosen {
23*4882a593Smuzhiyun		bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait";
24*4882a593Smuzhiyun		stdout-path = &uart0;
25*4882a593Smuzhiyun	};
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun	gpio_keys {
28*4882a593Smuzhiyun		compatible = "gpio-keys";
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun		button-setup {
31*4882a593Smuzhiyun			debounce-interval = <100>;
32*4882a593Smuzhiyun			wakeup-source;
33*4882a593Smuzhiyun			linux,code = <KEY_SETUP>;
34*4882a593Smuzhiyun			label = "factory reset";
35*4882a593Smuzhiyun			/* Conflict with NAND flash */
36*4882a593Smuzhiyun			gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
37*4882a593Smuzhiyun		};
38*4882a593Smuzhiyun	};
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun	leds {
41*4882a593Smuzhiyun		compatible = "gpio-leds";
42*4882a593Smuzhiyun		led-green-info {
43*4882a593Smuzhiyun			label = "sq201:green:info";
44*4882a593Smuzhiyun			gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
45*4882a593Smuzhiyun			default-state = "on";
46*4882a593Smuzhiyun			linux,default-trigger = "heartbeat";
47*4882a593Smuzhiyun		};
48*4882a593Smuzhiyun		led-green-usb {
49*4882a593Smuzhiyun			label = "sq201:green:usb";
50*4882a593Smuzhiyun			gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>;
51*4882a593Smuzhiyun			default-state = "off";
52*4882a593Smuzhiyun			linux,default-trigger = "usb-host";
53*4882a593Smuzhiyun		};
54*4882a593Smuzhiyun	};
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun	mdio0: mdio {
57*4882a593Smuzhiyun		compatible = "virtual,mdio-gpio";
58*4882a593Smuzhiyun		/* Uses MDC and MDIO */
59*4882a593Smuzhiyun		gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */
60*4882a593Smuzhiyun			<&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */
61*4882a593Smuzhiyun		#address-cells = <1>;
62*4882a593Smuzhiyun		#size-cells = <0>;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun		/* This is a Marvell 88E1111 ethernet transciever */
65*4882a593Smuzhiyun		phy0: ethernet-phy@1 {
66*4882a593Smuzhiyun			reg = <1>;
67*4882a593Smuzhiyun		};
68*4882a593Smuzhiyun	};
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun	spi {
71*4882a593Smuzhiyun		compatible = "spi-gpio";
72*4882a593Smuzhiyun		#address-cells = <1>;
73*4882a593Smuzhiyun		#size-cells = <0>;
74*4882a593Smuzhiyun		/* Check pin collisions */
75*4882a593Smuzhiyun		gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>;
76*4882a593Smuzhiyun		gpio-miso = <&gpio1 30 GPIO_ACTIVE_HIGH>;
77*4882a593Smuzhiyun		gpio-mosi = <&gpio1 29 GPIO_ACTIVE_HIGH>;
78*4882a593Smuzhiyun		cs-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
79*4882a593Smuzhiyun		num-chipselects = <1>;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun		switch@0 {
82*4882a593Smuzhiyun			compatible = "vitesse,vsc7395";
83*4882a593Smuzhiyun			reg = <0>;
84*4882a593Smuzhiyun			/* Specified for 2.5 MHz or below */
85*4882a593Smuzhiyun			spi-max-frequency = <2500000>;
86*4882a593Smuzhiyun			gpio-controller;
87*4882a593Smuzhiyun			#gpio-cells = <2>;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun			ports {
90*4882a593Smuzhiyun				#address-cells = <1>;
91*4882a593Smuzhiyun				#size-cells = <0>;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun				port@0 {
94*4882a593Smuzhiyun					reg = <0>;
95*4882a593Smuzhiyun					label = "lan1";
96*4882a593Smuzhiyun				};
97*4882a593Smuzhiyun				port@1 {
98*4882a593Smuzhiyun					reg = <1>;
99*4882a593Smuzhiyun					label = "lan2";
100*4882a593Smuzhiyun				};
101*4882a593Smuzhiyun				port@2 {
102*4882a593Smuzhiyun					reg = <2>;
103*4882a593Smuzhiyun					label = "lan3";
104*4882a593Smuzhiyun				};
105*4882a593Smuzhiyun				port@3 {
106*4882a593Smuzhiyun					reg = <3>;
107*4882a593Smuzhiyun					label = "lan4";
108*4882a593Smuzhiyun				};
109*4882a593Smuzhiyun				vsc: port@6 {
110*4882a593Smuzhiyun					reg = <6>;
111*4882a593Smuzhiyun					label = "cpu";
112*4882a593Smuzhiyun					ethernet = <&gmac1>;
113*4882a593Smuzhiyun					phy-mode = "rgmii";
114*4882a593Smuzhiyun					fixed-link {
115*4882a593Smuzhiyun						speed = <1000>;
116*4882a593Smuzhiyun						full-duplex;
117*4882a593Smuzhiyun						pause;
118*4882a593Smuzhiyun					};
119*4882a593Smuzhiyun				};
120*4882a593Smuzhiyun			};
121*4882a593Smuzhiyun		};
122*4882a593Smuzhiyun	};
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun	soc {
126*4882a593Smuzhiyun		flash@30000000 {
127*4882a593Smuzhiyun			status = "okay";
128*4882a593Smuzhiyun			pinctrl-names = "enabled", "disabled";
129*4882a593Smuzhiyun			pinctrl-0 = <&pflash_default_pins>;
130*4882a593Smuzhiyun			pinctrl-1 = <&pflash_disabled_pins>;
131*4882a593Smuzhiyun			/* 16MB of flash */
132*4882a593Smuzhiyun			reg = <0x30000000 0x01000000>;
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun			partitions {
135*4882a593Smuzhiyun				compatible = "redboot-fis";
136*4882a593Smuzhiyun				/* Eraseblock at 0xfe0000 */
137*4882a593Smuzhiyun				fis-index-block = <0x1fc>;
138*4882a593Smuzhiyun			};
139*4882a593Smuzhiyun		};
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun		syscon: syscon@40000000 {
142*4882a593Smuzhiyun			pinctrl {
143*4882a593Smuzhiyun				/*
144*4882a593Smuzhiyun				 * gpio0fgrp cover line 18 used by reset button
145*4882a593Smuzhiyun				 * gpio0ggrp cover line 20 used by info LED
146*4882a593Smuzhiyun				 * gpio0hgrp cover line 21, 22 used by MDIO for Marvell PHY
147*4882a593Smuzhiyun				 * gpio0kgrp cover line 31 used by USB LED
148*4882a593Smuzhiyun				 */
149*4882a593Smuzhiyun				gpio0_default_pins: pinctrl-gpio0 {
150*4882a593Smuzhiyun					mux {
151*4882a593Smuzhiyun						function = "gpio0";
152*4882a593Smuzhiyun						groups = "gpio0fgrp",
153*4882a593Smuzhiyun						"gpio0hgrp";
154*4882a593Smuzhiyun					};
155*4882a593Smuzhiyun				};
156*4882a593Smuzhiyun				/*
157*4882a593Smuzhiyun				 * gpio0dgrp cover lines used by the SPI
158*4882a593Smuzhiyun				 * to the Vitesse G5x chip.
159*4882a593Smuzhiyun				 */
160*4882a593Smuzhiyun				gpio1_default_pins: pinctrl-gpio1 {
161*4882a593Smuzhiyun					mux {
162*4882a593Smuzhiyun						function = "gpio1";
163*4882a593Smuzhiyun						groups = "gpio1dgrp";
164*4882a593Smuzhiyun					};
165*4882a593Smuzhiyun				};
166*4882a593Smuzhiyun				/*
167*4882a593Smuzhiyun				 * These GPIO groups will be mapped in over some
168*4882a593Smuzhiyun				 * of the flash pins when the flash is not in
169*4882a593Smuzhiyun				 * active use.
170*4882a593Smuzhiyun				 */
171*4882a593Smuzhiyun				pflash_disabled_pins: pinctrl-pflash-disabled {
172*4882a593Smuzhiyun					mux {
173*4882a593Smuzhiyun						function = "gpio0";
174*4882a593Smuzhiyun						groups = "gpio0ggrp", "gpio0igrp", "gpio0jgrp",
175*4882a593Smuzhiyun							 "gpio0kgrp";
176*4882a593Smuzhiyun					};
177*4882a593Smuzhiyun				};
178*4882a593Smuzhiyun				pinctrl-gmii {
179*4882a593Smuzhiyun					mux {
180*4882a593Smuzhiyun						function = "gmii";
181*4882a593Smuzhiyun						groups = "gmii_gmac0_grp", "gmii_gmac1_grp";
182*4882a593Smuzhiyun					};
183*4882a593Smuzhiyun					/* Settings come from memory dump in PLATO */
184*4882a593Smuzhiyun					conf0 {
185*4882a593Smuzhiyun						pins = "V8 GMAC0 RXDV";
186*4882a593Smuzhiyun						skew-delay = <0>;
187*4882a593Smuzhiyun					};
188*4882a593Smuzhiyun					conf1 {
189*4882a593Smuzhiyun						pins = "Y7 GMAC0 RXC";
190*4882a593Smuzhiyun						skew-delay = <15>;
191*4882a593Smuzhiyun					};
192*4882a593Smuzhiyun					conf2 {
193*4882a593Smuzhiyun						pins = "T8 GMAC0 TXEN";
194*4882a593Smuzhiyun						skew-delay = <7>;
195*4882a593Smuzhiyun					};
196*4882a593Smuzhiyun					conf3 {
197*4882a593Smuzhiyun						pins = "U8 GMAC0 TXC";
198*4882a593Smuzhiyun						skew-delay = <10>;
199*4882a593Smuzhiyun					};
200*4882a593Smuzhiyun					conf4 {
201*4882a593Smuzhiyun						pins = "T10 GMAC1 RXDV";
202*4882a593Smuzhiyun						skew-delay = <7>;
203*4882a593Smuzhiyun					};
204*4882a593Smuzhiyun					conf5 {
205*4882a593Smuzhiyun						pins = "Y11 GMAC1 RXC";
206*4882a593Smuzhiyun						skew-delay = <8>;
207*4882a593Smuzhiyun					};
208*4882a593Smuzhiyun					conf6 {
209*4882a593Smuzhiyun						pins = "W11 GMAC1 TXEN";
210*4882a593Smuzhiyun						skew-delay = <7>;
211*4882a593Smuzhiyun					};
212*4882a593Smuzhiyun					conf7 {
213*4882a593Smuzhiyun						pins = "V11 GMAC1 TXC";
214*4882a593Smuzhiyun						skew-delay = <5>;
215*4882a593Smuzhiyun					};
216*4882a593Smuzhiyun					conf8 {
217*4882a593Smuzhiyun						/* The data lines all have default skew */
218*4882a593Smuzhiyun						pins = "W8 GMAC0 RXD0", "V9 GMAC0 RXD1",
219*4882a593Smuzhiyun						       "Y8 GMAC0 RXD2", "U9 GMAC0 RXD3",
220*4882a593Smuzhiyun						       "T7 GMAC0 TXD0", "U6 GMAC0 TXD1",
221*4882a593Smuzhiyun						       "V7 GMAC0 TXD2", "U7 GMAC0 TXD3",
222*4882a593Smuzhiyun						       "Y12 GMAC1 RXD0", "V12 GMAC1 RXD1",
223*4882a593Smuzhiyun						       "T11 GMAC1 RXD2", "W12 GMAC1 RXD3",
224*4882a593Smuzhiyun						       "U10 GMAC1 TXD0", "Y10 GMAC1 TXD1",
225*4882a593Smuzhiyun						       "W10 GMAC1 TXD2", "T9 GMAC1 TXD3";
226*4882a593Smuzhiyun						skew-delay = <7>;
227*4882a593Smuzhiyun					};
228*4882a593Smuzhiyun					/* Set up drive strength on GMAC0 and GMAC1 to 16 mA */
229*4882a593Smuzhiyun					conf9 {
230*4882a593Smuzhiyun						groups = "gmii_gmac0_grp", "gmii_gmac1_grp";
231*4882a593Smuzhiyun						drive-strength = <16>;
232*4882a593Smuzhiyun					};
233*4882a593Smuzhiyun				};
234*4882a593Smuzhiyun			};
235*4882a593Smuzhiyun		};
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun		sata: sata@46000000 {
238*4882a593Smuzhiyun			cortina,gemini-ata-muxmode = <0>;
239*4882a593Smuzhiyun			cortina,gemini-enable-sata-bridge;
240*4882a593Smuzhiyun			status = "okay";
241*4882a593Smuzhiyun		};
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun		gpio0: gpio@4d000000 {
244*4882a593Smuzhiyun			pinctrl-names = "default";
245*4882a593Smuzhiyun			pinctrl-0 = <&gpio0_default_pins>;
246*4882a593Smuzhiyun		};
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun		gpio1: gpio@4e000000 {
249*4882a593Smuzhiyun			pinctrl-names = "default";
250*4882a593Smuzhiyun			pinctrl-0 = <&gpio1_default_pins>;
251*4882a593Smuzhiyun		};
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun		pci@50000000 {
254*4882a593Smuzhiyun			status = "okay";
255*4882a593Smuzhiyun			interrupt-map-mask = <0xf800 0 0 7>;
256*4882a593Smuzhiyun			interrupt-map =
257*4882a593Smuzhiyun				<0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
258*4882a593Smuzhiyun				<0x4800 0 0 2 &pci_intc 1>,
259*4882a593Smuzhiyun				<0x4800 0 0 3 &pci_intc 2>,
260*4882a593Smuzhiyun				<0x4800 0 0 4 &pci_intc 3>,
261*4882a593Smuzhiyun				<0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
262*4882a593Smuzhiyun				<0x5000 0 0 2 &pci_intc 2>,
263*4882a593Smuzhiyun				<0x5000 0 0 3 &pci_intc 3>,
264*4882a593Smuzhiyun				<0x5000 0 0 4 &pci_intc 0>,
265*4882a593Smuzhiyun				<0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */
266*4882a593Smuzhiyun				<0x5800 0 0 2 &pci_intc 3>,
267*4882a593Smuzhiyun				<0x5800 0 0 3 &pci_intc 0>,
268*4882a593Smuzhiyun				<0x5800 0 0 4 &pci_intc 1>,
269*4882a593Smuzhiyun				<0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */
270*4882a593Smuzhiyun				<0x6000 0 0 2 &pci_intc 0>,
271*4882a593Smuzhiyun				<0x6000 0 0 3 &pci_intc 1>,
272*4882a593Smuzhiyun				<0x6000 0 0 4 &pci_intc 2>;
273*4882a593Smuzhiyun		};
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun		ethernet@60000000 {
276*4882a593Smuzhiyun			status = "okay";
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun			ethernet-port@0 {
279*4882a593Smuzhiyun				phy-mode = "rgmii";
280*4882a593Smuzhiyun				phy-handle = <&phy0>;
281*4882a593Smuzhiyun			};
282*4882a593Smuzhiyun			ethernet-port@1 {
283*4882a593Smuzhiyun				phy-mode = "rgmii";
284*4882a593Smuzhiyun				fixed-link {
285*4882a593Smuzhiyun					speed = <1000>;
286*4882a593Smuzhiyun					full-duplex;
287*4882a593Smuzhiyun					pause;
288*4882a593Smuzhiyun				};
289*4882a593Smuzhiyun			};
290*4882a593Smuzhiyun		};
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun		ide@63000000 {
293*4882a593Smuzhiyun			status = "okay";
294*4882a593Smuzhiyun		};
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun		usb@68000000 {
297*4882a593Smuzhiyun			status = "okay";
298*4882a593Smuzhiyun		};
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun		usb@69000000 {
301*4882a593Smuzhiyun			status = "okay";
302*4882a593Smuzhiyun		};
303*4882a593Smuzhiyun	};
304*4882a593Smuzhiyun};
305